Add CRMV register as required.
While at this also fix the issues with compilation failures.
- Fix the schema path.
- Fix max items in reg, interrupts properties.
- Fix indentation.
- Update examples.
Change-Id: I435ca457f3a2a60ac2c5063b7b65cfa4357ee7dd
Signed-off-by: Minghao Zhang <quic_minghao@quicinc.com>
Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
Add DT entry to enable the memory onject support for
smcinvoke.
Change-Id: I87b62b048e94e2aad2a8329b275bbd8d75ae6cc7
Signed-off-by: Amirreza Zarrabi <quic_azarrabi@quicinc.com>
Add compatible string for APQ variant on RCM platform for
Sun SoC.
Change-Id: I1d20c8b8c5f8156ae299fd2646160086859badd5
Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com>
Add bindings for QCOM AMOLED regulator which is used to configure
triple power supply for amoled displays.
This is a snapshot of the bindings taken as of qcom-6.1
commit 6f13701949ee ("dt-bindings: qpnp-amoled: Fix the IBB Spur mitigation example code")
and converted from .txt to .yaml file.
Change-Id: I51f6029f2a140e5a6d2a53d3b1a2d468a8721bfa
Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
Add new "qcom,adc5-gen4" property to flag ADC5 GEN4 channels.
Change-Id: I271b6e74d36721f6c38bd1f3d68e47bc5393b04d
Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
Add a bindings file for max31760 fan controller.
Change-Id: Id6d885d3678a6ffb1b1797b85e37dae121b66fa8
Signed-off-by: Minghao Zhang <quic_minghao@quicinc.com>
Add the device tree binding for mpm sleep counter
so that it device nodes can be added for respective
SoC where it is supported.
Change-Id: Ic503641c25a4be7121cbf00ccffe103e641cd2f8
Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
Remove the qcom,cesta-l1sub-timeout-ext-int property as its no
longer required due to recent changes in the pcie driver using the
change commit b53d4aa20ee7 ("pci: msm: Add support to enable
PCIE CESTA clkreq config").
Initially this property was intended to be used to enable the BIT(3):
PARF_CESTA_L1SUB_TIMEOUT_EXT_INT_EN field of
PCIE0_PCIE_PARF_L1SUB_CESTA_CTRL register for platforms where CESTA
is enabled and the platform is not pineapple.
Currently the pcie driver will by default set this BIT(3) when CESTA is
enabled and the qcom,pcie-clkreq-offset property is present. Since the
qcom,pcie-clkreq-offset property will not be present when CESTA
is enabled on pineapple, pcie driver will not touch the
PCIE0_PCIE_PARF_L1SUB_CESTA_CTRL register.
Pcie driver will set only the BIT(0) PARF_CESTA_CLKREQ_SEL field when
qcom,pcie-clkreq-offset property is present and CESTA is not present
which is the case of pineapple platform when CESTA is enabled. And
this case is also taken care of by the pcie driver without the need
for qcom,pcie-clkreq-offset property.
Below are the required cases that needs to be taken care of by the
pcie driver.
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| CESTA is enabled | BIT(0) set | BIT(3) set | platform |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| YES | need to set| need to set| non-pineapple |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| YES | set by | Not | pineapple |
| | default | applicable | |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| NO | NO | NO | non-pineapple |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| NO | need to | Not | pineapple |
| | unset | applicable | |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++.
Above mentioned cases are taken care by using the qcom,pcie-clkreq-offset
property in the following way.
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| CESTA is enabled | qcom,pcie-clkreq-offset | platform |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| YES | YES | non-pineapple |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| YES | NO | pineapple |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| NO | NO | non-pineapple |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| NO | YES | pineapple |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++.
Change-Id: I1bc4985be0080d295153233b0d5d4ce07e006818
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Add compatible string for ATP variant on Sun SoC.
Change-Id: Ibaa26b372af475afe291c78c57a1e32d4a76ea93
Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com>
Add snapshot of devicetree bindings from commit (bb95f5ff94:
"ARM: dts: msm: Add probe dependency to PMIC PON Log driver")
for qcedev. Update the bindings from .txt to .yaml.
Change-Id: I7e46035c6ac66c14e932c009d4a1291ec6127001
Signed-off-by: Daniel Perez-Zoghbi <quic_dperezzo@quicinc.com>
Add the bindings to describe a device node for the qmsgq gunyah
transport. This device enables communication between VMs through
gunyah message queues.
Change-Id: I4ee9b8b7d7069580a3f43eb9452b17ee13b74805
Signed-off-by: Kishore Kumar Ravi <quic_kiskum@quicinc.com>
Update the compatibility to include soccp for sun SoC.
Change-Id: I40f694364589345d62589211ddac14713e4c3b0d
Signed-off-by: Gokul krishna Krishnakumar <quic_gokukris@quicinc.com>
Document the bindings for the reboot reason driver.
Change-Id: I30dacc4f2c9ca59ed12dc94eb81b5ef39a27d187
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Update the binding information for the STMicroelectronics
touch driver, adding st_fts compatible string.
Change-Id: I78b31190d75720dd68f2b74c74fa67777fad650c
Signed-off-by: Rohith Iyer <quic_rohiiyer@quicinc.com>
Add the device_type property in the pci device tree as a mandatory
property so that the ranges property will be read correctly by
the of framework (of.c) file when pci framework is parsing the
pci device tree nodes.
Also add the qcom,cesta-l1sub-timeout-ext-int property as an
optional property for the platforms that have cesta clkreq routing
bit disabled and legacy l1ss timeout enabled by default.
The presence of this property on a cesta enabled platform will
enable routing of the L1ss timeout interrupt to cesta HW block
instead of routing it to APPS subsystem.
Change-Id: I96db05d6cd38f507c7ddba968ee65808b8263076
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
