Commit Graph

13 Commits

Author SHA1 Message Date
QCTECMDR Service
51286b910f Merge "ARM: dts: msm: Add support for Tuna7 and TunaP SoC" 2025-03-17 13:39:48 -07:00
Hrishabh Rajput
b0ed9373e7 ARM: dts: msm: Add support for Tuna7 and TunaP SoC
Add devicetree support for Tuna7 and TunaP SoC.

Change-Id: I5f94559c66f00bcb746fc05f7c445a8e2501d862
Signed-off-by: Hrishabh Rajput <quic_hrishabh@quicinc.com>
2025-03-17 13:50:32 +05:30
Sneh Mankad
54a9c53389 ARM: dts: msm: Enable idle states for tuna VMs
Enable idle states devices for virtual CPU to enter LPMs
when idle.

Change-Id: I0e03ea5ac0263a385a1ee4e79f16070826d88320
Signed-off-by: Sneh Mankad <quic_smankad@quicinc.com>
2024-12-27 17:24:54 +05:30
Akhil Budampati
fabbf1b2b5 ARM: dts: msm: enabling mem-object node for tuna
Tuna needs mem-object node for si-core xts enablement.

Change-Id: I1ece1cc93606cc11febab038ae2e7f0ab7f0bd8e
Signed-off-by: Akhil Budampati <quic_abudampa@quicinc.com>
2024-11-21 21:24:33 -08:00
Pranav Mahesh Phansalkar
062d9202aa ARM: dts: msm: Add nodes for qmsgq gunyah on tuna
Add the device nodes on tuna oemvm and tuivm to enable qmsgq socket
communication over gunyah message queues.

Change-Id: I42be6dabb313e914691945521962cff53f969a02
Signed-off-by: Pranav Mahesh Phansalkar <quic_pphansal@quicinc.com>
2024-11-01 15:22:02 +05:30
QCTECMDR Service
e4e59bff40 Merge "ARM: dts: msm: Add test nodes for Tuna VMs" 2024-10-30 02:06:05 -07:00
Hrishabh Rajput
1ee0d138da ARM: dts: msm: Add test nodes for Tuna VMs
Add test nodes for Tuna Trusted VM and OEMVM.

Change-Id: I9b7fe8d547f764e5917e48ef36f9727018a8fb79
Signed-off-by: Hrishabh Rajput <quic_hrishabh@quicinc.com>
2024-10-25 14:49:28 +05:30
Pranav Mahesh Phansalkar
c989bbec1e ARM: dts: msm: Add oemvm qrtr gunyah node for tuna
Add the nodes for enable qrtr communication between primary vm and
oemvm on tuna.

This adds platform devices and vdevice descriptions to start the
qrtr gunyah transport on both primary vm and oemvm device trees. This
also adds the device tree node to configure qrtr as node id 21 on oem
vm.

Change-Id: I8697478e2e1b8269aa3b93f940a8c98f03b7c9b2
Signed-off-by: Pranav Mahesh Phansalkar <quic_pphansal@quicinc.com>
2024-10-25 10:59:11 +05:30
QCTECMDR Service
cb1489ed60 Merge "ARM: dts: msm: Set vCPU affinity to CPU0 for VMs on Tuna" 2024-10-16 09:05:07 -07:00
Vijayanand Jitta
a7ce6b1cb4 ARM: dts: msm: Enable virtio-mem device for oemvm on tuna
Describe the properties of the memory region virtio-mem supports.
Also reserve the IPA space for dmabuf buffers.

Change-Id: I6baa1a7d00b26f1a885e9c85c57b7c30745dd5f6
Signed-off-by: Vijayanand Jitta <quic_vjitta@quicinc.com>
2024-10-14 02:17:22 -07:00
Vijayanand Jitta
eb791d346b ARM: dts: msm: Add mem-buf device on oemvm
Describe the properties and msgqs of the mem-buf device.

Change-Id: Ie05f273fd3747d4bf7a071ad5addae285ab612b4
Signed-off-by: Vijayanand Jitta <quic_vjitta@quicinc.com>
2024-10-14 02:17:07 -07:00
Hrishabh Rajput
8954f28a7e ARM: dts: msm: Set vCPU affinity to CPU0 for VMs on Tuna
Even though we use proxy scheduling, during VM bootup hypervisor tries
to boot the VMs as per the affinity-map. This may cause panic in case a
CPU within affinity-map is unavailable.

Affining vCPUs to CPU0 makes sure VM proceeds with
powered-ON sequence, assuming CPU0 is always available.

Change-Id: Ia6799445891e1b003b5055178adb50778bade863
Signed-off-by: Hrishabh Rajput <quic_hrishabh@quicinc.com>
2024-10-09 15:08:10 +05:30
Hrishabh Rajput
7aba41bc8d ARM: dts: msm: Add initial devicetree for Tuna OEMVM
Add initial devicetree files for OEMVM for RUMI platform on Tuna SoC.

Change-Id: Ia8a0dbeb6a345e6f5e08ba70c92b9957e27122ed
Signed-off-by: Hrishabh Rajput <quic_hrishabh@quicinc.com>
2024-10-03 11:37:21 +05:30