Commit Graph

4 Commits

Author SHA1 Message Date
Manish Pandey
67fdf207c7 ARM: dts: msm: Update Reference Clock to clk8_a4 for Kera UFS 2.x
The Kera UFS 2.x requires a reference clock of 19.2MHz. Currently,
the reference clock provided by the DTSI node RPMH_LN_BB_CLK3
returns clk_get_rate() as 38.4MHz.

To address this, the handler is updated to use clk8_a4, ensuring the
clock rate is set to 19.2MHz.

Change-Id: I92ad772c7b86652c0dc5bdc3af18a9db900d74e5
Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
2025-01-10 12:08:24 +05:30
Manish Pandey
b70023c975 ARM: dts: msm: Update ref_clk_src for kera UFS 2.x platforms
Update ref_clk_src to source 19.2MHz clock to UFS 2.x Platforms.

Change-Id: I0f8a2307bc700a4eac2caa5e9ff5d0bfaac1b163
Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
2024-12-05 16:44:04 +05:30
Manish Pandey
6cdef07bc0 ARM: dts: msm: Update UFS PHY compatible for Kera SoC
Update Kera ufs device tree to use niobe UFS PHY driver. Hence
align with UFS SoC guide settings in HSR v19 specifications.

Change-Id: Ia83b887a2a8b49131e2141ff936ab3990700dd91
Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
2024-11-27 22:40:19 -08:00
Manish Pandey
9c9b405454 ARM: dts: msm: Add UFS support for kera platforms
Add UFS support for kera cdp, mtp and rcm platforms.

Change-Id: Iee003994d693a23e563e25621a23a99e85aaadac
Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
2024-11-25 00:39:55 -08:00