Currently, charger FW configures and enables ship mode in parallel with
shutdown activity. This can cause a race condition leaving the device in
a bad state if the device is powering down while SW is still issuing SPMI
writes.
Add new "qcom,ship-mode-immediate" property to flag that ship mode should
be immediately configured after user sets ship_mode_en to avoid this
race condition.
Change-Id: I16b1e307cac8befff7a1136de1cb522e03a95c46
Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
Add compatible strings for Ravelin and RavelinP SoCs.
Change-Id: Ibf00b144c1798024fec669545e4fbeeefe5b21c9
Signed-off-by: Saranya R <quic_sarar@quicinc.com>
Add qcom,ramoops binding for its device and it is exactly copy of
ramoops device but differ in just memory is dynamically reserved
during early boot.
Change-Id: I2b2b288061ba001aa8cc9a73fad1176a01ce4769
Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
Add documentation for the qcom,cpufreq-thermal device, which is used to
handle CPU thermal limit mailboxes notifications.
Change-Id: I6e2c33d2a9d55ab4bb2c8361091ebb0110739d43
Signed-off-by: Mike Tipton <quic_mdtipton@quicinc.com>
Add compatible strings for Parrot and ParrotP SoCs.
Change-Id: Ia09ce9cc0ecbb5f3677acc609b3fd394a5f15beb
Signed-off-by: Saranya R <quic_sarar@quicinc.com>
Update cpucp and cpucp-log bindings to include compatible
string and properties required for pdp mailbox and logging.
Change-Id: I40f8f5ef64e9e1079e5925833e87e48288684ae7
Signed-off-by: Amir Vajid <quic_avajid@quicinc.com>
Signed-off-by: Shivnandan Kumar <quic_kshivnan@quicinc.com>
Add bindings for gpu dump skip cooling device driver. This cooling
device is added to set WR_THERMAL_FLAG region in SDAM which is used
by PMIC to disable GFX in SDI path, when SDI path reset is caused
during high temperature. It also set a SOC cookie in sys dbg imem
region which is used to skip GPU scan dump collection in SDI path,
when SDI path reset is triggered during high temperature.
Change-Id: Icefd3b2ee0e36de1738c177bc2bb3e67700372f0
Signed-off-by: Priyansh Jain <quic_priyjain@quicinc.com>
Add gpu dump skip region info to IMEM device tree binding.
Change-Id: I2ec1947201f4e78d18aeefb813faaf5427fa481b
Signed-off-by: Priyansh Jain <quic_priyjain@quicinc.com>
Added SP PBL Patch Version Register to read the SP-PBL
patch version to handle SPSS attach timed out scenario.
Change-Id: Id7ee4df5d09d9c09410bc24fc475ee2a36fca246
Signed-off-by: Magesh M <quic_murugan@quicinc.com>
Add CRMV register as required.
While at this also fix the issues with compilation failures.
- Fix the schema path.
- Fix max items in reg, interrupts properties.
- Fix indentation.
- Update examples.
Change-Id: I435ca457f3a2a60ac2c5063b7b65cfa4357ee7dd
Signed-off-by: Minghao Zhang <quic_minghao@quicinc.com>
Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
Add DT entry to enable the memory onject support for
smcinvoke.
Change-Id: I87b62b048e94e2aad2a8329b275bbd8d75ae6cc7
Signed-off-by: Amirreza Zarrabi <quic_azarrabi@quicinc.com>
Add compatible string for APQ variant on RCM platform for
Sun SoC.
Change-Id: I1d20c8b8c5f8156ae299fd2646160086859badd5
Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com>
Add bindings for QCOM AMOLED regulator which is used to configure
triple power supply for amoled displays.
This is a snapshot of the bindings taken as of qcom-6.1
commit 6f13701949ee ("dt-bindings: qpnp-amoled: Fix the IBB Spur mitigation example code")
and converted from .txt to .yaml file.
Change-Id: I51f6029f2a140e5a6d2a53d3b1a2d468a8721bfa
Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
Add new "qcom,adc5-gen4" property to flag ADC5 GEN4 channels.
Change-Id: I271b6e74d36721f6c38bd1f3d68e47bc5393b04d
Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
Add a bindings file for max31760 fan controller.
Change-Id: Id6d885d3678a6ffb1b1797b85e37dae121b66fa8
Signed-off-by: Minghao Zhang <quic_minghao@quicinc.com>
Add the device tree binding for mpm sleep counter
so that it device nodes can be added for respective
SoC where it is supported.
Change-Id: Ic503641c25a4be7121cbf00ccffe103e641cd2f8
Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
Remove the qcom,cesta-l1sub-timeout-ext-int property as its no
longer required due to recent changes in the pcie driver using the
change commit b53d4aa20ee7 ("pci: msm: Add support to enable
PCIE CESTA clkreq config").
Initially this property was intended to be used to enable the BIT(3):
PARF_CESTA_L1SUB_TIMEOUT_EXT_INT_EN field of
PCIE0_PCIE_PARF_L1SUB_CESTA_CTRL register for platforms where CESTA
is enabled and the platform is not pineapple.
Currently the pcie driver will by default set this BIT(3) when CESTA is
enabled and the qcom,pcie-clkreq-offset property is present. Since the
qcom,pcie-clkreq-offset property will not be present when CESTA
is enabled on pineapple, pcie driver will not touch the
PCIE0_PCIE_PARF_L1SUB_CESTA_CTRL register.
Pcie driver will set only the BIT(0) PARF_CESTA_CLKREQ_SEL field when
qcom,pcie-clkreq-offset property is present and CESTA is not present
which is the case of pineapple platform when CESTA is enabled. And
this case is also taken care of by the pcie driver without the need
for qcom,pcie-clkreq-offset property.
Below are the required cases that needs to be taken care of by the
pcie driver.
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| CESTA is enabled | BIT(0) set | BIT(3) set | platform |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| YES | need to set| need to set| non-pineapple |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| YES | set by | Not | pineapple |
| | default | applicable | |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| NO | NO | NO | non-pineapple |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| NO | need to | Not | pineapple |
| | unset | applicable | |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++.
Above mentioned cases are taken care by using the qcom,pcie-clkreq-offset
property in the following way.
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| CESTA is enabled | qcom,pcie-clkreq-offset | platform |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| YES | YES | non-pineapple |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| YES | NO | pineapple |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| NO | NO | non-pineapple |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
| NO | YES | pineapple |
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++.
Change-Id: I1bc4985be0080d295153233b0d5d4ce07e006818
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
