Jerome Lee
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df64193218
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ARM: dts: msm: Add register lists to DCC for Sun
Add register lists to DCC for Sun.
Change-Id: Iffec4f0022a11be7fb5e0701e37975d71a1e9428
Signed-off-by: Jerome Lee <quic_jaewookl@quicinc.com>
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2023-11-30 21:49:05 -08:00 |
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Yuanfang Zhang
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f2e93ba80b
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ARM: dts: msm: correct dcc sram size on sun
correct dcc sram size to 0x8000 on sun.
Change-Id: I1c4458390101d9d9026977ca71e95fad74667f05
Signed-off-by: Yuanfang Zhang <quic_yuanfang@quicinc.com>
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2023-11-19 21:39:16 -08:00 |
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Yuanfang Zhang
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d39b93f626
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ARM: dts: msm: add cpu related dump for sun
Add cpu related dump entry for sun.
Change-Id: Idf8723bc0e04fb87822a37d271361d2da0baa690
Signed-off-by: Yuanfang Zhang <quic_yuanfang@quicinc.com>
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2023-11-14 02:45:01 -08:00 |
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Yuanfang Zhang
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103a530725
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ARM: dts: msm: correct size for reserved dump_mem on sun
Correct the reserved dump_mem size on sun.
Change-Id: Ic7c4843f5789d2d75cdc19d2762e9e2651544996
Signed-off-by: Yuanfang Zhang <quic_yuanfang@quicinc.com>
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2023-11-09 21:02:59 -08:00 |
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Yuanfang Zhang
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01986ee6f6
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ARM: dts: msm: add dump table for sun
Add memory dump table for sun.
Change-Id: I1ed6ad897b7bf1be878821475c5270a406efb3d7
Signed-off-by: Yuanfang Zhang <quic_yuanfang@quicinc.com>
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2023-11-07 02:40:59 -08:00 |
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Yuanfang Zhang
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2964e2edd2
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ARM: dts: msm: add coresight component DT file for sun
Add coresight component devicetree file for sun.
Change-Id: I28b8b6a2142fc89ed457553f039eca785064007b
Signed-off-by: Yuanfang Zhang <quic_yuanfang@quicinc.com>
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2023-09-19 23:21:39 -07:00 |
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