Correct the port mask of mbhc port.
Since the WCD_SWR_TX DATA0 voltage was incorrect
with default setting, but was correct when
the ADC_LP was running in the swrm bus 9.6mhz,
So copy the SWR_UC0(9.6mhz) to SWR_UC1(4.8mhz).
Change-Id: I3638349a6ebec06b8f4a828498e1285579361e45
Signed-off-by: Yuhui Zhao <quic_yuhuzhao@quicinc.com>
Add ldo-ocp notifier support for tuna for platforms.
Change-Id: I46c1feb2f4ff2da3945f9ad445eb5d99f81f7af4
Signed-off-by: Kavya Nunna <quic_knunna@quicinc.com>
Add device tree bindings for arm,arch-cache node.
Change-Id: I46acfdd171e297368d6bedc431af7dd1270909f8
Signed-off-by: Asit Shah <quic_asitshah@quicinc.com>
Only add wcn-bt-ext for enabling second bt backend for needed dtsi file.
Change-Id: I42ca1840019a9db7d02ac39092f15dd438ea334f
Signed-off-by: MingShu Pang <quic_mpang@quicinc.com>
Remove lpass_bt_swr in ssr devs as bt_swr is disabled in
Kera cdp variant.
Change-Id: Idd149e79b09c1cd3db57100887c3e187bd8420c8
Signed-off-by: Ravulapati Vishnu Vardhan Rao <quic_visr@quicinc.com>
Add wcd usbss node for CDP to detect mic from wcd usbss driver.
Change-Id: Ic7fbab156a2dda2185a80c96d6589764ca66b57d
Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com>
This change adds the entries of qusb phys and
usb bam in yaml format.
Change-Id: I5697f28cf786ab6cc61c462a164ff4b0e4e68aac
Signed-off-by: Rajkumar Patel <quic_rajkpate@quicinc.com>
Add devicetree support for Tuna7 and TunaP SoC.
Change-Id: I5f94559c66f00bcb746fc05f7c445a8e2501d862
Signed-off-by: Hrishabh Rajput <quic_hrishabh@quicinc.com>
(cherry picked from commit b0ed9373e7)
Update clk div factor entries for TX and VA macros to reflect
proper HW configuration.
Change-Id: Iecc4f684aaf90dc671ed850c0c159e0b7eeaa42c
Signed-off-by: Ravulapati Vishnu Vardhan Rao <quic_visr@quicinc.com>
Only add wcn-bt-ext for enabling second bt backend for needed dtsi file.
Change-Id: I42ca1840019a9db7d02ac39092f15dd438ea334f
Signed-off-by: MingShu Pang <quic_mpang@quicinc.com>
Increase DVDD initial voltage from 1.06V to 1.09V. Also increase
the min voltage voting to 1.09V for CDP and MTP platforms of Tuna.
This is to avoid any voltage drop issue on the DVDD rail similar
to Tuna QRD platform.
Change-Id: I77eabf294777130059bac6f748cc5c0f4a7d0002
Signed-off-by: Abhinav Saurabh <quic_abhisaur@quicinc.com>
Signed-off-by: lnxdisplay <lnxdisplay@localhost>
Added initial device tree for QCS610 LE target.
Change-Id: Ia8b8790fa0916a8a87a5bc696f5b9e23d7e951dc
Signed-off-by: Kunal Singh Ranawat <quic_kranawat@quicinc.com>
Add devicetree support for Tuna7 and TunaP SoC.
Change-Id: I5f94559c66f00bcb746fc05f7c445a8e2501d862
Signed-off-by: Hrishabh Rajput <quic_hrishabh@quicinc.com>
Update memory map for kera, inline with v4.
Change-Id: Ifc5acdc379372239f4fde0f22fcd8c17f66ce636
Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com>
Add wcd usbss node for CDP to detect mic from wcd usbss driver.
Change-Id: Ic7fbab156a2dda2185a80c96d6589764ca66b57d
Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com>
Remove lpass_bt_swr in ssr devs as bt_swr is disabled in
Kera cdp variant.
Change-Id: Idd149e79b09c1cd3db57100887c3e187bd8420c8
Signed-off-by: Ravulapati Vishnu Vardhan Rao <quic_visr@quicinc.com>
According to the Hardware Programming Guide, when going into hibern8,
select XO clock (RPMH_CXO_CLK) clock as the parent of the phy symbol
mux clocks (GCC_UFS_PHY_RX/TX_SYMBOL_0/1_CLK_SRC). When exiting the
hibern8, select the phy symbol clocks (UFS_PHY_RX/TX_SYMBOL_0/1_CLK)
as the parent of the phy symbol mux clocks.
Change-Id: I624f98c39b7548dc2a9a5207d82600bb69ac41d5
Signed-off-by: Bao D. Nguyen <quic_nguyenb@quicinc.com>
Update memory map for kera, inline with v4.
Change-Id: Ifc5acdc379372239f4fde0f22fcd8c17f66ce636
Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com>
Reserve 16kb to dcc on TZ while HLOS have 16 KB.
Change-Id: I2063be0924b5719bd2c3abfffc84c0044d74ae37
Signed-off-by: Yingchao Deng <quic_yingdeng@quicinc.com>
(cherry picked from commit 285a63e7b4)
This update adjusts the PHY timings for the VTDR command mode panel on
Kera RCM/CDP platforms based on the required FPS, following the removal
of the qcom,mdss-dsi-panel-clockrate hardcoding. Previously, the
hardcoding resulted in uniform panel PHY timings across all FPS.
Some Kera RCMs have exhibited screen freeze issues when switching from
120 FPS to 60 FPS in command mode after the removal of the hardcoded
clock rate. Interestingly, this issue has not been observed on Kera
CDPs and other platforms, suggesting potential underlying hardware
differences between CDPs and RCMs that necessitate proper tuning of
panel PHY timings.
Update the panel PHY timings to fix this.
Fixes: I1c3c77eed76 ("ARM: dts: msm: remove hard coded panel clk rate
for kera RCM").
Change-Id: Iffd1d5da485d6961baa49ff96a65882c491a8ff6
Signed-off-by: Abhinav Saurabh <quic_abhisaur@quicinc.com>
