DWC3 host and XHCI plat now communicates the maximum number
of interrupters the XHCI HCD will allocate. Since platforms
only require a limited number of interrupters (i.e. 3) make
sure XHCI doesn't allocate more than is required.
Change-Id: I9e8592c8f62562f44c760571ac1505ab80b05fc6
Signed-off-by: Jigyanshu Mani <quic_jmani@quicinc.com>
Use upstream compatible DT property "iommu-addresses" instead
of "qcom,iommu-dma-addr-pool" for dwc3 which describes the
addresses that dwc3 cannot use.
Extend the address and size cells to ensure that IOMMU returns
a 32 bit address, in order to define a region that will block
0xf0000000--0xffffffffffffffff.
Change-Id: I211ba1b8bd1f7717f639d91dddb8adb86f17b42e
Signed-off-by: Saranya R <quic_sarar@quicinc.com>
Add initial device tree support for ravelin target.
This is a snapshot of dtsi files as of KP.1.0
'commit <370d8eab7cc6> ("Merge "ARM: dts: qcom:
Disable cnss-kiwi SOL on anorak platform"")'.
Modified as per compilation and bootup.
Change-Id: Icb9a6e67879c68dbf894d1713fa2837882b9f00c
Signed-off-by: Swetha Chikkaboraiah <quic_schikk@quicinc.com>
