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6 Commits

Author SHA1 Message Date
Vijayanand Jitta
6e5000b911 ARM: dts: msm: Add power domain and interconnect for kgsl-smmu 
Replace regulators with per-device genpd power domain and
add interconnect for kgsl-smmu on tuna.

Change-Id: I897b39ba98beaf630efef5397957e8cfb26b3d08
Signed-off-by: Vijayanand Jitta <quic_vjitta@quicinc.com>
 2024-11-24 14:30:05 +05:30
Vijayanand Jitta
b12060a823 ARM: dts: msm: Update smmu ACLTR mask values for tuna 
Update ACTLR mask for Compute clients for tuna.

Change-Id: I79c87a15f31b0fc769f83f25bcfd833a011f8790
Signed-off-by: Vijayanand Jitta <quic_vjitta@quicinc.com>
 2024-09-16 14:27:58 +05:30
Vijayanand Jitta
2c5e849024 ARM: dts: msm: Add smmu ACLTR values for tuna 
Configure per-context bank pre-fetch settings using
actlr for tuna.

Change-Id: I9053c5ddac34a25d60fa7345f533678ff294d454
Signed-off-by: Vijayanand Jitta <quic_vjitta@quicinc.com>
 2024-08-25 23:57:03 -07:00
Vijayanand Jitta
adfa829366 ARM: dts: msm: Add interconnect properties for smmus for tuna 
Enable bus bandwidth voting by adding interconnect properties
for kgsl and apps smmu on tuna.

Change-Id: Iafb8c6975154048aff74b04fad75c9ce0f48aa3e
Signed-off-by: Vijayanand Jitta <quic_vjitta@quicinc.com>
 2024-08-25 23:56:57 -07:00
Vijayanand Jitta
2b2f9d893c ARM: dts: msm: Add clock and regulator for kgsl-smmu for tuna 
Add clock and regulator which would be required for
register accesses of kgsl-smmu for tuna.

Change-Id: Ib09be9911e6b37b1e83ad59183a46284de2835b9
Signed-off-by: Vijayanand Jitta <quic_vjitta@quicinc.com>
 2024-08-25 23:56:49 -07:00
Vijayanand Jitta
65104c0f2c ARM: dts: msm: Add initial SMMU configuration for tuna 
Add initial apps and gpu SMMU configuration for tuna.

Change-Id: Icee98ad4ce7639a398e026e9f2c805d67d3afb06
Signed-off-by: Vijayanand Jitta <quic_vjitta@quicinc.com>
 2024-06-30 22:40:28 -07:00