From ff6aa4f63e4eb984c0c2ccda1b8c6f68d0cdd096 Mon Sep 17 00:00:00 2001 From: Abhilash Kumar Date: Tue, 25 Mar 2025 03:20:16 +0530 Subject: [PATCH] ARM: dts: msm: Remove drv clocks from kera This change removes DRV clocks from Kera devicetree. CRs-Fixed: 4099869 Change-Id: Id6ceee898302168f741a04cfe7f9710c210e62b6 --- kera-camera.dtsi | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/kera-camera.dtsi b/kera-camera.dtsi index ef0845ed..ae12f682 100644 --- a/kera-camera.dtsi +++ b/kera-camera.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -1150,13 +1150,11 @@ "cam_cc_slow_ahb_clk_src", "cpas_ahb_clk", "cpas_core_ahb_clk", - "cam_cc_drv_ahb_clk", "cam_cc_fast_ahb_clk_src", "cam_cc_top_fast_ahb_clk", "camnoc_rt_axi_clk_src", "camnoc_rt_axi_clk", "camnoc_nrt_axi_clk", - "cam_cc_drv_xo_clk", "cam_cc_pll0", "cam_cc_qdss_debug_xo_clk"; clocks = @@ -1166,22 +1164,20 @@ <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, <&camcc CAM_CC_CAM_TOP_AHB_CLK>, <&camcc CAM_CC_CORE_AHB_CLK>, - <&camcc CAM_CC_DRV_AHB_CLK>, <&camcc CAM_CC_FAST_AHB_CLK_SRC>, <&camcc CAM_CC_CAM_TOP_FAST_AHB_CLK>, <&camcc CAM_CC_CAMNOC_RT_AXI_CLK_SRC>, <&camcc CAM_CC_CAMNOC_RT_AXI_CLK>, <&camcc CAM_CC_CAMNOC_NRT_AXI_CLK>, - <&camcc CAM_CC_DRV_XO_CLK>, <&camcc CAM_CC_PLL0>, <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>; clock-rates = - <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, - <0 0 0 80000000 0 0 0 300000000 0 300000000 0 0 0 0 0>, - <0 0 0 80000000 0 0 0 300000000 0 400000000 0 0 0 0 0>, - <0 0 0 80000000 0 0 0 300000000 0 400000000 0 0 0 0 0>, - <0 0 0 80000000 0 0 0 400000000 0 400000000 0 0 0 0 0>, - <0 0 0 80000000 0 0 0 400000000 0 400000000 0 0 0 0 0>; + <0 0 0 0 0 0 0 0 0 0 0 0 0>, + <0 0 0 80000000 0 0 300000000 0 300000000 0 0 0 0>, + <0 0 0 80000000 0 0 300000000 0 400000000 0 0 0 0>, + <0 0 0 80000000 0 0 300000000 0 400000000 0 0 0 0>, + <0 0 0 80000000 0 0 400000000 0 400000000 0 0 0 0>, + <0 0 0 80000000 0 0 400000000 0 400000000 0 0 0 0>; clock-cntl-level = "suspend", "lowsvs", "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "camnoc_rt_axi_clk_src";