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ARM: dts: msm: Add Kera GPU ACD values

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Add ACD control register values and support for Kera GPU.

Change-Id: Idfb20fe8b46655fadf121d2a8192a4fbc42c051c
Signed-off-by: Sanjay Yadav <quic_sanjyada@quicinc.com>
This commit is contained in:
Sanjay Yadav
2025-02-19 22:27:25 +05:30
committed by Vishvanath Singh
parent 81ee1745cf
commit fd59987095
2 changed files with 35 additions and 0 deletions
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20
gpu/kera-gpu-pwrlevels.dtsi
View File

@@ -26,6 +26,8 @@
qcom,bus-freq-ddr8 = <9>; qcom,bus-freq-ddr8 = <9>;
qcom,bus-min-ddr8 = <8>; qcom,bus-min-ddr8 = <8>;
qcom,bus-max-ddr8 = <10>; qcom,bus-max-ddr8 = <10>;
qcom,acd-level = <ACD_LEVEL_Turbo_L2>;
}; };
/* Turbo_L1 */ /* Turbo_L1 */
@@ -41,6 +43,8 @@
qcom,bus-freq-ddr8 = <9>; qcom,bus-freq-ddr8 = <9>;
qcom,bus-min-ddr8 = <8>; qcom,bus-min-ddr8 = <8>;
qcom,bus-max-ddr8 = <10>; qcom,bus-max-ddr8 = <10>;
qcom,acd-level = <ACD_LEVEL_Turbo_L1>;
}; };
/* Turbo */ /* Turbo */
@@ -56,6 +60,8 @@
qcom,bus-freq-ddr8 = <8>; qcom,bus-freq-ddr8 = <8>;
qcom,bus-min-ddr8 = <8>; qcom,bus-min-ddr8 = <8>;
qcom,bus-max-ddr8 = <9>; qcom,bus-max-ddr8 = <9>;
qcom,acd-level = <ACD_LEVEL_Turbo>;
}; };
/* Nom_L1 */ /* Nom_L1 */
@@ -71,6 +77,8 @@
qcom,bus-freq-ddr8 = <8>; qcom,bus-freq-ddr8 = <8>;
qcom,bus-min-ddr8 = <8>; qcom,bus-min-ddr8 = <8>;
qcom,bus-max-ddr8 = <8>; qcom,bus-max-ddr8 = <8>;
qcom,acd-level = <ACD_LEVEL_Nominal_L1>;
}; };
/* Nom */ /* Nom */
@@ -86,6 +94,8 @@
qcom,bus-freq-ddr8 = <7>; qcom,bus-freq-ddr8 = <7>;
qcom,bus-min-ddr8 = <6>; qcom,bus-min-ddr8 = <6>;
qcom,bus-max-ddr8 = <8>; qcom,bus-max-ddr8 = <8>;
qcom,acd-level = <ACD_LEVEL_Nominal>;
}; };
/* SVS_L2 */ /* SVS_L2 */
@@ -101,6 +111,8 @@
qcom,bus-freq-ddr8 = <6>; qcom,bus-freq-ddr8 = <6>;
qcom,bus-min-ddr8 = <5>; qcom,bus-min-ddr8 = <5>;
qcom,bus-max-ddr8 = <7>; qcom,bus-max-ddr8 = <7>;
qcom,acd-level = <ACD_LEVEL_SVS_L2>;
}; };
/* SVS_L1 */ /* SVS_L1 */
@@ -116,6 +128,8 @@
qcom,bus-freq-ddr8 = <6>; qcom,bus-freq-ddr8 = <6>;
qcom,bus-min-ddr8 = <5>; qcom,bus-min-ddr8 = <5>;
qcom,bus-max-ddr8 = <7>; qcom,bus-max-ddr8 = <7>;
qcom,acd-level = <ACD_LEVEL_SVS_L1>;
}; };
/* SVS */ /* SVS */
@@ -131,6 +145,8 @@
qcom,bus-freq-ddr8 = <4>; qcom,bus-freq-ddr8 = <4>;
qcom,bus-min-ddr8 = <2>; qcom,bus-min-ddr8 = <2>;
qcom,bus-max-ddr8 = <5>; qcom,bus-max-ddr8 = <5>;
qcom,acd-level = <ACD_LEVEL_SVS>;
}; };
/* Low_SVS */ /* Low_SVS */
@@ -146,6 +162,8 @@
qcom,bus-freq-ddr8 = <2>; qcom,bus-freq-ddr8 = <2>;
qcom,bus-min-ddr8 = <2>; qcom,bus-min-ddr8 = <2>;
qcom,bus-max-ddr8 = <4>; qcom,bus-max-ddr8 = <4>;
qcom,acd-level = <ACD_LEVEL_LowSVS>;
}; };
/* Low_SVS_D1 */ /* Low_SVS_D1 */
@@ -161,6 +179,8 @@
qcom,bus-freq-ddr8 = <2>; qcom,bus-freq-ddr8 = <2>;
qcom,bus-min-ddr8 = <2>; qcom,bus-min-ddr8 = <2>;
qcom,bus-max-ddr8 = <4>; qcom,bus-max-ddr8 = <4>;
qcom,acd-level = <ACD_LEVEL_LowSVS_D1>;
}; };
}; };
}; };

15
gpu/kera-gpu.dtsi
View File

@@ -5,6 +5,18 @@
#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024)) #define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
/* ACD Control register values */
#define ACD_LEVEL_Turbo_L2 0xa8295ffd
#define ACD_LEVEL_Turbo_L1 0xa82a5ffd
#define ACD_LEVEL_Turbo 0x882c5ffd
#define ACD_LEVEL_Nominal_L1 0x882d5ffd
#define ACD_LEVEL_Nominal 0x882d5ffd
#define ACD_LEVEL_SVS_L2 0xa82d5ffd
#define ACD_LEVEL_SVS_L1 0x882f5ffd
#define ACD_LEVEL_SVS 0Xc02d5ffd
#define ACD_LEVEL_LowSVS 0Xc82f5ffd
#define ACD_LEVEL_LowSVS_D1 0Xc82f5ffd
&msm_gpu { &msm_gpu {
compatible = "qcom,adreno-gpu-gen7-17-0", "qcom,kgsl-3d0"; compatible = "qcom,adreno-gpu-gen7-17-0", "qcom,kgsl-3d0";
status = "ok"; status = "ok";
@@ -169,5 +181,8 @@
iommus = <&kgsl_smmu 0x5 0x000>; iommus = <&kgsl_smmu 0x5 0x000>;
qcom,iommu-dma = "disabled"; qcom,iommu-dma = "disabled";
mboxes = <&qmp_aop 0>;
mbox-names = "aop";
}; };
}; };