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ARM: dts: msm: Update dispcc clock node as GenPD provider on Kera

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Mark dispcc clock node as GenPD provider and disable the display GDSC
regulator nodes for kera platform.
While at it, keep the gdsc's as it is on kera-rumi platform and update
the compatible to align with freq plan.

Change-Id: If01f876b3d160cf5c1cfe6be13e3e4b42f62cfa6
Signed-off-by: Anaadi Mishra <quic_anaadim@quicinc.com>
This commit is contained in:
Anaadi Mishra
2024-09-25 16:36:41 +05:30
parent f42efc56a8
commit fc794cac57
2 changed files with 10 additions and 3 deletions
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8
qcom/kera-rumi.dtsi
View File

@@ -172,3 +172,11 @@
&video_cc_mvs0c_gdsc { &video_cc_mvs0c_gdsc {
status = "ok"; status = "ok";
}; };
&disp_cc_mdss_core_gdsc {
status = "ok";
};
&disp_cc_mdss_core_int2_gdsc {
status = "ok";
};

5
qcom/kera.dtsi
View File

@@ -1798,7 +1798,7 @@
}; };
dispcc: clock-controller@af00000 { dispcc: clock-controller@af00000 {
compatible = "qcom,tuna-dispcc", "syscon"; compatible = "qcom,kera-dispcc", "syscon";
reg = <0xaf00000 0x20000>; reg = <0xaf00000 0x20000>;
reg-name = "cc_base"; reg-name = "cc_base";
vdd_mm-supply = <&VDD_CX_LEVEL>; vdd_mm-supply = <&VDD_CX_LEVEL>;
@@ -1814,6 +1814,7 @@
qcom,disp_crm-crmc = <&dispcc_crm>; qcom,disp_crm-crmc = <&dispcc_crm>;
#clock-cells = <1>; #clock-cells = <1>;
#reset-cells = <1>; #reset-cells = <1>;
#power-domain-cells = <1>;
}; };
gcc: clock-controller@100000 { gcc: clock-controller@100000 {
@@ -3164,13 +3165,11 @@
&disp_cc_mdss_core_gdsc { &disp_cc_mdss_core_gdsc {
clocks = <&gcc GCC_DISP_AHB_CLK>; clocks = <&gcc GCC_DISP_AHB_CLK>;
parent-supply = <&VDD_CX_LEVEL>; parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
}; };
&disp_cc_mdss_core_int2_gdsc { &disp_cc_mdss_core_int2_gdsc {
clocks = <&gcc GCC_DISP_AHB_CLK>; clocks = <&gcc GCC_DISP_AHB_CLK>;
parent-supply = <&VDD_CX_LEVEL>; parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
}; };
&gcc_pcie_0_gdsc { &gcc_pcie_0_gdsc {