From fc4b7903f4876423d5f41cf2123ed1af0ffd6b2b Mon Sep 17 00:00:00 2001 From: Sampurna Bolloju Date: Thu, 21 Nov 2024 10:01:50 +0530 Subject: [PATCH] ARM: dts: msm: enable display cesta on tuna target Add display cesta related DT node on tuna target. Move the GDSC & MDP core clock from MDP to cesta node, as it will be controlled through cesta. Add the cesta related register offsets in trusted-vm DT. Change-Id: Ifa9f0b4500c5e6b453395bcf1de492e332d63306 Signed-off-by: Sampurna Bolloju Signed-off-by: lnxdisplay --- display/trustedvm-tuna-sde.dtsi | 9 ++++++ display/tuna-sde-display.dtsi | 3 +- display/tuna-sde.dtsi | 54 ++++++++++++++++++++++++++++----- 3 files changed, 57 insertions(+), 9 deletions(-) diff --git a/display/trustedvm-tuna-sde.dtsi b/display/trustedvm-tuna-sde.dtsi index 79d85eab..e07423fe 100644 --- a/display/trustedvm-tuna-sde.dtsi +++ b/display/trustedvm-tuna-sde.dtsi @@ -36,6 +36,15 @@ "sid_phys"; qcom,sde-vm-exclude-reg-names = "sid_phys"; + + qcom,tvm-include-reg = <0x0af20000 0x850>, + <0xaf30000 0x60>, + <0xaf31000 0x30>, + <0xaf32000 0x30>, + <0xaf33000 0x30>, + <0xaf34000 0x30>, + <0xaf35000 0x30>, + <0xaf36000 0x30>; qcom,sde-hw-version =<0xC0000000>; clocks = <&clock_cpucc GCC_DISP_AHB_CLK>, diff --git a/display/tuna-sde-display.dtsi b/display/tuna-sde-display.dtsi index ce534cc8..b905f813 100644 --- a/display/tuna-sde-display.dtsi +++ b/display/tuna-sde-display.dtsi @@ -95,7 +95,8 @@ }; &mdss_mdp { - connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2>; + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2 + &sde_cesta>; }; &dsi_vtdr6130_amoled_cmd { diff --git a/display/tuna-sde.dtsi b/display/tuna-sde.dtsi index f9db998d..a1de8490 100644 --- a/display/tuna-sde.dtsi +++ b/display/tuna-sde.dtsi @@ -207,27 +207,65 @@ clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "mdp_core_clk"; }; + + sde_cesta: qcom,sde_cesta@0x0af30000 { + cell-index = <0>; + compatible = "qcom,sde-cesta"; + reg = <0x0af20000 0x850>, + <0xaf30000 0x60>, + <0xaf31000 0x30>, + <0xaf32000 0x30>, + <0xaf33000 0x30>, + <0xaf34000 0x30>, + <0xaf35000 0x30>, + <0xaf36000 0x30>; + reg-names = "rscc", "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5"; + + clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; + + clock-names = "branch_clk", "core_clk"; + clock-rate = <660000000 660000000>; + clock-max-rate = <660000000 660000000>; + clock-mmrm = <0 DISP_CC_MDSS_MDP_CLK_SRC>; + + interconnects = <&mmss_noc MASTER_MDP_DISP_CRM_HW_0 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_0>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_1 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_1>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_2 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_2>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_3 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_3>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_4 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_4>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_5 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_5>, + <&mmss_noc MASTER_MDP_DISP_CRM_SW_0 + &mc_virt SLAVE_EBI1_DISP_CRM_SW_0>; + interconnect-names = "qcom,sde-data-bus-hw-0", "qcom,sde-data-bus-hw-1", + "qcom,sde-data-bus-hw-2", "qcom,sde-data-bus-hw-3", + "qcom,sde-data-bus-hw-4", "qcom,sde-data-bus-hw-5", + "qcom,sde-data-bus-sw-0"; + + power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; + }; }; &mdss_mdp { clocks = <&gcc GCC_DISP_HF_AXI_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>, <&dispcc DISP_CC_MDSS_VSYNC_CLK>, <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; clock-names = "gcc_bus", - "iface_clk", "branch_clk", "core_clk", "vsync_clk", - "lut_clk"; - clock-rate = <0 0 660000000 660000000 19200000 660000000>; - clock-max-rate = <0 0 660000000 660000000 19200000 660000000>; - clock-mmrm = <0 0 0 DISP_CC_MDSS_MDP_CLK_SRC 0 0>; + "iface_clk", "vsync_clk", "lut_clk"; + clock-rate = <0 0 19200000 660000000>; + clock-max-rate = <0 0 19200000 660000000>; qcom,hw-fence-sw-version = <0x1>; - power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; mmcx-supply = <&VDD_MMCX_LEVEL>; qti,smmu-proxy-cb-id = ;