From f5335c097f5ce0dde2890c887fb8125de04da089 Mon Sep 17 00:00:00 2001 From: David Collins Date: Tue, 24 Oct 2023 15:39:43 -0700 Subject: [PATCH 1/4] ARM: dts: qcom: add PMIC Glink and clients for Sun Add PMIC Glink devices and their client devices. The PMIC Glink device with name PMIC_RTR_ADSP_APPS supports the clients: ucsi, altmode, and battery_charger. The PMIC Glink device with name PMIC_LOGS_ADSP_APPS supports the clients: battery_debug, pmic_glink_debug, charger_ulog_glink, and glink_adc. Change-Id: Ib5a15c136c77c8368d4a561f266a1588c4649893 Signed-off-by: David Collins --- qcom/sun.dtsi | 61 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index f788f456..5f1d429d 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -1893,6 +1894,66 @@ }; }; + qcom,pmic_glink { + compatible = "qcom,qti-pmic-glink"; + qcom,pmic-glink-channel = "PMIC_RTR_ADSP_APPS"; + depends-on-supply = <&ipcc_mproc>; + + battery_charger: qcom,battery_charger { + compatible = "qcom,battery-charger"; + }; + + ucsi: qcom,ucsi { + compatible = "qcom,ucsi-glink"; + }; + + altmode: qcom,altmode { + compatible = "qcom,altmode-glink"; + #altmode-cells = <1>; + }; + }; + + qcom,pmic_glink_log { + compatible = "qcom,qti-pmic-glink"; + qcom,pmic-glink-channel = "PMIC_LOGS_ADSP_APPS"; + + qcom,battery_debug { + compatible = "qcom,battery-debug"; + }; + + qcom,charger_ulog_glink { + compatible = "qcom,charger-ulog-glink"; + }; + + pmic_glink_debug: qcom,pmic_glink_debug { + compatible = "qcom,pmic-glink-debug"; + #address-cells = <1>; + #size-cells = <0>; + depends-on-supply = <&spmi_bus>; + + /* Primary SPMI bus */ + spmi@0 { + reg = <0>; + #address-cells = <2>; + #size-cells = <0>; + + pmih010x_glink_debug: qcom,pmih010x-debug@7 { + compatible = "qcom,spmi-pmic"; + reg = <0x7 SPMI_USID>; + qcom,can-sleep; + }; + }; + }; + + pmic_glink_adc: qcom,glink-adc { + compatible = "qcom,glink-adc"; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + status = "disabled"; + }; + }; + thermal_zones: thermal-zones { }; From 47e74e072e731b5ebb1675156402a5025bebc1bb Mon Sep 17 00:00:00 2001 From: David Collins Date: Wed, 25 Oct 2023 11:46:30 -0700 Subject: [PATCH 2/4] ARM: dts: qcom: add PMIC Glink ADC channel nodes for Sun boards Add PMIC Glink ADC channel nodes for Sun MTP and QRD boards. This exposes an interface for software to read PMIC charger ADC channels for input current, charge current, and die temperature. This is useful for PMICs connected via I2C which are only accessible to charger firmware. Change-Id: Ie8a9a0690b9937f9c0c541123c28e544ba3495ec Signed-off-by: David Collins --- qcom/sun-mtp.dtsi | 34 ++++++++++++++++++++++++++++++++++ qcom/sun-qrd-sku1.dtsi | 34 ++++++++++++++++++++++++++++++++++ qcom/sun-qrd-sku2.dtsi | 34 ++++++++++++++++++++++++++++++++++ 3 files changed, 102 insertions(+) diff --git a/qcom/sun-mtp.dtsi b/qcom/sun-mtp.dtsi index 6738e922..a642e7db 100644 --- a/qcom/sun-mtp.dtsi +++ b/qcom/sun-mtp.dtsi @@ -28,6 +28,40 @@ }; }; +&pmic_glink_adc { + status = "ok"; + + smb1501_1_iin { + reg = <0x1066801>; + label = "smb1501_1_iin"; + }; + + smb1501_1_ichg { + reg = <0x1066802>; + label = "smb1501_1_ichg"; + }; + + smb1501_1_die_temp { + reg = <0x1066803>; + label = "smb1501_1_die_temp"; + }; + + smb1501_2_iin { + reg = <0x1066901>; + label = "smb1501_2_iin"; + }; + + smb1501_2_ichg { + reg = <0x1066902>; + label = "smb1501_2_ichg"; + }; + + smb1501_2_die_temp { + reg = <0x1066903>; + label = "smb1501_2_die_temp"; + }; +}; + ®ulator_ocp_notifier { periph-1c1-supply = <&L1B>; periph-1c2-supply = <&L2B>; diff --git a/qcom/sun-qrd-sku1.dtsi b/qcom/sun-qrd-sku1.dtsi index 69a76e8d..ed3b4a09 100644 --- a/qcom/sun-qrd-sku1.dtsi +++ b/qcom/sun-qrd-sku1.dtsi @@ -4,3 +4,37 @@ */ #include "sun-qrd.dtsi" + +&pmic_glink_adc { + status = "ok"; + + smb1396_1_iin { + reg = <0x1063401>; + label = "smb1396_1_iin"; + }; + + smb1396_1_ichg { + reg = <0x1063402>; + label = "smb1396_1_ichg"; + }; + + smb1396_1_die_temp { + reg = <0x1063403>; + label = "smb1396_1_die_temp"; + }; + + smb1396_2_iin { + reg = <0x1063501>; + label = "smb1396_2_iin"; + }; + + smb1396_2_ichg { + reg = <0x1063502>; + label = "smb1396_2_ichg"; + }; + + smb1396_2_die_temp { + reg = <0x1063503>; + label = "smb1396_2_die_temp"; + }; +}; diff --git a/qcom/sun-qrd-sku2.dtsi b/qcom/sun-qrd-sku2.dtsi index 69a76e8d..de2ef9b0 100644 --- a/qcom/sun-qrd-sku2.dtsi +++ b/qcom/sun-qrd-sku2.dtsi @@ -4,3 +4,37 @@ */ #include "sun-qrd.dtsi" + +&pmic_glink_adc { + status = "ok"; + + smb1501_1_iin { + reg = <0x1066801>; + label = "smb1501_1_iin"; + }; + + smb1501_1_ichg { + reg = <0x1066802>; + label = "smb1501_1_ichg"; + }; + + smb1501_1_die_temp { + reg = <0x1066803>; + label = "smb1501_1_die_temp"; + }; + + smb1501_2_iin { + reg = <0x1066901>; + label = "smb1501_2_iin"; + }; + + smb1501_2_ichg { + reg = <0x1066902>; + label = "smb1501_2_ichg"; + }; + + smb1501_2_die_temp { + reg = <0x1066903>; + label = "smb1501_2_die_temp"; + }; +}; From 834840db5a293b5faacc50d15d1fb0905ad9954d Mon Sep 17 00:00:00 2001 From: David Collins Date: Wed, 25 Oct 2023 12:09:31 -0700 Subject: [PATCH 3/4] ARM: dts: msm: add pmic-glink-debug PMIC subdevices for Sun boards Add SMB and IDT charger PMIC devices inside of the pmic-glink-debug device. These are interfaced over I2C and an SPMI bridge bus. This ensures that software is able to access the registers of these PMICs. Change-Id: I7afc56cb78a353960cb7db98ce5d9b51a05db9fe Signed-off-by: David Collins --- qcom/sun-mtp.dtsi | 27 ++++++++++++++++++++++++++ qcom/sun-qrd-sku1.dtsi | 43 ++++++++++++++++++++++++++++++++++++++++++ qcom/sun-qrd-sku2.dtsi | 27 ++++++++++++++++++++++++++ 3 files changed, 97 insertions(+) diff --git a/qcom/sun-mtp.dtsi b/qcom/sun-mtp.dtsi index a642e7db..4df2a1fa 100644 --- a/qcom/sun-mtp.dtsi +++ b/qcom/sun-mtp.dtsi @@ -62,6 +62,33 @@ }; }; +&pmic_glink_debug { + i2c@106 { + reg = <0x106>; /* I2C instance 6 in ADSP for SE5 */ + #address-cells = <1>; + #size-cells = <0>; + qcom,bus-type = "i2c"; + + qcom,smb1501@68 { + compatible = "qcom,i2c-pmic"; + reg = <0x68>; + qcom,can-sleep; + }; + + qcom,smb1501@69 { + compatible = "qcom,i2c-pmic"; + reg = <0x69>; + qcom,can-sleep; + }; + + qcom,idt9418@3b { + compatible = "qcom,i2c-pmic"; + reg = <0x3b>; + qcom,can-sleep; + }; + }; +}; + ®ulator_ocp_notifier { periph-1c1-supply = <&L1B>; periph-1c2-supply = <&L2B>; diff --git a/qcom/sun-qrd-sku1.dtsi b/qcom/sun-qrd-sku1.dtsi index ed3b4a09..ebbc3714 100644 --- a/qcom/sun-qrd-sku1.dtsi +++ b/qcom/sun-qrd-sku1.dtsi @@ -3,6 +3,8 @@ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ +#include + #include "sun-qrd.dtsi" &pmic_glink_adc { @@ -38,3 +40,44 @@ label = "smb1396_2_die_temp"; }; }; + +&pmic_glink_debug { + i2c@106 { + reg = <0x106>; /* I2C instance 6 in ADSP for SE5 */ + #address-cells = <1>; + #size-cells = <0>; + qcom,bus-type = "i2c"; + + qcom,smb1396@34 { + compatible = "qcom,i2c-pmic"; + reg = <0x34>; + qcom,can-sleep; + }; + + qcom,smb1396@35 { + compatible = "qcom,i2c-pmic"; + reg = <0x35>; + qcom,can-sleep; + }; + + qcom,idt9418@3b { + compatible = "qcom,i2c-pmic"; + reg = <0x3b>; + qcom,can-sleep; + }; + }; + + /* SPMI bridge bus 0 with SMB1510 device */ + spmi@200 { + reg = <0x200>; + #address-cells = <2>; + #size-cells = <0>; + qcom,bus-type = "spmi"; + + qcom,smb1510@d { + compatible = "qcom,spmi-pmic"; + reg = <0xd SPMI_USID>; + qcom,can-sleep; + }; + }; +}; diff --git a/qcom/sun-qrd-sku2.dtsi b/qcom/sun-qrd-sku2.dtsi index de2ef9b0..562b358e 100644 --- a/qcom/sun-qrd-sku2.dtsi +++ b/qcom/sun-qrd-sku2.dtsi @@ -38,3 +38,30 @@ label = "smb1501_2_die_temp"; }; }; + +&pmic_glink_debug { + i2c@106 { + reg = <0x106>; /* I2C instance 6 in ADSP for SE5 */ + #address-cells = <1>; + #size-cells = <0>; + qcom,bus-type = "i2c"; + + qcom,smb1501@68 { + compatible = "qcom,i2c-pmic"; + reg = <0x68>; + qcom,can-sleep; + }; + + qcom,smb1501@69 { + compatible = "qcom,i2c-pmic"; + reg = <0x69>; + qcom,can-sleep; + }; + + qcom,idt9418@3b { + compatible = "qcom,i2c-pmic"; + reg = <0x3b>; + qcom,can-sleep; + }; + }; +}; From ae98f1e70e069f34c38ac5d9aca8a035358d08cc Mon Sep 17 00:00:00 2001 From: David Collins Date: Wed, 25 Oct 2023 14:10:07 -0700 Subject: [PATCH 4/4] ARM: dts: qcom: add primary SPMI debug bus for Sun boards Add an SPMI debug device and associated PMIC child devices for the primary SPMI interface. This provides consumers with unrestricted access to the PMIC registers on pre-production devices. This helps to simplify debugging. Change-Id: I920a3655e0e257ee819c7227e154d27ee43f3250 Signed-off-by: David Collins --- qcom/sun.dtsi | 109 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 109 insertions(+) diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index 5f1d429d..5e3d084d 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -1646,6 +1646,115 @@ status = "disabled"; }; + spmi0_debug_bus: spmi-debug@10b14000 { + compatible = "qcom,spmi-pmic-arb-debug"; + reg = <0x10b14000 0x60>, <0x221c8784 0x4>; + reg-names = "core", "fuse"; + clocks = <&aoss_qmp>; + clock-names = "core_clk"; + qcom,fuse-enable-bit = <18>; + #address-cells = <2>; + #size-cells = <0>; + depends-on-supply = <&spmi_bus>; + depends-on2-supply = <&pmih010x_glink_debug>; + + pmk8550@0 { + compatible = "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + pm8550@1 { + compatible = "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + pm8550ve@3 { + compatible = "qcom,spmi-pmic"; + reg = <0x3 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + pmd802x@4 { + compatible = "qcom,spmi-pmic"; + reg = <0x4 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + pm8550vs@5 { + compatible = "qcom,spmi-pmic"; + reg = <0x5 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + pm8550ve@6 { + compatible = "qcom,spmi-pmic"; + reg = <0x6 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + pmih010x@7 { + compatible = "qcom,spmi-pmic"; + reg = <0x7 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + pm8550ve@8 { + compatible = "qcom,spmi-pmic"; + reg = <0x8 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + pm8550vs@9 { + compatible = "qcom,spmi-pmic"; + reg = <0x9 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + pmr735d@a { + compatible = "qcom,spmi-pmic"; + reg = <0xa SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + pm8010@c { + compatible = "qcom,spmi-pmic"; + reg = <0xc SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + pm8010@d { + compatible = "qcom,spmi-pmic"; + reg = <0xd SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + }; + qcom,msm-adsprpc-mem { compatible = "qcom,msm-adsprpc-mem-region"; memory-region = <&adsp_mem_heap>;