From 0df85d38624f3779d3efe05c3dd9c94eb56fc595 Mon Sep 17 00:00:00 2001 From: Sarannya S Date: Thu, 25 Apr 2024 15:48:51 +0530 Subject: [PATCH 01/54] ARM: dts: msm: Add glink probe entry for Sun Add glink probe driver entry for Sun to have a way for glink core to get pm notifications during apps suspend/resume. Change-Id: I0f27ac9377cd6818f4c60cace116bdefc935ab88 Signed-off-by: Sarannya S --- qcom/sun.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index 6e2bc13c..4fc05980 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -683,6 +683,10 @@ }; }; + qcom,glink { + compatible = "qcom,glink"; + }; + qcom,qsee_ipc_irq_bridge { compatible = "qcom,qsee-ipc-irq-bridge"; From 9a679f13c344c1618840ee459508a94e75a8a314 Mon Sep 17 00:00:00 2001 From: Anaadi Mishra Date: Fri, 24 May 2024 16:18:41 +0530 Subject: [PATCH 02/54] dt-bindings: clock: qcom: add GPU clock controller bindings on tuna Add GPU clock controller bindings on tuna device. Change-Id: Iabde510426d9eef51f65d1f5161ddb79bf643429 Signed-off-by: Anaadi Mishra --- bindings/clock/qcom,gpucc.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/bindings/clock/qcom,gpucc.yaml b/bindings/clock/qcom,gpucc.yaml index ecf3cd6a..ccdb4c98 100644 --- a/bindings/clock/qcom,gpucc.yaml +++ b/bindings/clock/qcom,gpucc.yaml @@ -26,6 +26,7 @@ description: | dt-bindings/clock/qcom,gpucc-sun.h dt-bindings/clock/qcom,gpucc-parrot.h dt-bindings/clock/qcom,gpucc-monaco.h + dt-bindings/clock/qcom,gpucc-tuna.h properties: compatible: @@ -43,6 +44,7 @@ properties: - qcom,sun-gpucc - qcom,parrot-gpucc - qcom,monaco-gpucc + - qcom,tuna-gpucc clocks: items: From 791caa032264aedf616000165f81e434ea95c4d3 Mon Sep 17 00:00:00 2001 From: Anaadi Mishra Date: Fri, 24 May 2024 13:59:14 +0530 Subject: [PATCH 03/54] ARM: dts: msm: Add support for graphics clock controller on TUNA Add support for GPU clock controller and move corresponding CX/GX gdsc's from dummy to real on Tuna platform. Change-Id: Idc90b51bf63232dd5e080610ad5438eb6aab129d Signed-off-by: Anaadi Mishra --- qcom/tuna.dtsi | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 85334931..e5328282 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -584,8 +584,17 @@ }; gpucc: clock-controller@3d90000 { - compatible = "qcom,dummycc"; - clock-output-names = "gpucc_clocks"; + compatible = "qcom,tuna-gpucc", "syscon"; + reg = <0x3d90000 0x9800>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CPH_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CPH_CLK_SRC>; + clock-names = "bi_tcxo", + "gpll0_out_main", + "gpll0_out_main_div"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -710,12 +719,13 @@ }; &gpu_cc_cx_gdsc { - compatible = "regulator-fixed"; + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>; + parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &gx_clkctl_gx_gdsc { - compatible = "regulator-fixed"; + parent-supply = <&VDD_GFX_MXC_VOTER_LEVEL>; status = "ok"; }; From 178e39f646d5fe46fea404c3baae7c4be46b3669 Mon Sep 17 00:00:00 2001 From: Unnathi Chalicheemala Date: Tue, 25 Jun 2024 14:07:10 -0700 Subject: [PATCH 04/54] ARM: dts: qcom: Add 3.5mm with Kiwi WLAN for MTP platform Add 3.5mm support with Kiwi WLAN and V8 power grid for MTP platform on Sun. Change-Id: Ib2bd43008d0ffeadade713778fdf30ed64bc2f68 Signed-off-by: Unnathi Chalicheemala --- qcom/Makefile | 1 + qcom/platform_map.bzl | 1 + qcom/sun-mtp-3.5mm-kiwi-v8-overlay.dts | 19 +++++++++++++++++++ qcom/sun-mtp-3.5mm-kiwi-v8.dtsi | 6 ++++++ 4 files changed, 27 insertions(+) create mode 100644 qcom/sun-mtp-3.5mm-kiwi-v8-overlay.dts create mode 100644 qcom/sun-mtp-3.5mm-kiwi-v8.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index ebe62f22..7842dffb 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -19,6 +19,7 @@ SUN_BASE_DTB += sun.dtb sun-v2.dtb sun-tp.dtb sun-tp-v2.dtb SUN_APQ_BASE_DTB += sunp.dtb sunp-v2.dtb sunp-tp.dtb sunp-tp-v2.dtb SUN_BOARDS += \ + sun-mtp-3.5mm-kiwi-v8-overlay.dtbo \ sun-mtp-3.5mm-overlay.dtbo \ sun-mtp-kiwi-overlay.dtbo \ sun-mtp-kiwi-v8-overlay.dtbo \ diff --git a/qcom/platform_map.bzl b/qcom/platform_map.bzl index f70d7b36..aab42d27 100644 --- a/qcom/platform_map.bzl +++ b/qcom/platform_map.bzl @@ -32,6 +32,7 @@ _platform_map = { {"name": "sun-cdp-no-display-overlay.dtbo"}, {"name": "sun-cdp-overlay.dtbo"}, {"name": "sun-cdp-v8-overlay.dtbo"}, + {"name": "sun-mtp-3.5mm-kiwi-v8-overlay.dtbo"}, {"name": "sun-mtp-3.5mm-overlay.dtbo"}, {"name": "sun-mtp-kiwi-overlay.dtbo"}, {"name": "sun-mtp-kiwi-v8-overlay.dtbo"}, diff --git a/qcom/sun-mtp-3.5mm-kiwi-v8-overlay.dts b/qcom/sun-mtp-3.5mm-kiwi-v8-overlay.dts new file mode 100644 index 00000000..e6e99360 --- /dev/null +++ b/qcom/sun-mtp-3.5mm-kiwi-v8-overlay.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-mtp-3.5mm-kiwi-v8.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun MTP with 3.5mm Kiwi WLAN V8 Power Grid"; + compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", + "qcom,mtp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; + qcom,board-id = <0x60108 0>; +}; diff --git a/qcom/sun-mtp-3.5mm-kiwi-v8.dtsi b/qcom/sun-mtp-3.5mm-kiwi-v8.dtsi new file mode 100644 index 00000000..70c2649d --- /dev/null +++ b/qcom/sun-mtp-3.5mm-kiwi-v8.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "sun-mtp-kiwi-v8.dtsi" From 81c3937e65633217a6426cb09fe64a3809dde33d Mon Sep 17 00:00:00 2001 From: Akshay Gola Date: Fri, 28 Jun 2024 17:23:23 +0530 Subject: [PATCH 05/54] ARM: dts: msm: Enable raydium touch driver node Enable raydium touch driver node and add its documentation for bring-up. Change-Id: I00a2d137d452959a555b13f38f971ce08d9173a8 Signed-off-by: Akshay Gola --- bindings/input/touchscreen/raydium_ts.yaml | 80 ++++++++++++++++++++++ qcom/monaco-wdp-v1.dtsi | 40 +++++++++++ 2 files changed, 120 insertions(+) create mode 100644 bindings/input/touchscreen/raydium_ts.yaml diff --git a/bindings/input/touchscreen/raydium_ts.yaml b/bindings/input/touchscreen/raydium_ts.yaml new file mode 100644 index 00000000..965b375a --- /dev/null +++ b/bindings/input/touchscreen/raydium_ts.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/touchscreen/raydium_ts.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Raydium WT030 touch controller + +description: The Raydium Touch controller is connected to + the host processor via I2C. The controller generates + interrupts when the user touches the panel. The host + controller is expected to read the touch coordinates over + I2C and pass the coordinates to the rest of the system. + +maintainers: + - Akshay Gola + +allOf: + - $ref: touchscreen.yaml# + +properties: + compatible: + enum: + - raydium,raydium-ts + + reg: + description: i2c slave address of the device. + + interrupt-parent: + description: parent of interrupt. + + raydium,reset-gpio: + description: reset gpio + + raydium,irq-gpio: + description: irq gpio + + vdd_ana-supply: + description: digital voltage power supply needed to power device. + + vcc_i2c-supply: + description: i2c voltage power supply needed to power device. + +unevaluatedProperties: false + +required: + - compatible + - reg + - interrupt-parent + - raydium,irq-gpio + - raydium,reset-gpio + - vdd_ana-supply + - vcc_i2c-supply + +examples: + - | + i2c@78b7000 { + status = "ok"; + raydium_ts@39 { + compatible = "raydium,raydium-ts"; + reg = <0x39>; + interrupt-parent = <&msm_gpio>; + interrupts = <13 0x2008>; + vdd_ana-supply = <&pm8916_l17>; + vcc_i2c-supply = <&pm8916_l6>; + pinctrl-names ="pmx_ts_active","pmx_ts_suspend","pmx_ts_release"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&ts_release>; + raydium,reset-gpio = <&msm_gpio 12 0x00>; + raydium,irq-gpio = <&msm_gpio 13 0x00>; + raydium,num-max-touches = <2>; + raydium,soft-reset-delay-ms = <50>; + raydium,hard-reset-delay-ms = <100>; + raydium,x_max = <390>; + raydium,y_max = <390>; + raydium,display-coords= <0 0 390 390>; + raydium,fw_id = <0x2202> + }; + }; diff --git a/qcom/monaco-wdp-v1.dtsi b/qcom/monaco-wdp-v1.dtsi index 85fb6846..9e397a3f 100644 --- a/qcom/monaco-wdp-v1.dtsi +++ b/qcom/monaco-wdp-v1.dtsi @@ -6,3 +6,43 @@ #include "monaco-idp-v1.dtsi" #include "monaco-thermal-wdp.dtsi" + + + + + + + + +&qupv3_se1_i2c { + status = "ok"; + + tsc@24 { + compatible = "parade,pt_i2c_adapter"; + reg = <0x24>; + status = "disabled"; + }; + + raydium_ts@39 { + compatible = "raydium,raydium-ts"; + reg = <0x39>; + status = "ok"; + interrupt-parent = <&tlmm>; + interrupts = <13 0x2008>; + vdd_ana-supply = <&L29A>; + vcc_i2c-supply = <&L21A>; + pinctrl-names = "pmx_ts_active","pmx_ts_suspend","pmx_ts_release"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&ts_release>; + raydium,reset-gpio = <&tlmm 12 0x00>; + raydium,irq-gpio = <&tlmm 13 0x00>; + raydium,num-max-touches = <2>; + raydium,soft-reset-delay-ms = <50>; + raydium,hard-reset-delay-ms = <100>; + raydium,x_max = <320>; + raydium,y_max = <360>; + raydium,display-coords= <0 0 320 360>; + }; +}; + From 21061bbb8499fee8de0e5c9b1141893df6f2a583 Mon Sep 17 00:00:00 2001 From: Bibek Kumar Patro Date: Mon, 3 Jun 2024 18:57:45 +0530 Subject: [PATCH 06/54] ARM: dts: msm: add initial memory configuration for kera Add initial memory configuration and reserved memory map for kera, inline with v1. Change-Id: I2b3ed445feebd6141beb59bd23e416711e17747c Signed-off-by: Bibek Kumar Patro Signed-off-by: Vijayanand Jitta --- qcom/kera-reserved-memory.dtsi | 234 +++++++++++++++++++++++++++++++++ qcom/kera.dtsi | 18 +++ 2 files changed, 252 insertions(+) create mode 100644 qcom/kera-reserved-memory.dtsi diff --git a/qcom/kera-reserved-memory.dtsi b/qcom/kera-reserved-memory.dtsi new file mode 100644 index 00000000..8c9df41b --- /dev/null +++ b/qcom/kera-reserved-memory.dtsi @@ -0,0 +1,234 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gunyah_hyp_mem: gunyah_hyp_region@80000000 { + no-map; + reg = <0x0 0x80000000 0x0 0xe00000>; + }; + + cpusys_vm_mem: cpusys_vm_region@80e00000 { + no-map; + reg = <0x0 0x80e00000 0x0 0x400000>; + }; + + cpucp_pdp_mem: cpucp_region@81200000 { + no-map; + reg = <0x0 0x81200000 0x0 0x200000>; + }; + + /* + * hyp_tags_mem is dynamically removed from the RAM + * partition tables before boot occurs. Size of region + * varies. + */ + + xbl_dtlog_mem: xbl_dtlog_region@81a00000 { + no-map; + reg = <0x0 0x81a00000 0x0 0x40000>; + }; + + aop_image_mem: aop_image_region@81c00000 { + no-map; + reg = <0x0 0x81c00000 0x0 0x60000>; + }; + + aop_cmd_db_mem: aop_cmd_db_region@81c60000 { + compatible = "qcom,cmd-db"; + no-map; + reg = <0x0 0x81c60000 0x0 0x20000>; + }; + + aop_config_mem: aop_config_region@81c80000 { + no-map; + reg = <0x0 0x81c80000 0x0 0x20000>; + }; + + tme_crash_dump_mem: tme_crash_dump_region@81ca0000 { + no-map; + reg = <0x0 0x81ca0000 0x0 0x40000>; + }; + + tme_log_mem: tme_log_region@81ce0000 { + no-map; + reg = <0x0 0x81ce0000 0x0 0x4000>; + }; + + uefi_log_mem: uefi_log_region@81ce4000 { + no-map; + reg = <0x0 0x81ce4000 0x0 0x10000>; + }; + + smem_mem: smem_region@81d00000 { + no-map; + reg = <0x0 0x81d00000 0x0 0x200000>; + }; + + pdp_ns_shared_mem: pdp_ns_shared_region@81f00000 { + no-map; + reg = <0x0 0x81f00000 0x0 0x100000>; + }; + + cpucp_scandump_mem: cpucp_scandump_region@82000000 { + no-map; + reg = <0x0 0x82000000 0x0 0x380000>; + }; + + adsp_mhi_mem: adsp_mhi_region@82380000 { + no-map; + reg = <0x0 0x82380000 0x0 0x20000>; + }; + + soccp_sdi_mem: soccp_sdi_region@823a0000 { + no-map; + reg = <0x0 0x823a0000 0x0 0x40000>; + }; + + pmic_minii_dump_mem: pmic_minii_dump_region@823e0000 { + no-map; + reg = <0x0 0x823e0000 0x0 0x80000>; + }; + + pvm_fw_mem: pvm_fw_region@824a0000 { + no-map; + reg = <0x0 0x824a0000 0x0 0x100000>; + }; + + hyp_mem_database_mem: hyp_mem_database_region@825a0000 { + no-map; + reg = <0x0 0x825a0000 0x0 0x60000>; + }; + + global_sync_mem: global_sync_region@82600000 { + no-map; + reg = <0x0 0x82600000 0x0 0x100000>; + }; + + tz_stat_mem: tz_stat_region@82700000 { + no-map; + reg = <0x0 0x82700000 0x0 0x100000>; + }; + + dsm_partition_1_mem: dsm_partition_1_region@84a00000 { + no-map; + reg = <0x0 0x84a00000 0x0 0x4900000>; + }; + + dsm_partition_2_mem: dsm_partition_2_region@89300000 { + no-map; + reg = <0x0 0x89300000 0x0 0xa80000>; + }; + + mpss_mem: mpss_region@89e00000 { + no-map; + reg = <0x0 0x89e00000 0x0 0x11200000>; + }; + + q6_mpss_dtb_mem: q6_mpss_dtb_region@9b000000 { + no-map; + reg = <0x0 0x9b000000 0x0 0x80000>; + }; + + ipa_fw_mem: ipa_fw_region@9b080000 { + no-map; + reg = <0x0 0x9b080000 0x0 0x10000>; + }; + + ipa_gsi_mem: ipa_gsi_region@9b090000 { + no-map; + reg = <0x0 0x9b090000 0x0 0xa000>; + }; + + gpu_microcode_mem: gpu_microcode_region@9b09a000 { + no-map; + reg = <0x0 0x9b09a000 0x0 0x2000>; + }; + + camera_mem: camera_region@9b300000 { + no-map; + reg = <0x0 0x9b300000 0x0 0x800000>; + }; + + camera_2_mem: camera_2_region@9bb00000 { + no-map; + reg = <0x0 0x9bb00000 0x0 0x800000>; + }; + + video_mem: video_region@9c300000 { + no-map; + reg = <0x0 0x9c300000 0x0 0x800000>; + }; + + cvp_mem: cvp_region@9cb00000 { + no-map; + reg = <0x0 0x9cb00000 0x0 0x700000>; + }; + + cdsp_mem: cdsp_region@9d200000 { + no-map; + reg = <0x0 0x9d200000 0x0 0x2000000>; + }; + + q6_cdsp_dtb_mem: q6_cdsp_dtb_region@9f200000 { + no-map; + reg = <0x0 0x9f200000 0x0 0x80000>; + }; + + q6_adsp_dtb_mem: q6_adsp_dtb_region@9f280000 { + no-map; + reg = <0x0 0x9f280000 0x0 0x80000>; + }; + + adspslpi_mem: adspslpi_region@9f300000 { + no-map; + reg = <0x0 0x9f300000 0x0 0x4080000>; + }; + + soccp_mem: soccp_region@a3380000 { + no-map; + reg = <0x0 0xa3380000 0x0 0x180000>; + }; + + wpss_mem: wpss_region@a3500000 { + no-map; + reg = <0x0 0xa3500000 0x0 0x1900000>; + }; + + wlan_msa_mem: wlan_msa_region@a6400000 { + no-map; + reg = <0x0 0xa6400000 0x0 0xc00000>; + }; + + /* uefi region can be reused by apps */ + + /* Linux kernel image is loaded at 0xa8000000 */ + + xbl_ramdump_mem: xbl_ramdump_region@b8000000 { + no-map; + reg = <0x0 0xb8000000 0x0 0x1c0000>; + }; + + /* merged tz_reserved, xbl_sc, and qtee regions */ + tz_merged_mem: tz_merged_region@d8000000 { + no-map; + reg = <0x0 0xd8000000 0x0 0x600000>; + }; + + /* + * ta/tags mem is dynamically removed from the RAM + * partition tables before boot occurs. Size of region + * varies. + */ + + llcc_lpi_mem: llcc_lpi_region@ff800000 { + no-map; + reg = <0x0 0xff800000 0x0 0x400000>; + }; + +}; diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 0036927e..7ff9aa92 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -212,6 +212,24 @@ }; }; +#include "kera-reserved-memory.dtsi" + +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + system_cma: linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2000000>; + linux,cma-default; + }; +}; + &soc { #address-cells = <1>; #size-cells = <1>; From d076a78f32f8a871cb3f878d9bd7a8fbc2a51734 Mon Sep 17 00:00:00 2001 From: Bibek Kumar Patro Date: Tue, 4 Jun 2024 15:08:45 +0530 Subject: [PATCH 07/54] ARM: dts: msm: Add initial SMMU configuration for kera Add initial apps and gpu SMMU configuration for kera. Change-Id: I98949dccd2f5a005e9d9bf8fc6923f777ca4b6a7 Signed-off-by: Bibek Kumar Patro Signed-off-by: Vijayanand Jitta --- qcom/kera.dtsi | 1 + qcom/msm-arm-smmu-kera.dtsi | 300 ++++++++++++++++++++++++++++++++++++ 2 files changed, 301 insertions(+) create mode 100644 qcom/msm-arm-smmu-kera.dtsi diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 7ff9aa92..efa7e969 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -213,6 +213,7 @@ }; #include "kera-reserved-memory.dtsi" +#include "msm-arm-smmu-kera.dtsi" &reserved_memory { #address-cells = <2>; diff --git a/qcom/msm-arm-smmu-kera.dtsi b/qcom/msm-arm-smmu-kera.dtsi new file mode 100644 index 00000000..a18d50fe --- /dev/null +++ b/qcom/msm-arm-smmu-kera.dtsi @@ -0,0 +1,300 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + kgsl_smmu: kgsl-smmu@3da0000 { + compatible = "qcom,qsmmu-v500", "qcom,adreno-smmu"; + reg = <0x3da0000 0x40000>; + #iommu-cells = <2>; + qcom,use-3-lvl-tables; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + dma-coherent; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + gpu_qtb: gpu_qtb@03de8000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x3de8000 0x1000>; + qcom,stream-id-range = <0x0 0x400>; + qcom,iova-width = <49>; + qcom,num-qtb-ports = <2>; + }; + }; + + apps_smmu: apps-smmu@15000000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15000000 0x100000>; + #iommu-cells = <2>; + qcom,use-3-lvl-tables; + qcom,handoff-smrs = <0x800 0x2>; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + dma-coherent; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + anoc_1_qtb: anoc_1_qtb@16f2000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x16f2000 0x1000>; + qcom,stream-id-range = <0x0 0x400>; + qcom,iova-width = <36>; + qcom,num-qtb-ports = <1>; + }; + + anoc_2_qtb: anoc_2_qtb@171b000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x171b000 0x1000>; + qcom,stream-id-range = <0x400 0x400>; + qcom,iova-width = <36>; + qcom,num-qtb-ports = <1>; + }; + + cam_hf_qtb: cam_hf_qtb@17f7000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x17f7000 0x1000>; + qcom,stream-id-range = <0x1c00 0x400>; + qcom,iova-width = <32>; + qcom,num-qtb-ports = <2>; + }; + + nsp_qtb: nsp_qtb@7d3000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x7d3000 0x1000>; + qcom,stream-id-range = <0xc00 0x400>; + qcom,iova-width = <32>; + qcom,num-qtb-ports = <2>; + }; + + lpass_qtb: lpass_qtb@7b3000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x7b3000 0x1000>; + qcom,stream-id-range = <0x1000 0x400>; + qcom,iova-width = <32>; + qcom,num-qtb-ports = <1>; + }; + + pcie_qtb: pcie_qtb@16cd000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x16cd000 0x1000>; + qcom,stream-id-range = <0x1400 0x400>; + qcom,iova-width = <32>; + qcom,num-qtb-ports = <1>; + qcom,opt-out-tbu-halting; + }; + + sf_qtb: sf_qtb@17b7000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x17b7000 0x1000>; + qcom,stream-id-range = <0x1800 0x400>; + qcom,iova-width = <32>; + qcom,num-qtb-ports = <2>; + }; + + mdp_hf_qtb: mdp_hf_qtb@17f6000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x17f6000 0x1000>; + qcom,stream-id-range = <0x800 0x400>; + qcom,iova-width = <36>; + qcom,num-qtb-ports = <2>; + }; + + }; + + dma_dev { + compatible = "qcom,iommu-dma"; + memory-region = <&system_cma>; + }; + + iommu_test_device { + compatible = "qcom,iommu-debug-test"; + #address-cells = <2>; + #size-cells = <2>; + + usecase0_apps { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x400 0x0>; + }; + + usecase1_apps_fastmap { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x400 0x0>; + qcom,iommu-dma = "fastmap"; + }; + + usecase2_apps_atomic { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x400 0x0>; + qcom,iommu-dma = "atomic"; + }; + + usecase3_apps_dma { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x400 0x0>; + dma-coherent; + }; + + usecase4_apps_secure { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x400 0x0>; + qcom,iommu-vmid = <0xa>; /* VMID_CP_PIXEL */ + }; + + usecase5_kgsl { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&kgsl_smmu 0x7 0x0>; + }; + + usecase6_kgsl_dma { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&kgsl_smmu 0x7 0x0>; + dma-coherent; + }; + }; + +}; From 5ac00ac9638d30fbd9d496f23f1bc8712326ec2b Mon Sep 17 00:00:00 2001 From: Vijayanand Jitta Date: Mon, 1 Jul 2024 11:17:49 +0530 Subject: [PATCH 08/54] ARM: dts: msm: Add DMA-BUF heaps node for kera Add the DMA-BUF heaps node for kera. This adds default heaps like system and secure-system heap. Clients can add their own DMA-BUF heaps in here. Change-Id: Iee72407be99b936e22f5cf4b5eb55b302fed5cac Signed-off-by: Vijayanand Jitta --- qcom/kera-dma-heaps.dtsi | 13 +++++++++++++ qcom/kera.dtsi | 1 + 2 files changed, 14 insertions(+) create mode 100644 qcom/kera-dma-heaps.dtsi diff --git a/qcom/kera-dma-heaps.dtsi b/qcom/kera-dma-heaps.dtsi new file mode 100644 index 00000000..6472b080 --- /dev/null +++ b/qcom/kera-dma-heaps.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + qcom,dma-heaps { + compatible = "qcom,dma-heaps"; + depends-on-supply = <&qcom_scm>; + }; +}; diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index efa7e969..11101240 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -214,6 +214,7 @@ #include "kera-reserved-memory.dtsi" #include "msm-arm-smmu-kera.dtsi" +#include "kera-dma-heaps.dtsi" &reserved_memory { #address-cells = <2>; From e3f180676582a0f67378d4389b35c5e3157f1a8b Mon Sep 17 00:00:00 2001 From: Prakash Yadachi Date: Thu, 11 Jul 2024 10:34:40 +0530 Subject: [PATCH 09/54] ARM: dts: qcom: Update proper clock name Update uart clock name from se to se-clk for Ravelin. Change-Id: Ib2b614ba3a0f2bf307e7fa7678a10ccfe97da1c1 Signed-off-by: Prakash Yadachi --- qcom/ravelin-qupv3.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/ravelin-qupv3.dtsi b/qcom/ravelin-qupv3.dtsi index 904c2722..b3017389 100644 --- a/qcom/ravelin-qupv3.dtsi +++ b/qcom/ravelin-qupv3.dtsi @@ -76,7 +76,7 @@ reg-names = "se_phys"; interrupts-extended = <&intc GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, <&tlmm 17 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "se"; + clock-names = "se-clk"; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = From 15e281f23e8d865f0b81b82a505f6085d7e6f09e Mon Sep 17 00:00:00 2001 From: Amir Vajid Date: Tue, 12 Dec 2023 12:47:30 -0800 Subject: [PATCH 10/54] ARM: dts: msm: Map llcc gold bwmon as non-early for sun Update llcc gold bwmon to have its memory mapped as non-early for sun. Change-Id: I190283c136736b069eaed6805f5813ceb0c2d38f Signed-off-by: Amir Vajid --- qcom/sun.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index 2cd07115..ca1b1d8f 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -3468,6 +3468,7 @@ reg = <0x240B3400 0x300>, <0x240B3300 0x200>; reg-names = "base", "global_base"; interrupts = ; + qcom,map-ne; qcom,mport = <0>; qcom,hw-timer-hz = <19200000>; qcom,count-unit = <0x10000>; From c856ee5768adc3b1c031e458e0e484b8d04844a9 Mon Sep 17 00:00:00 2001 From: songrui Date: Fri, 12 Jul 2024 10:55:00 +0800 Subject: [PATCH 11/54] ARM: dts: qcom: add UIDs for QTEE service in sun OEMVM "3" is uid of the CApploader which is running on QTEE. Change-Id: I2e058b3e1687cbcde3e6b8b2564731aac6f46903 Signed-off-by: songrui --- qcom/sun-oemvm.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sun-oemvm.dtsi b/qcom/sun-oemvm.dtsi index 1e14534e..fe156b2b 100644 --- a/qcom/sun-oemvm.dtsi +++ b/qcom/sun-oemvm.dtsi @@ -69,7 +69,7 @@ vendor = "QTI"; image-name = "qcom,oemvm"; qcom,pasid = <0x0 0x22>; - qcom,qtee-config-info = "p=9,39,7C,8F,97,159,7F1,CDF;"; + qcom,qtee-config-info = "p=3,9,39,7C,8F,97,159,7F1,CDF;"; qcom,secdomain-ids = <49>; qcom,primary-vm-index = <0>; vm-uri = "vmuid/oemvm"; From 23636e49925f8c9e5d4fbce946a63a6931cdad52 Mon Sep 17 00:00:00 2001 From: Srinivasarao Pathipati Date: Fri, 12 Jul 2024 14:48:18 +0530 Subject: [PATCH 12/54] ARM: dts: msm: parrot: Add msgq-names property for Parrot The commit 39dd329a019b ("mem-buf-msgq: Support multiple msgqs") mandates to have 'msgq-names' property in node 'mem-buf-msgq'. Adding default msgq entry to fix probe failure. Change-Id: Ie882ae87864a0afbed267e4be88573d4c4b41cb3 Signed-off-by: Srinivasarao Pathipati --- qcom/parrot.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/parrot.dtsi b/qcom/parrot.dtsi index 3235f238..d35f04e1 100644 --- a/qcom/parrot.dtsi +++ b/qcom/parrot.dtsi @@ -2032,6 +2032,7 @@ qcom,mem-buf-msgq { compatible = "qcom,mem-buf-msgq"; + qcom,msgq-names = "trusted_vm"; }; trust_ui_vm: qcom,trust_ui_vm@e55fc000 { From 6173d74ff41edf47ff4dd0bc9c0f16af1404c2a8 Mon Sep 17 00:00:00 2001 From: Pradnya Dahiwale Date: Mon, 8 Jul 2024 14:58:21 +0530 Subject: [PATCH 13/54] ARM: dts: msm: remove dload compatible for monaco Remove dload compatible since scm driver is loading dload module in monaco. Change-Id: I7cb6e02fcbc20468cab863923acccc960700eedd Signed-off-by: Pradnya Dahiwale --- qcom/monaco.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index b1777b35..896f6594 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -535,10 +535,6 @@ }; }; - dload_mode { - compatible = "qcom,dload-mode"; - }; - mini_dump_mode { compatible = "qcom,minidump"; status = "ok"; From 00b7d1455c90283a0631cafa0dc78fa5b532e4f7 Mon Sep 17 00:00:00 2001 From: Uttkarsh Aggarwal Date: Tue, 28 May 2024 10:12:00 +0530 Subject: [PATCH 14/54] ARM: dts: msm: Enable SMMU in tuna Enable SMMU for the USB controller on tuna. Note: Currently in bypass mode. Change-Id: If60f552246306b2f73527b2cd8cbb6a9396eeaad Signed-off-by: Uttkarsh Aggarwal --- qcom/tuna-usb.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/tuna-usb.dtsi b/qcom/tuna-usb.dtsi index cb065d25..21c1cea6 100644 --- a/qcom/tuna-usb.dtsi +++ b/qcom/tuna-usb.dtsi @@ -39,6 +39,11 @@ compatible = "snps,dwc3"; reg = <0xa600000 0xd93c>; + iommus = <&apps_smmu 0x40 0x0>; + qcom,iommu-dma = "bypass"; + qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + dma-coherent; + interrupts = ; snps,disable-clk-gating; snps,has-lpm-erratum; From 37943fdc917f5e45654297638e1bdc52ffb3bf36 Mon Sep 17 00:00:00 2001 From: Uttkarsh Aggarwal Date: Tue, 16 Jul 2024 10:14:49 +0530 Subject: [PATCH 15/54] ARM: dts: msm: Setting IOMMU to atomic in tuna In this change switching from "bypass" to "atomic" for tuna. Change-Id: Iae14cab97f4e98d6bd6cc350f61e5cfb4a97f7fc Signed-off-by: Uttkarsh Aggarwal --- qcom/tuna-usb.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/tuna-usb.dtsi b/qcom/tuna-usb.dtsi index 21c1cea6..88fa476e 100644 --- a/qcom/tuna-usb.dtsi +++ b/qcom/tuna-usb.dtsi @@ -40,7 +40,7 @@ reg = <0xa600000 0xd93c>; iommus = <&apps_smmu 0x40 0x0>; - qcom,iommu-dma = "bypass"; + qcom,iommu-dma = "atomic"; qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; dma-coherent; From e0529a17d736cea41ffa37af36d0635a904e03ed Mon Sep 17 00:00:00 2001 From: Prakash Yadachi Date: Tue, 2 Jul 2024 12:41:44 +0530 Subject: [PATCH 16/54] ARM: dts: msm: Add interconnect-names for Ravelin Add interconnect-names qup-core,qup-config and qup-memory to all qupv3 nodes. Change-Id: I6cbed2a84fcd1ae7df96253121fc2dc735110b34 Signed-off-by: Prakash Yadachi --- qcom/ravelin-qupv3.dtsi | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/qcom/ravelin-qupv3.dtsi b/qcom/ravelin-qupv3.dtsi index aeceb616..5135a2ab 100644 --- a/qcom/ravelin-qupv3.dtsi +++ b/qcom/ravelin-qupv3.dtsi @@ -95,7 +95,7 @@ reg = <0x980000 0x4000>; reg-names = "se_phys"; interrupts = ; - interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, @@ -114,7 +114,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = ; - interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, @@ -135,7 +135,7 @@ reg = <0x984000 0x4000>; #address-cells = <1>; #size-cells = <0>; - interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, @@ -159,7 +159,7 @@ #size-cells = <0>; reg-names = "se_phys"; interrupts = ; - interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, @@ -182,7 +182,7 @@ reg = <0x98c000 0x4000>; #address-cells = <1>; #size-cells = <0>; - interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, @@ -206,7 +206,7 @@ #size-cells = <0>; reg-names = "se_phys"; interrupts = ; - interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, @@ -230,7 +230,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = ; - interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, @@ -253,7 +253,7 @@ #size-cells = <0>; reg-names = "se_phys"; interrupts = ; - interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, @@ -342,7 +342,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = ; - interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, @@ -365,7 +365,7 @@ #size-cells = <0>; reg-names = "se_phys"; interrupts = ; - interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, @@ -389,7 +389,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = ; - interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, @@ -412,7 +412,7 @@ #size-cells = <0>; reg-names = "se_phys"; interrupts = ; - interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, @@ -436,7 +436,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = ; - interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, @@ -460,7 +460,7 @@ #size-cells = <0>; reg-names = "se_phys"; interrupts = ; - interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, @@ -484,7 +484,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = ; - interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, @@ -507,7 +507,7 @@ #size-cells = <0>; reg-names = "se_phys"; interrupts = ; - interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, From fab52d3dce5c0ffddb242c439d395c55508560ad Mon Sep 17 00:00:00 2001 From: Jagadeesh Ponduru Date: Tue, 9 Jul 2024 11:50:15 +0530 Subject: [PATCH 17/54] ARM: dts: msm: Add smp2p ipa nodes for ravelin Add the smp2p ipa device nodes to enable smp2p communication with remote processors. Change-Id: Ie59a7317e227cce4d02a600f542ac2dcdba6e421 Signed-off-by: Pavan Kumar M Signed-off-by: Jagadeesh Ponduru --- qcom/ravelin.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/qcom/ravelin.dtsi b/qcom/ravelin.dtsi index 813f3c80..09fc3050 100644 --- a/qcom/ravelin.dtsi +++ b/qcom/ravelin.dtsi @@ -1081,6 +1081,17 @@ #interrupt-cells = <2>; }; + smp2p_ipa_1_out: qcom,smp2p-ipa-1-out { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + /* ipa - inbound entry from mss */ + smp2p_ipa_1_in: qcom,smp2p-ipa-1-in { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; }; qcom,smp2p-adsp { From e09af43a4a09350cdebfa59394a19ceb4aa96055 Mon Sep 17 00:00:00 2001 From: Swetha Chikkaboraiah Date: Wed, 10 Jul 2024 17:19:49 +0530 Subject: [PATCH 18/54] ARM: dts: msm: Add initial device tree for ravelin Gaming Variant Add initial device tree support for ravelin Gaming variant. This is a snapshot of dtsi files as of KP.1.0 'commit <370d8eab7cc6> ("Merge "ARM: dts: qcom: Disable cnss-kiwi SOL on anorak platform"")'. Modified as per compilation and bootup. Change-Id: Id02d9765147e54d44713c36f7a1b10cb6a627d44 Signed-off-by: Swetha Chikkaboraiah --- qcom/Makefile | 4 ++-- qcom/platform_map.bzl | 2 ++ qcom/ravelin-atp-overlay.dts | 2 +- qcom/ravelin-idp-overlay.dts | 2 +- qcom/ravelin-idp-wcn3950-amoled-rcm-overlay.dts | 2 +- qcom/ravelin-idp-wcn3988-4gb-overlay.dts | 2 +- qcom/ravelin-qrd-4gb-overlay.dts | 2 +- qcom/ravelin-qrd-overlay.dts | 3 ++- qcom/ravelin-sg-atp.dts | 16 ++++++++++++++++ qcom/ravelin-sg-atp.dtsi | 6 ++++++ qcom/ravelin-sg-idp-wcn3950-amoled-rcm.dts | 15 +++++++++++++++ qcom/ravelin-sg-idp-wcn3950-amoled-rcm.dtsi | 7 +++++++ qcom/ravelin-sg-idp-wcn3988-4gb.dts | 15 +++++++++++++++ qcom/ravelin-sg-idp-wcn3988-4gb.dtsi | 6 ++++++ qcom/ravelin-sg-idp.dts | 16 ++++++++++++++++ qcom/ravelin-sg-idp.dtsi | 6 ++++++ qcom/ravelin-sg-qrd-4gb.dts | 16 ++++++++++++++++ qcom/ravelin-sg-qrd-4gb.dtsi | 7 +++++++ qcom/ravelin-sg-qrd.dts | 17 +++++++++++++++++ qcom/ravelin-sg-qrd.dtsi | 6 ++++++ qcom/ravelin-sg.dts | 15 +++++++++++++++ qcom/ravelin-sg.dtsi | 13 +++++++++++++ qcom/ravelinp-sg-atp.dts | 16 ++++++++++++++++ qcom/ravelinp-sg-atp.dtsi | 6 ++++++ qcom/ravelinp-sg-idp-wcn3950-amoled-rcm.dts | 15 +++++++++++++++ qcom/ravelinp-sg-idp-wcn3950-amoled-rcm.dtsi | 7 +++++++ qcom/ravelinp-sg-idp-wcn3988-4gb.dts | 15 +++++++++++++++ qcom/ravelinp-sg-idp-wcn3988-4gb.dtsi | 6 ++++++ qcom/ravelinp-sg-idp.dts | 16 ++++++++++++++++ qcom/ravelinp-sg-idp.dtsi | 6 ++++++ qcom/ravelinp-sg-qrd-4gb.dts | 16 ++++++++++++++++ qcom/ravelinp-sg-qrd-4gb.dtsi | 7 +++++++ qcom/ravelinp-sg-qrd.dts | 17 +++++++++++++++++ qcom/ravelinp-sg-qrd.dtsi | 6 ++++++ qcom/ravelinp-sg.dts | 15 +++++++++++++++ qcom/ravelinp-sg.dtsi | 13 +++++++++++++ 36 files changed, 333 insertions(+), 8 deletions(-) create mode 100644 qcom/ravelin-sg-atp.dts create mode 100644 qcom/ravelin-sg-atp.dtsi create mode 100644 qcom/ravelin-sg-idp-wcn3950-amoled-rcm.dts create mode 100644 qcom/ravelin-sg-idp-wcn3950-amoled-rcm.dtsi create mode 100644 qcom/ravelin-sg-idp-wcn3988-4gb.dts create mode 100644 qcom/ravelin-sg-idp-wcn3988-4gb.dtsi create mode 100644 qcom/ravelin-sg-idp.dts create mode 100644 qcom/ravelin-sg-idp.dtsi create mode 100644 qcom/ravelin-sg-qrd-4gb.dts create mode 100644 qcom/ravelin-sg-qrd-4gb.dtsi create mode 100644 qcom/ravelin-sg-qrd.dts create mode 100644 qcom/ravelin-sg-qrd.dtsi create mode 100644 qcom/ravelin-sg.dts create mode 100644 qcom/ravelin-sg.dtsi create mode 100644 qcom/ravelinp-sg-atp.dts create mode 100644 qcom/ravelinp-sg-atp.dtsi create mode 100644 qcom/ravelinp-sg-idp-wcn3950-amoled-rcm.dts create mode 100644 qcom/ravelinp-sg-idp-wcn3950-amoled-rcm.dtsi create mode 100644 qcom/ravelinp-sg-idp-wcn3988-4gb.dts create mode 100644 qcom/ravelinp-sg-idp-wcn3988-4gb.dtsi create mode 100644 qcom/ravelinp-sg-idp.dts create mode 100644 qcom/ravelinp-sg-idp.dtsi create mode 100644 qcom/ravelinp-sg-qrd-4gb.dts create mode 100644 qcom/ravelinp-sg-qrd-4gb.dtsi create mode 100644 qcom/ravelinp-sg-qrd.dts create mode 100644 qcom/ravelinp-sg-qrd.dtsi create mode 100644 qcom/ravelinp-sg.dts create mode 100644 qcom/ravelinp-sg.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index 50bec119..811ed5fe 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -130,8 +130,8 @@ parrot-dtb-$(CONFIG_ARCH_PARROT) += \ parrot-overlays-dtb-$(CONFIG_ARCH_PARROT) += $(PARROT_BOARDS) $(PARROT_BASE_DTB) $(PARROT_4GB_BOARDS) $(PARROT_4GB_BASE_DTB) dtb-y += $(parrot-dtb-y) -RAVELIN_BASE_DTB += ravelin.dtb ravelinp.dtb -RAVELIN_4GB_BASE_DTB += ravelin-4gb.dtb ravelinp-4gb.dtb +RAVELIN_BASE_DTB += ravelin.dtb ravelinp.dtb ravelin-sg.dtb ravelinp-sg.dtb +RAVELIN_4GB_BASE_DTB += ravelin-4gb.dtb ravelinp-4gb.dtb ravelin-sg.dtb ravelinp-sg.dtb RAVELIN_BOARDS += \ ravelin-rumi-overlay.dtbo \ diff --git a/qcom/platform_map.bzl b/qcom/platform_map.bzl index deb66a79..79d4aeef 100644 --- a/qcom/platform_map.bzl +++ b/qcom/platform_map.bzl @@ -195,6 +195,8 @@ _platform_map = { {"name": "ravelinp.dtb"}, {"name": "ravelin-4gb.dtb"}, {"name": "ravelinp-4gb.dtb"}, + {"name": "ravelin-sg.dtb"}, + {"name": "ravelinp-sg.dtb"}, ], "dtbo_list": [ # keep sorted diff --git a/qcom/ravelin-atp-overlay.dts b/qcom/ravelin-atp-overlay.dts index 7ea7d64b..afffb52e 100644 --- a/qcom/ravelin-atp-overlay.dts +++ b/qcom/ravelin-atp-overlay.dts @@ -11,6 +11,6 @@ / { model = "Qualcomm Technologies, Inc. Ravelin ATP"; compatible = "qcom,ravelin-atp", "qcom,ravelin", "qcom,atp"; - qcom,msm-id = <568 0x10000>, <602 0x10000>; + qcom,msm-id = <568 0x10000>, <602 0x10000>, <653 0x10000>, <654 0x10000>; qcom,board-id = <33 0>; }; diff --git a/qcom/ravelin-idp-overlay.dts b/qcom/ravelin-idp-overlay.dts index e46b8a1e..e888ce71 100644 --- a/qcom/ravelin-idp-overlay.dts +++ b/qcom/ravelin-idp-overlay.dts @@ -11,6 +11,6 @@ / { model = "Qualcomm Technologies, Inc. Ravelin IDP"; compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp"; - qcom,msm-id = <568 0x10000>, <602 0x10000>; + qcom,msm-id = <568 0x10000>, <602 0x10000>, <653 0x10000>, <654 0x10000>; qcom,board-id = <34 0>; }; diff --git a/qcom/ravelin-idp-wcn3950-amoled-rcm-overlay.dts b/qcom/ravelin-idp-wcn3950-amoled-rcm-overlay.dts index 8f917453..41248f2a 100644 --- a/qcom/ravelin-idp-wcn3950-amoled-rcm-overlay.dts +++ b/qcom/ravelin-idp-wcn3950-amoled-rcm-overlay.dts @@ -11,6 +11,6 @@ / { model = "Qualcomm Technologies, Inc. Ravelin WCN3950 IDP + AMOLED + RCM"; compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp"; - qcom,msm-id = <568 0x10000>, <602 0x10000>; + qcom,msm-id = <568 0x10000>, <602 0x10000>, <653 0x10000>, <654 0x10000>; qcom,board-id = <34 2>; }; diff --git a/qcom/ravelin-idp-wcn3988-4gb-overlay.dts b/qcom/ravelin-idp-wcn3988-4gb-overlay.dts index cc8bf2e9..8402b692 100644 --- a/qcom/ravelin-idp-wcn3988-4gb-overlay.dts +++ b/qcom/ravelin-idp-wcn3988-4gb-overlay.dts @@ -11,6 +11,6 @@ / { model = "Qualcomm Technologies, Inc. Ravelin IDP 4GB DDR + WCN3988"; compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp"; - qcom,msm-id = <568 0x10000>, <602 0x10000>; + qcom,msm-id = <568 0x10000>, <602 0x10000>, <653 0x10000>, <654 0x10000>; qcom,board-id = <34 0x601>; }; diff --git a/qcom/ravelin-qrd-4gb-overlay.dts b/qcom/ravelin-qrd-4gb-overlay.dts index ea38d8c4..0909b4cc 100644 --- a/qcom/ravelin-qrd-4gb-overlay.dts +++ b/qcom/ravelin-qrd-4gb-overlay.dts @@ -11,6 +11,6 @@ / { model = "Qualcomm Technologies, Inc. Ravelin QRD 4GB DDR"; compatible = "qcom,ravelin-qrd", "qcom,ravelin", "qcom,qrd"; - qcom,msm-id = <568 0x10000>, <602 0x10000>; + qcom,msm-id = <568 0x10000>, <602 0x10000>, <653 0x10000>, <654 0x10000>; qcom,board-id = <0x1000B 0x600>; }; diff --git a/qcom/ravelin-qrd-overlay.dts b/qcom/ravelin-qrd-overlay.dts index 5de8fb12..762a33d2 100644 --- a/qcom/ravelin-qrd-overlay.dts +++ b/qcom/ravelin-qrd-overlay.dts @@ -11,7 +11,8 @@ / { model = "Qualcomm Technologies, Inc. Ravelin QRD"; compatible = "qcom,ravelin-qrd", "qcom,ravelin", "qcom,qrd"; - qcom,msm-id = <568 0x10000>, <602 0x10000>, <581 0x10000>, <582 0x10000>; + qcom,msm-id = <568 0x10000>, <602 0x10000>, <581 0x10000>, <582 0x10000>, + <653 0x10000>, <654 0x10000>; qcom,board-id = <0x1000B 0>; }; diff --git a/qcom/ravelin-sg-atp.dts b/qcom/ravelin-sg-atp.dts new file mode 100644 index 00000000..95dec91a --- /dev/null +++ b/qcom/ravelin-sg-atp.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelin-sg.dtsi" +#include "ravelin-sg-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin SG ATP"; + compatible = "qcom,ravelin-atp", "qcom,ravelin", "qcom,atp"; + qcom,board-id = <33 0>; +}; + diff --git a/qcom/ravelin-sg-atp.dtsi b/qcom/ravelin-sg-atp.dtsi new file mode 100644 index 00000000..1a4b89e5 --- /dev/null +++ b/qcom/ravelin-sg-atp.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-atp.dtsi" diff --git a/qcom/ravelin-sg-idp-wcn3950-amoled-rcm.dts b/qcom/ravelin-sg-idp-wcn3950-amoled-rcm.dts new file mode 100644 index 00000000..4026ad8d --- /dev/null +++ b/qcom/ravelin-sg-idp-wcn3950-amoled-rcm.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelin-sg.dtsi" +#include "ravelin-sg-idp-wcn3950-amoled-rcm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin SG WCN3950 IDP + AMOLED + RCM"; + compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp"; + qcom,board-id = <34 2>; +}; diff --git a/qcom/ravelin-sg-idp-wcn3950-amoled-rcm.dtsi b/qcom/ravelin-sg-idp-wcn3950-amoled-rcm.dtsi new file mode 100644 index 00000000..787f9e04 --- /dev/null +++ b/qcom/ravelin-sg-idp-wcn3950-amoled-rcm.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-idp-wcn3950-amoled-rcm.dtsi" + diff --git a/qcom/ravelin-sg-idp-wcn3988-4gb.dts b/qcom/ravelin-sg-idp-wcn3988-4gb.dts new file mode 100644 index 00000000..362958cc --- /dev/null +++ b/qcom/ravelin-sg-idp-wcn3988-4gb.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelin-4gb.dtsi" +#include "ravelin-sg-idp-wcn3988-4gb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin SG IDP 4GB DDR + WCN3988"; + compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp"; + qcom,board-id = <34 0x601>; +}; diff --git a/qcom/ravelin-sg-idp-wcn3988-4gb.dtsi b/qcom/ravelin-sg-idp-wcn3988-4gb.dtsi new file mode 100644 index 00000000..b3eb3adb --- /dev/null +++ b/qcom/ravelin-sg-idp-wcn3988-4gb.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-idp-wcn3988-4gb.dtsi" diff --git a/qcom/ravelin-sg-idp.dts b/qcom/ravelin-sg-idp.dts new file mode 100644 index 00000000..381cdcca --- /dev/null +++ b/qcom/ravelin-sg-idp.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelin-sg.dtsi" +#include "ravelin-sg-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin SG IDP"; + compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp"; + qcom,board-id = <34 0>; +}; + diff --git a/qcom/ravelin-sg-idp.dtsi b/qcom/ravelin-sg-idp.dtsi new file mode 100644 index 00000000..122b06c7 --- /dev/null +++ b/qcom/ravelin-sg-idp.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-idp.dtsi" diff --git a/qcom/ravelin-sg-qrd-4gb.dts b/qcom/ravelin-sg-qrd-4gb.dts new file mode 100644 index 00000000..ce83076c --- /dev/null +++ b/qcom/ravelin-sg-qrd-4gb.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelin-4gb.dtsi" +#include "ravelin-sg-qrd-4gb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin SG QRD 4GB DDR"; + compatible = "qcom,ravelin-qrd", "qcom,ravelin", "qcom,qrd"; + qcom,board-id = <0x1000B 0x600>; +}; + diff --git a/qcom/ravelin-sg-qrd-4gb.dtsi b/qcom/ravelin-sg-qrd-4gb.dtsi new file mode 100644 index 00000000..4b5b6f61 --- /dev/null +++ b/qcom/ravelin-sg-qrd-4gb.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-qrd-4gb.dtsi" + diff --git a/qcom/ravelin-sg-qrd.dts b/qcom/ravelin-sg-qrd.dts new file mode 100644 index 00000000..d52cdc6c --- /dev/null +++ b/qcom/ravelin-sg-qrd.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelin-sg.dtsi" +#include "ravelin-sg-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin SG QRD"; + compatible = "qcom,ravelin-qrd", "qcom,ravelin", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; +}; + + diff --git a/qcom/ravelin-sg-qrd.dtsi b/qcom/ravelin-sg-qrd.dtsi new file mode 100644 index 00000000..c0e0c1bc --- /dev/null +++ b/qcom/ravelin-sg-qrd.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-qrd.dtsi" diff --git a/qcom/ravelin-sg.dts b/qcom/ravelin-sg.dts new file mode 100644 index 00000000..a851c7a8 --- /dev/null +++ b/qcom/ravelin-sg.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelin-sg.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin SG SoC"; + compatible = "qcom,ravelin"; + qcom,board-id = <0 0>; +}; + diff --git a/qcom/ravelin-sg.dtsi b/qcom/ravelin-sg.dtsi new file mode 100644 index 00000000..0981fc84 --- /dev/null +++ b/qcom/ravelin-sg.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin.dtsi" + +/ { + + model = "Qualcomm Technologies, Inc. Ravelin SG"; + compatible = "qcom,ravelin"; + qcom,msm-id = <653 0x10000>; +}; diff --git a/qcom/ravelinp-sg-atp.dts b/qcom/ravelinp-sg-atp.dts new file mode 100644 index 00000000..0b8a551f --- /dev/null +++ b/qcom/ravelinp-sg-atp.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelinp-sg.dtsi" +#include "ravelinp-sg-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. RavelinP SG ATP"; + compatible = "qcom,ravelinp-atp", "qcom,ravelinp", "qcom,atp"; + qcom,board-id = <33 0>; +}; + diff --git a/qcom/ravelinp-sg-atp.dtsi b/qcom/ravelinp-sg-atp.dtsi new file mode 100644 index 00000000..ebb9b984 --- /dev/null +++ b/qcom/ravelinp-sg-atp.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-sg-atp.dtsi" diff --git a/qcom/ravelinp-sg-idp-wcn3950-amoled-rcm.dts b/qcom/ravelinp-sg-idp-wcn3950-amoled-rcm.dts new file mode 100644 index 00000000..8c27ce5f --- /dev/null +++ b/qcom/ravelinp-sg-idp-wcn3950-amoled-rcm.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelinp-sg.dtsi" +#include "ravelinp-sg-idp-wcn3950-amoled-rcm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. RavelinP SG WCN3950 IDP + AMOLED + RCM"; + compatible = "qcom,ravelinp-idp", "qcom,ravelinp", "qcom,idp"; + qcom,board-id = <34 2>; +}; diff --git a/qcom/ravelinp-sg-idp-wcn3950-amoled-rcm.dtsi b/qcom/ravelinp-sg-idp-wcn3950-amoled-rcm.dtsi new file mode 100644 index 00000000..dbc926c2 --- /dev/null +++ b/qcom/ravelinp-sg-idp-wcn3950-amoled-rcm.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-sg-idp-wcn3950-amoled-rcm.dtsi" + diff --git a/qcom/ravelinp-sg-idp-wcn3988-4gb.dts b/qcom/ravelinp-sg-idp-wcn3988-4gb.dts new file mode 100644 index 00000000..26e344ca --- /dev/null +++ b/qcom/ravelinp-sg-idp-wcn3988-4gb.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelinp-4gb.dtsi" +#include "ravelinp-sg-idp-wcn3988-4gb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. RavelinP SG IDP 4GB DDR + WCN3988"; + compatible = "qcom,ravelinp-idp", "qcom,ravelinp", "qcom,idp"; + qcom,board-id = <34 0x601>; +}; diff --git a/qcom/ravelinp-sg-idp-wcn3988-4gb.dtsi b/qcom/ravelinp-sg-idp-wcn3988-4gb.dtsi new file mode 100644 index 00000000..c4d7b514 --- /dev/null +++ b/qcom/ravelinp-sg-idp-wcn3988-4gb.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-sg-idp-wcn3988-4gb.dtsi" diff --git a/qcom/ravelinp-sg-idp.dts b/qcom/ravelinp-sg-idp.dts new file mode 100644 index 00000000..33902723 --- /dev/null +++ b/qcom/ravelinp-sg-idp.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelinp-sg.dtsi" +#include "ravelinp-sg-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. RavelinP SG IDP"; + compatible = "qcom,ravelinp-idp", "qcom,ravelinp", "qcom,idp"; + qcom,board-id = <34 0>; +}; + diff --git a/qcom/ravelinp-sg-idp.dtsi b/qcom/ravelinp-sg-idp.dtsi new file mode 100644 index 00000000..d1626b92 --- /dev/null +++ b/qcom/ravelinp-sg-idp.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-sg-idp.dtsi" diff --git a/qcom/ravelinp-sg-qrd-4gb.dts b/qcom/ravelinp-sg-qrd-4gb.dts new file mode 100644 index 00000000..02ed7743 --- /dev/null +++ b/qcom/ravelinp-sg-qrd-4gb.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelinp-4gb.dtsi" +#include "ravelinp-sg-qrd-4gb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. RavelinP SG QRD 4GB DDR"; + compatible = "qcom,ravelinp-qrd", "qcom,ravelinp", "qcom,qrd"; + qcom,board-id = <0x1000B 0x600>; +}; + diff --git a/qcom/ravelinp-sg-qrd-4gb.dtsi b/qcom/ravelinp-sg-qrd-4gb.dtsi new file mode 100644 index 00000000..0245ec57 --- /dev/null +++ b/qcom/ravelinp-sg-qrd-4gb.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-sg-qrd-4gb.dtsi" + diff --git a/qcom/ravelinp-sg-qrd.dts b/qcom/ravelinp-sg-qrd.dts new file mode 100644 index 00000000..fb97f8b3 --- /dev/null +++ b/qcom/ravelinp-sg-qrd.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelinp-sg.dtsi" +#include "ravelinp-sg-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. RavelinP SG QRD"; + compatible = "qcom,ravelinp-qrd", "qcom,ravelinp", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; +}; + + diff --git a/qcom/ravelinp-sg-qrd.dtsi b/qcom/ravelinp-sg-qrd.dtsi new file mode 100644 index 00000000..e7fa0492 --- /dev/null +++ b/qcom/ravelinp-sg-qrd.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-sg-qrd.dtsi" diff --git a/qcom/ravelinp-sg.dts b/qcom/ravelinp-sg.dts new file mode 100644 index 00000000..3ee5eceb --- /dev/null +++ b/qcom/ravelinp-sg.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelinp-sg.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. RavelinP SG SoC"; + compatible = "qcom,ravelinp"; + qcom,board-id = <0 0>; +}; + diff --git a/qcom/ravelinp-sg.dtsi b/qcom/ravelinp-sg.dtsi new file mode 100644 index 00000000..66a40c4c --- /dev/null +++ b/qcom/ravelinp-sg.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-sg.dtsi" + +/ { + + model = "Qualcomm Technologies, Inc. RavelinP SG"; + compatible = "qcom,ravelinp"; + qcom,msm-id = <654 0x10000>; +}; From 06fcb8934553b4cfeb272cfbcd28e1df4a578f96 Mon Sep 17 00:00:00 2001 From: Shashikala Katthi Date: Tue, 16 Jul 2024 19:50:00 +0530 Subject: [PATCH 19/54] ARM: dts: msm: Add qrng device node Add qrng device node support for ravelin. Change-Id: Ia256ae34538bb755fe6ced0d5b01ef465bd04664 Signed-off-by: Shashikala Katthi --- qcom/ravelin.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qcom/ravelin.dtsi b/qcom/ravelin.dtsi index 813f3c80..1f6b8192 100644 --- a/qcom/ravelin.dtsi +++ b/qcom/ravelin.dtsi @@ -1291,6 +1291,13 @@ }; }; + qcom_rng: qrng@10c3000 { + compatible = "qcom,msm-rng"; + reg = <0x10c3000 0x1000>; + qcom,no-qrng-config; + qcom,no-clock-support; + }; + ufsphy_mem: ufsphy_mem@1d87000 { reg = <0x1d87000 0xe10>; reg-names = "phy_mem"; From 857c487ffa8a402f6810f8a04e3bad4a258143a0 Mon Sep 17 00:00:00 2001 From: Xiaoqi Zhuang Date: Tue, 16 Jul 2024 10:35:01 +0800 Subject: [PATCH 20/54] ARM: dts: msm: Modify dump_mem dts node property to adapt kernel-6.6 on monaco For static-mem-dump, it's required to include in a child node. Change-Id: Ic625878142c4a0c17bc6d2084d794f8d593b6fa8 Signed-off-by: Xiaoqi Zhuang --- qcom/monaco.dtsi | 163 ++++++++++++++++++++++++----------------------- 1 file changed, 84 insertions(+), 79 deletions(-) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 63f5bec8..fc676346 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -719,105 +719,110 @@ mem_dump { compatible = "qcom,mem-dump"; + memory-region = <&dump_mem>; - c0_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x0>; - }; + static_dump { + qcom,static-mem-dump; - c1_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x1>; - }; + c0_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x0>; + }; - c2_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x2>; - }; + c1_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x1>; + }; - c3_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x3>; - }; + c2_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x2>; + }; - l1_icache0 { - qcom,dump-size = <0x9040>; - qcom,dump-id = <0x60>; - }; + c3_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x3>; + }; - l1_icache1 { - qcom,dump-size = <0x9040>; - qcom,dump-id = <0x61>; - }; + l1_icache0 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x60>; + }; - l1_icache2 { - qcom,dump-size = <0x9040>; - qcom,dump-id = <0x62>; - }; + l1_icache1 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x61>; + }; - l1_icache3 { - qcom,dump-size = <0x9040>; - qcom,dump-id = <0x63>; - }; + l1_icache2 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x62>; + }; - l1_dcache0 { - qcom,dump-size = <0x9040>; - qcom,dump-id = <0x80>; - }; + l1_icache3 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x63>; + }; - l1_dcache1 { - qcom,dump-size = <0x9040>; - qcom,dump-id = <0x81>; - }; + l1_dcache0 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x80>; + }; - l1_dcache2 { - qcom,dump-size = <0x9040>; - qcom,dump-id = <0x82>; - }; + l1_dcache1 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x81>; + }; - l1_dcache3 { - qcom,dump-size = <0x9040>; - qcom,dump-id = <0x83>; - }; + l1_dcache2 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x82>; + }; - l2_tlb0 { - qcom,dump-size = <0x2000>; - qcom,dump-id = <0x120>; - }; + l1_dcache3 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x83>; + }; - l2_tlb1 { - qcom,dump-size = <0x2000>; - qcom,dump-id = <0x121>; - }; + l2_tlb0 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x120>; + }; - l2_tlb2 { - qcom,dump-size = <0x2000>; - qcom,dump-id = <0x122>; - }; + l2_tlb1 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x121>; + }; - l2_tlb3 { - qcom,dump-size = <0x2000>; - qcom,dump-id = <0x123>; - }; + l2_tlb2 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x122>; + }; - pmic { - qcom,dump-size = <0x200000>; - qcom,dump-id = <0xe4>; - }; + l2_tlb3 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x123>; + }; - tmc_etf { - qcom,dump-size = <0x8000>; - qcom,dump-id = <0xf0>; - }; + pmic { + qcom,dump-size = <0x200000>; + qcom,dump-id = <0xe4>; + }; - etr_reg { - qcom,dump-size = <0x1000>; - qcom,dump-id = <0x100>; - }; + tmc_etf { + qcom,dump-size = <0x8000>; + qcom,dump-id = <0xf0>; + }; - etf_reg { - qcom,dump-size = <0x1000>; - qcom,dump-id = <0x101>; + etr_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x100>; + }; + + etf_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x101>; + }; }; }; From b4682c47fb28821a6e8c945f13670aa5b85d33a2 Mon Sep 17 00:00:00 2001 From: Xiaoqi Zhuang Date: Wed, 17 Jul 2024 10:21:52 +0800 Subject: [PATCH 21/54] ARM: dts: msm: Modify dump_mem dts node property to adapt kernel-6.6 on monaco Remove DMA property for Reserved memory via memremap instead of DMA API. Change-Id: I2c717dc3766df7df22f6750941da0e0d03824920 Signed-off-by: Xiaoqi Zhuang --- qcom/monaco.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index fc676346..c1795622 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -274,9 +274,7 @@ }; dump_mem: mem_dump_region { - compatible = "shared-dma-pool"; alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; size = <0 0x800000>; }; From 6d44454ad1c16612912c65bb95948a0feb838378 Mon Sep 17 00:00:00 2001 From: Shilpa Suresh Date: Tue, 16 Jul 2024 13:08:01 +0530 Subject: [PATCH 22/54] ARM: dts: msm: Enable PM8010 nodes for Ravelin Compatible strings for the PM8008 chip and PM8010 regulator nodes were removed during the bulk DT porting for Ravelin on qcom-6.6 device-tree branch 'commit 1b78f8027a4fe ("ARM: dts: msm: Add initial device tree for ravelin")'. Add them back to enable the PM8010 regulator support. While at it, remove the PM8010's REVID device node references as they are not required for Ravelin. Change-Id: Iec11cd246f86e35d0330103143182c6aee94959e Signed-off-by: Shilpa Suresh --- qcom/ravelin-pmic-overlay.dtsi | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/qcom/ravelin-pmic-overlay.dtsi b/qcom/ravelin-pmic-overlay.dtsi index d6bc3028..d1e9e838 100644 --- a/qcom/ravelin-pmic-overlay.dtsi +++ b/qcom/ravelin-pmic-overlay.dtsi @@ -483,16 +483,13 @@ pinctrl-0 = <&pm8010m_active>; pm8010-chip@900 { + compatible = "qcom,pm8008-chip"; reg = <0x900>; PM8010M_EN: qcom,pm8008-chip-en { regulator-name = "pm8010m-chip-en"; }; }; - - qcom,revid@100 { - reg = <0x100>; - }; }; pm8010m@9 { @@ -502,6 +499,7 @@ #size-cells = <0>; qcom,pm8010m-regulator { + compatible = "qcom,pm8010-regulator"; #address-cells = <1>; #size-cells = <0>; @@ -570,16 +568,13 @@ pinctrl-0 = <&pm8010n_active>; pm8010-chip@900 { + compatible = "qcom,pm8008-chip"; reg = <0x900>; PM8010N_EN: qcom,pm8008-chip-en { regulator-name = "pm8010n-chip-en"; }; }; - - qcom,revid@100 { - reg = <0x100>; - }; }; pm8010n@d { @@ -589,6 +584,7 @@ #size-cells = <0>; qcom,pm8010n-regulator { + compatible = "qcom,pm8010-regulator"; #address-cells = <1>; #size-cells = <0>; From 8bc7268ce0f9d6c514267177ae603b4210472883 Mon Sep 17 00:00:00 2001 From: Bibek Kumar Patro Date: Thu, 4 Jul 2024 18:22:46 +0530 Subject: [PATCH 23/54] ARM: dts: msm: add initial memory configuration for sdxkova Add initial memory configuration and reserved memory map for sdxkova, inline with v1. Change-Id: I3748f7264d39b579c6cabfb5ae0ec7dbf9da3ef0 Signed-off-by: Bibek Kumar Patro --- qcom/sdxkova-idp-cpe.dts | 1 + qcom/sdxkova-idp-mbb.dts | 1 + qcom/sdxkova-reserved-memory.dtsi | 141 ++++++++++++++++++++++++++++++ qcom/sdxkova.dtsi | 18 ++++ 4 files changed, 161 insertions(+) create mode 100644 qcom/sdxkova-reserved-memory.dtsi diff --git a/qcom/sdxkova-idp-cpe.dts b/qcom/sdxkova-idp-cpe.dts index 079b3ec8..a2d3e8c1 100644 --- a/qcom/sdxkova-idp-cpe.dts +++ b/qcom/sdxkova-idp-cpe.dts @@ -7,6 +7,7 @@ #include "sdxkova.dtsi" #include "sdxkova-idp-cpe.dtsi" +#include "sdxkova-reserved-memory.dtsi" / { model = "Qualcomm Technologies, Inc. SDXKOVA IDP CPE"; diff --git a/qcom/sdxkova-idp-mbb.dts b/qcom/sdxkova-idp-mbb.dts index bbe2a28e..18dfa58e 100644 --- a/qcom/sdxkova-idp-mbb.dts +++ b/qcom/sdxkova-idp-mbb.dts @@ -7,6 +7,7 @@ #include "sdxkova.dtsi" #include "sdxkova-idp-mbb.dtsi" +#include "sdxkova-reserved-memory.dtsi" / { model = "Qualcomm Technologies, Inc. SDXKOVA IDP MBB"; diff --git a/qcom/sdxkova-reserved-memory.dtsi b/qcom/sdxkova-reserved-memory.dtsi new file mode 100644 index 00000000..0a6f7f3f --- /dev/null +++ b/qcom/sdxkova-reserved-memory.dtsi @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gunyah_hyp_mem: gunyah_hyp_region@80000000 { + no-map; + reg = <0x0 0x80000000 0x0 0x800000>; + }; + + /* HYP elf package region at 0x80800000 to be shared with Linux */ + + access_control_db_mem: access_control_db_region@81380000 { + no-map; + reg = <0x0 0x81380000 0x0 0x80000>; + }; + + qteetz_mem: qteetz_region@814e0000 { + no-map; + reg = <0x0 0x814e0000 0x0 0x2a0000>; + }; + + trusted_apps_mem: trusted_apps_region@81780000 { + no-map; + reg = <0x0 0x81780000 0x0 0xa00000>; + }; + + /* UEFI region at 0x87100000 is reclaimed by Linux */ + + /* UEFI region at 0x87500000 is reclaimed by Linux */ + + /* ABL region at 0x87900000 is reclaimed by Linux */ + + /* XBL RAMdump at 0x87a00000 to be reused Linux */ + + cpucp_fw_mem: cpucp_fw_region@87c00000 { + no-map; + reg = <0x0 0x87c00000 0x0 0x100000>; + }; + + xbl_dtlog_mem: xbl_dtlog_region@87d00000 { + no-map; + reg = <0x0 0x87d00000 0x0 0x40000>; + }; + + xbl_sc_mem: xbl_sc_region@87d40000 { + no-map; + reg = <0x0 0x87d40000 0x0 0x40000>; + }; + + modem_efs_shared_mem: modem_efs_shared_region@87d80000 { + no-map; + reg = <0x0 0x87d80000 0x0 0x10000>; + }; + + aop_image_mem: aop_image_region@87e00000 { + no-map; + reg = <0x0 0x87e00000 0x0 0x20000>; + }; + + smem_mem: smem_region@87e20000 { + no-map; + reg = <0x0 0x87e20000 0x0 0xc0000>; + }; + + aop_cmd_db_mem: aop_cmd_db_region@87ee0000 { + compatible = "qcom,cmd-db"; + no-map; + reg = <0x0 0x87ee0000 0x0 0x20000>; + }; + + aop_config_mem: aop_config_region@87f00000 { + no-map; + reg = <0x0 0x87f00000 0x0 0x20000>; + }; + + ipa_fw_mem: ipa_fw_region@87f20000 { + no-map; + reg = <0x0 0x87f20000 0x0 0x10000>; + }; + + secdata_mem: secdata_region@87f30000 { + no-map; + reg = <0x0 0x87f30000 0x0 0x1000>; + }; + + tme_crashdump_mem: tme_crashdump_region@87f31000 { + no-map; + reg = <0x0 0x87f31000 0x0 0x40000>; + }; + + tme_log_mem: tme_log_region@87f71000 { + no-map; + reg = <0x0 0x87f71000 0x0 0x4000>; + }; + + /* UEFI region at 0x87f75000 is reclaimed by Linux */ + + qdss_mem: qdss_region@88500000 { + no-map; + reg = <0x0 0x88500000 0x0 0x300000>; + }; + + qlink_logging_mem: qlink_logging_region@88800000 { + no-map; + reg = <0x0 0x88800000 0x0 0x300000>; + }; + + audio_heap_mem: audio_heap_region@88b00000 { + no-map; + reg = <0x0 0x88b00000 0x0 0x400000>; + }; + + dsm_partition_2_mem: dsm_partition_2_region@88f00000 { + no-map; + reg = <0x0 0x88f00000 0x0 0x2500000>; + }; + + dsm_partition_1_mem: dsm_partition_1_region@8b400000 { + no-map; + reg = <0x0 0x8b400000 0x0 0x2b80000>; + }; + + q6_mpss_dtb_mem: q6_mpss_dtb_region@8df80000 { + no-map; + reg = <0x0 0x8df80000 0x0 0x80000>; + }; + + mpssadsp_mem: mpssadsp_region@8e000000 { + no-map; + reg = <0x0 0x8e000000 0x0 0xf100000>; + }; + + /* Linux kernel image is loaded at 0xa8000000 */ + +}; diff --git a/qcom/sdxkova.dtsi b/qcom/sdxkova.dtsi index a4a57891..d58fb7b8 100644 --- a/qcom/sdxkova.dtsi +++ b/qcom/sdxkova.dtsi @@ -13,4 +13,22 @@ hyplog-address-offset = <0x410>; hyplog-size-offset = <0x414>; }; + +/delete-node/ reserved-memory; + +reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + system_cma: linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2000000>; + linux,cma-default; + }; +}; + }; From aede871268998ef0b716a3fc5078362bed2b9a7a Mon Sep 17 00:00:00 2001 From: Bibek Kumar Patro Date: Fri, 5 Jul 2024 11:45:10 +0530 Subject: [PATCH 24/54] ARM: dts: msm: Add initial SMMU configuration for sdxkova Add initial apps SMMU configuration for sdxkova. Change-Id: I2084cdd5a84b94d1f3eb98bca2ef31fdf792769d Signed-off-by: Bibek Kumar Patro --- qcom/msm-arm-smmu-sdxkova.dtsi | 117 +++++++++++++++++++++++++++++++++ qcom/sdxkova.dtsi | 3 +- 2 files changed, 119 insertions(+), 1 deletion(-) create mode 100644 qcom/msm-arm-smmu-sdxkova.dtsi diff --git a/qcom/msm-arm-smmu-sdxkova.dtsi b/qcom/msm-arm-smmu-sdxkova.dtsi new file mode 100644 index 00000000..66732ae4 --- /dev/null +++ b/qcom/msm-arm-smmu-sdxkova.dtsi @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + apps_smmu: apps-smmu@15000000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15000000 0x40000>; + #iommu-cells = <2>; + qcom,use-3-lvl-tables; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + dma-coherent; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + anoc_1_qtb: anoc_1_qtb@1680000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x1680000 0x1000>; + qcom,stream-id-range = <0x0 0x400>; + qcom,iova-width = <36>; + qcom,num-qtb-ports = <1>; + }; + + ipa_qtb: ipa_qtb@1688000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x1688000 0x1000>; + qcom,stream-id-range = <0x400 0x400>; + qcom,iova-width = <41>; + qcom,num-qtb-ports = <1>; + }; + + pcie_qtb: pcie_qtb@16d0000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x16d0000 0x1000>; + qcom,stream-id-range = <0x800 0x400>; + qcom,iova-width = <36>; + qcom,num-qtb-ports = <1>; + qcom,opt-out-tbu-halting; + }; + }; + + dma_dev { + compatible = "qcom,iommu-dma"; + memory-region = <&system_cma>; + }; + + iommu_test_device { + compatible = "qcom,iommu-debug-test"; + + usecase0_apps { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x3e0 0x0>; + }; + + usecase1_apps_fastmap { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x3e0 0x0>; + qcom,iommu-dma = "fastmap"; + }; + + usecase2_apps_atomic { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x3e0 0x0>; + qcom,iommu-dma = "atomic"; + }; + + usecase3_apps_dma { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x3e0 0x0>; + dma-coherent; + }; + + usecase4_apps_secure { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x3e0 0x0>; + qcom,iommu-vmid = <0x2d>; /* VMID_TUIVM */ + }; + }; +}; diff --git a/qcom/sdxkova.dtsi b/qcom/sdxkova.dtsi index d58fb7b8..749406b2 100644 --- a/qcom/sdxkova.dtsi +++ b/qcom/sdxkova.dtsi @@ -4,7 +4,8 @@ */ #include "sdx75.dtsi" - +/delete-node/ &apps_smmu; +#include "msm-arm-smmu-sdxkova.dtsi" / { qcom_tzlog: tz-log@14680720 { compatible = "qcom,tz-log"; From d129b2add35938024e2891360962fc0ce837fe9f Mon Sep 17 00:00:00 2001 From: Ayyagari Ushasreevalli Date: Thu, 30 May 2024 13:07:03 +0530 Subject: [PATCH 25/54] ARM: dts: msm: Uncomment compatible string for PMIC drivers Uncomment compatible string qcom,qpnp-power-on, qcom, qpnp-pm5100-smblite, qcom,pm5100-gpio, qcom,pm5100-rtc from pm5100.dtsi. Change-Id: I62379df9f18d40fc540a7f1512e84e60f7a51a23 Signed-off-by: Ayyagari Ushasreevalli --- qcom/pm5100.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/qcom/pm5100.dtsi b/qcom/pm5100.dtsi index 3d303c4c..d492a3c1 100644 --- a/qcom/pm5100.dtsi +++ b/qcom/pm5100.dtsi @@ -24,7 +24,7 @@ #size-cells = <0>; pon_hlos@1300 { - /* compatible = "qcom,qpnp-power-on"; */ + compatible = "qcom,qpnp-power-on"; reg = <0x1300>; interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>, <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>; @@ -42,7 +42,7 @@ }; pm5100_charger: qcom,qpnp-smblite { - /* compatible = "qcom,qpnp-pm5100-smblite"; */ + compatible = "qcom,qpnp-pm5100-smblite"; #address-cells = <1>; #size-cells = <1>; #cooling-cells = <2>; @@ -240,7 +240,7 @@ }; pm5100_gpios: pinctrl@8800 { - /* compatible = "qcom,pm5100-gpio"; */ + compatible = "qcom,pm5100-gpio"; reg = <0x8800>; gpio-controller; #gpio-cells = <2>; @@ -249,7 +249,7 @@ }; pm5100_rtc: rtc@6400 { - /* compatible = "qcom,pm5100-rtc"; */ + compatible = "qcom,pm5100-rtc"; reg = <0x6400>, <0x6500>; reg-names = "rtc", "alarm"; interrupts = <0x0 0x65 0x1 IRQ_TYPE_EDGE_RISING>; @@ -344,7 +344,7 @@ pm5100_qbg: qpnp,qbg@4f00 { status = "disabled"; - /* compatible = "qcom,qbg"; */ + compatible = "qcom,qbg"; #address-cells = <1>; reg = <0x4f00>; interrupt-names = "qbg-sdam", "qbg-vbatt-empty"; From 92235674d7b1c573f3c6ab0a208afd7de53748cc Mon Sep 17 00:00:00 2001 From: Shashikala Katthi Date: Tue, 16 Jul 2024 20:20:11 +0530 Subject: [PATCH 26/54] ARM: dts: msm: Add qseecom compatible Add dt support for qseecom for ravelin. Change-Id: I77d42910dd1a7276e2ac870926c8e54542a84157 Signed-off-by: Shashikala Katthi --- qcom/ravelin.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/ravelin.dtsi b/qcom/ravelin.dtsi index 1f6b8192..2977e380 100644 --- a/qcom/ravelin.dtsi +++ b/qcom/ravelin.dtsi @@ -826,6 +826,7 @@ }; qcom_qseecom: qseecom@c1700000 { + compatible = "qcom,qseecom"; memory-region = <&qseecom_mem>; qseecom_mem = <&qseecom_mem>; qseecom_ta_mem = <&qseecom_ta_mem>; From dea51fc5d28f468db0c9424465be9408d6a1c0b0 Mon Sep 17 00:00:00 2001 From: Patrick Daly Date: Fri, 17 May 2024 18:24:20 -0700 Subject: [PATCH 27/54] ARM: dts: msm: save 2M vmemmap of memory on sun There is 512K of DDR in a section memory and the rest is carveout in a memory region [0x98000000 a0000000). As section size is 128M, which require 2M of memmap. Lose this 512K to save (2M - 512K) of memory. CRs-Fixed: 3792207 Change-Id: I5fa1f7a366eefd464e67099ff1835dc84423d18b Signed-off-by: Patrick Daly --- qcom/sun.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index 73bc4e24..e9ee7136 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -3804,6 +3804,11 @@ reg = <0x0 0x9eb00000 0x0 0x80000>; }; + lost_reg_mem2 { + no-map; + reg = <0x0 0x9eb80000 0x0 0x80000>; + }; + soccp_mem: soccp_region@9ec00000 { no-map; reg = <0x0 0x9ec00000 0x0 0x180000>; From eca997e3cb1e8267af3afde39b6a95e3445e29fe Mon Sep 17 00:00:00 2001 From: Srinivasarao Pathipati Date: Thu, 18 Jul 2024 16:48:22 +0530 Subject: [PATCH 28/54] ARM: dts: msm: disable movable zone for parrot and ravelin Pages are getting allocated from Movable zone even though they are requested from Normal zone. Disable movable zone as work around until issue is fixed. Change-Id: Ib2f799ec36ef969368410fe8e86f92441ad0b81b Signed-off-by: Srinivasarao Pathipati --- qcom/parrot.dtsi | 1 + qcom/ravelin.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/qcom/parrot.dtsi b/qcom/parrot.dtsi index 3235f238..6dfba538 100644 --- a/qcom/parrot.dtsi +++ b/qcom/parrot.dtsi @@ -45,6 +45,7 @@ <0x2 0xc0000000 0x1 0x40000000>; granule = <512>; mboxes = <&qmp_aop 0>; + status = "disabled"; }; aliases: aliases { diff --git a/qcom/ravelin.dtsi b/qcom/ravelin.dtsi index 56692c6b..79d15f95 100644 --- a/qcom/ravelin.dtsi +++ b/qcom/ravelin.dtsi @@ -44,6 +44,7 @@ <0x2 0xc0000000 0x1 0x40000000>; granule = <512>; mboxes = <&qmp_aop 0>; + status = "disabled"; }; aliases: aliases { From c810232086bbffbe77be0064b6ba5afd2cd6abbc Mon Sep 17 00:00:00 2001 From: Shashikala Katthi Date: Fri, 19 Jul 2024 15:18:53 +0530 Subject: [PATCH 29/54] ARM: dts: msm: add ufs wrapped key support to ravelin Add support for ice wrapped keys to the UFS DTSI entry to ravelin. Change-Id: Ica90929da90464c64bb4b23c9a8236fa7149ed1e Signed-off-by: Shashikala Katthi --- qcom/ravelin.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/qcom/ravelin.dtsi b/qcom/ravelin.dtsi index 8c53406a..0f227aa6 100644 --- a/qcom/ravelin.dtsi +++ b/qcom/ravelin.dtsi @@ -1335,14 +1335,14 @@ ufshc_mem: ufshc@1d84000 { compatible = "qcom,ufshc"; reg = <0x1d84000 0x3000>, - <0x1d88000 0x8000>, - <0x1d90000 0x9000>; - reg-names = "ufs_mem", "ufs_ice", "ufs_ice_hwkm"; + <0x1d88000 0x18000>; + reg-names = "ufs_mem", "ice"; interrupts = ; phys = <&ufsphy_mem>; phy-names = "ufsphy"; #reset-cells = <1>; + qcom,ice-use-hwkm; lanes-per-direction = <2>; dev-ref-clk-freq = <0>; /* 19.2 MHz */ clock-names = From c8ce3e1b00bf36fd8fba70d812ca505b1822fa9a Mon Sep 17 00:00:00 2001 From: Akshay Gola Date: Fri, 19 Jul 2024 17:36:06 +0530 Subject: [PATCH 30/54] ARM: dts: msm: Enable the SPMI node and add node its documentation Enable SPMI node and add its documentation for bring-up. Change-Id: I6ddfb75c6ba03935a5c8338f859147ea676205dd Signed-off-by: Akshay Gola --- bindings/sound/qcom,wcd_codec.yaml | 32 ++++++++++++++++++++++++++++++ qcom/pm5100.dtsi | 2 +- 2 files changed, 33 insertions(+), 1 deletion(-) create mode 100644 bindings/sound/qcom,wcd_codec.yaml diff --git a/bindings/sound/qcom,wcd_codec.yaml b/bindings/sound/qcom,wcd_codec.yaml new file mode 100644 index 00000000..e75c3bde --- /dev/null +++ b/bindings/sound/qcom,wcd_codec.yaml @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/qcom,wcd_codec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. WCD audio CODEC + +maintainers: + - Swapnil Kangralkar + +description: + This document defines the bindings for pm5100_spmi child node of SPMI bus + required for besbev codec in order to access SPMI register to reset the + peripheral. + +properties: + compatible: + const: qcom,pm5100-spmi + +required: + - compatible + +additionalProperties: false + +examples: + - | + &spmi_bus { + pm5100_cdc: qcom,pm5100-cdc { + compatible = "qcom,pm5100-spmi"; + }; + }; diff --git a/qcom/pm5100.dtsi b/qcom/pm5100.dtsi index 3d303c4c..d13b2960 100644 --- a/qcom/pm5100.dtsi +++ b/qcom/pm5100.dtsi @@ -256,7 +256,7 @@ }; pm5100_cdc: qcom,pm5100-cdc { - /* compatible = "qcom,pm5100-spmi"; */ + compatible = "qcom,pm5100-spmi"; }; pm5100_bcl: bcl@4700 { From 15556562b8afd8801121c48e8d4af82f56661119 Mon Sep 17 00:00:00 2001 From: Devender Kaushik Date: Tue, 23 Jul 2024 10:39:32 +0530 Subject: [PATCH 31/54] ARM: dts: msm: add remote debugger support Add remote debugger device configuration. The Remote Debugger driver allows a debugger running on a host PC to communicate with a remote stub running on peripheral subsystems. Change-Id: I6513c219a4d3a50f0c0723036bd7387da3558477 Signed-off-by: Devender Kaushik --- qcom/tuna.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index a69a186b..f9893d7d 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -983,6 +983,7 @@ #include "tuna-stub-regulators.dtsi" #include "tuna-usb.dtsi" #include "tuna-qupv3.dtsi" +#include "msm-rdbg.dtsi" &qupv3_se7_2uart { status = "ok"; From 8e39e7601fbf9533a2fa4ca75a01bad3df2d55f9 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Thu, 18 Jul 2024 21:14:19 +0530 Subject: [PATCH 32/54] ARM: dts: msm: Mention class cpus as cpu phandles for sun/pineapple Remove the hard coded class cpus and replace them with their phandles. Change-Id: I283ac79d64d945e12477f61a67b058574bde7031 Signed-off-by: Mukesh Ojha --- qcom/pineapple.dtsi | 4 ++-- qcom/sun.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/qcom/pineapple.dtsi b/qcom/pineapple.dtsi index 394325b8..de39ea3a 100644 --- a/qcom/pineapple.dtsi +++ b/qcom/pineapple.dtsi @@ -2389,9 +2389,9 @@ gic-interrupt-router { compatible = "qcom,gic-intr-routing"; /* keep silver core only to avoid wakeup of gold cores */ - qcom,gic-class0-cpus = <0 1>; + qcom,gic-class0-cpus = <&CPU0 &CPU1>; /* keep gold and gold+ cores in class1 */ - qcom,gic-class1-cpus = <2 3 4 5 6 7>; + qcom,gic-class1-cpus = <&CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7>; }; qcom,secure-buffer { diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index a32f4531..154e21cf 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -928,9 +928,9 @@ gic-interrupt-router { compatible = "qcom,gic-intr-routing"; /* keep a few m cores in class0 only to avoid wakeup of l cores */ - qcom,gic-class0-cpus = <0 1>; + qcom,gic-class0-cpus = <&CPU0 &CPU1>; /* keep other cores in class1 */ - qcom,gic-class1-cpus = <2 3 4 5 6 7>; + qcom,gic-class1-cpus = <&CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7>; }; qcom,secure-buffer { From 40aa1b3eb7added0d407a545bafb98a3642af290 Mon Sep 17 00:00:00 2001 From: Anaadi Mishra Date: Mon, 17 Jun 2024 16:05:43 +0530 Subject: [PATCH 33/54] dt-bindings: clock: qcom: add GCC and TCSRCC bindings on KERA Add GCC and TCSRCC clock bindings on kera platform. Change-Id: I29f71b82ea76855a068ce26682037ae6095255e5 Signed-off-by: Anaadi Mishra --- bindings/clock/qcom,gcc-sun.yaml | 1 + bindings/clock/qcom,tcsrcc.yaml | 1 + 2 files changed, 2 insertions(+) diff --git a/bindings/clock/qcom,gcc-sun.yaml b/bindings/clock/qcom,gcc-sun.yaml index 29ca3d1a..fa5755e4 100644 --- a/bindings/clock/qcom,gcc-sun.yaml +++ b/bindings/clock/qcom,gcc-sun.yaml @@ -22,6 +22,7 @@ properties: enum: - qcom,gcc-sun - qcom,tuna-gcc + - qcom,kera-gcc clocks: items: diff --git a/bindings/clock/qcom,tcsrcc.yaml b/bindings/clock/qcom,tcsrcc.yaml index 18ada41c..4e0ab14f 100644 --- a/bindings/clock/qcom,tcsrcc.yaml +++ b/bindings/clock/qcom,tcsrcc.yaml @@ -22,6 +22,7 @@ properties: - qcom,pineapple-tcsrcc - qcom,sun-tcsrcc - qcom,tuna-tcsrcc + - qcom,kera-tcsrcc required: - compatible From c831e5e8c53f8a6e555a593de336cd39e0b47fc4 Mon Sep 17 00:00:00 2001 From: Amir Vajid Date: Tue, 12 Dec 2023 12:52:50 -0800 Subject: [PATCH 34/54] dt-bindings: soc: qcom: Add non-early mapping to bwmon bindings Update bwmon bindings to include support for non-early memory mapping. Change-Id: I4f45ea0fd3f219325463d832c958ebd900f15f1c Signed-off-by: Amir Vajid Signed-off-by: Shivnandan Kumar --- bindings/soc/qcom/qcom,bwmon.yaml | 33 +++++++++++++++++++++++++------ 1 file changed, 27 insertions(+), 6 deletions(-) diff --git a/bindings/soc/qcom/qcom,bwmon.yaml b/bindings/soc/qcom/qcom,bwmon.yaml index 4bfac87b..ccfbcf48 100644 --- a/bindings/soc/qcom/qcom,bwmon.yaml +++ b/bindings/soc/qcom/qcom,bwmon.yaml @@ -8,7 +8,7 @@ title: Qualcomm Technologies, Inc. (QTI) BWMON Driver maintainers: - avajid@quicinc.com - - gurbaror@quicinc.com + - Shivnandan Kumar description: | The Qualcomm Technologies, Inc. BWMON Driver monitors bandwidth counters that @@ -31,8 +31,15 @@ properties: maxItems: 2 reg-names: - - const: base - - const: global_base + items: + - const: base + - const: global_base + + "#address-cells": + enum: [1, 2] + + "#size-cells": + enum: [1, 2] interrupts: description: Lists the threshold IRQ. @@ -49,7 +56,6 @@ properties: node will be using for voting in the SLOW path. qcom,hw-timer-hz: - $ref: /schemas/types.yaml#/definitions/uint32 description: Hardware sampling rate in Hz. This field must be specified for "qcom,bwmon4" @@ -69,19 +75,34 @@ properties: description: Number of bytes monitor counts in + qcom,map-ne: + type: boolean + description: | + Specify if the bwmon memory region should be mapped as nE (non-Early). + required: - compatible - reg - reg-names - interrupts - - qcom,target-dev + - qcom,mport - qcom,hw-timer-hz + - qcom,count-unit + - qcom,target-dev + - '#address-cells' + - '#size-cells' + +additionalProperties: true examples: - | + #include bwmon_llcc: qcom,bwmon-llcc@90b6400 { compatible = "qcom,bwmon4"; - reg = <0x90b6400 0x300>, <0x90b6300 0x200>; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x90b6400 0x300>, + <0x90b6300 0x200>; reg-names = "base", "global_base"; interrupts = ; qcom,mport = <0>; From aeb4dbdd4c6febaa2f47ff0182f60a949806af1d Mon Sep 17 00:00:00 2001 From: Patrick Daly Date: Thu, 8 Feb 2024 16:50:37 -0800 Subject: [PATCH 35/54] ARM: dts: msm: Enable memmap_on_memory on arm64 on sun-vm Memmap_on_memory changes the behaviour of memory hotplug to reserve the first X Mb of a memory block for the struct page array. On arm64, the size of the struct page array for a 128Mb memory block is 2Mb. However, the memory-hotplug code requires X to be pageblock aligned (4Mb). memory_hotplug.memmap_on_memory="force" informs the memory-hotplug core to round up the size of the memory reserved for struct page array to meet this 4Mb requirement, even though only 2Mb will actually be used. This is preferred over allocating the struct page array from ZONE_NORMAL because adding additional memory into ZONE_NORMAL is not supported on this target. Change-Id: I9544b58c202cecddbe80be67a24a1115b162e478 Signed-off-by: Patrick Daly --- qcom/sun-oemvm.dtsi | 2 +- qcom/sun-vm.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/sun-oemvm.dtsi b/qcom/sun-oemvm.dtsi index 1750a749..cb13d1e8 100644 --- a/qcom/sun-oemvm.dtsi +++ b/qcom/sun-oemvm.dtsi @@ -12,7 +12,7 @@ interrupt-parent = <&vgic>; chosen { - bootargs = "nokaslr log_buf_len=256K console=hvc0 loglevel=8 swiotlb=noforce"; + bootargs = "nokaslr log_buf_len=256K console=hvc0 loglevel=8 swiotlb=noforce memhp_default_state=online_movable memory_hotplug.memmap_on_memory=force"; }; cpus { diff --git a/qcom/sun-vm.dtsi b/qcom/sun-vm.dtsi index 03b0aa0a..32240b3c 100644 --- a/qcom/sun-vm.dtsi +++ b/qcom/sun-vm.dtsi @@ -15,7 +15,7 @@ interrupt-parent = <&vgic>; chosen { - bootargs = "nokaslr log_buf_len=256K console=hvc0 loglevel=8 swiotlb=noforce memhp_default_state=online_movable"; + bootargs = "nokaslr log_buf_len=256K console=hvc0 loglevel=8 swiotlb=noforce memhp_default_state=online_movable memory_hotplug.memmap_on_memory=force"; }; cpus { From 0289936a74e1f6e70213ae3b8ebe09e79530f799 Mon Sep 17 00:00:00 2001 From: Lingutla Chandrasekhar Date: Tue, 23 Jul 2024 16:03:11 -0700 Subject: [PATCH 36/54] dt-bindings: soc: add qcom,cpucp_fast documentation Add documentation for the device qcom,cpucp_fast, which is used for handling system hints from firmware. Change-Id: I2336051df317d09d5224244e2d8248242980cc18 Signed-off-by: Lingutla Chandrasekhar --- bindings/soc/qcom/qcom,cpucp_fast.yaml | 43 ++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 bindings/soc/qcom/qcom,cpucp_fast.yaml diff --git a/bindings/soc/qcom/qcom,cpucp_fast.yaml b/bindings/soc/qcom/qcom,cpucp_fast.yaml new file mode 100644 index 00000000..7269c4cc --- /dev/null +++ b/bindings/soc/qcom/qcom,cpucp_fast.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,cpucp_fast.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. CPUCP FAST driver + +maintainers: + - Chandrasekhar Lingutla + +description: | + This device listens interrupts from CPUCP via mailbox and + sends notification to scheduler. + +properties: + compatible: + const: qcom,cpucp_fast + + mboxes: + description: Mailboxes used for Interrupt from CPUCP + + qcom,policy-cpus: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Base CPU index for cpufreq policy + +required: + - compatible + - mboxes + - qcom,policy-cpus + +additionalProperties: false + +examples: + - | + soc { + cpucp_fast: qcom,cpucp_fast { + compatible = "qcom,cpucp_fast"; + mboxes = <&cpucp 5>; + qcom,policy-cpus = <6>; + }; + }; +... From 6d5d8319b0f87f272a469d869c4a76e3cc04d92b Mon Sep 17 00:00:00 2001 From: Lingutla Chandrasekhar Date: Tue, 19 Mar 2024 14:54:22 -0700 Subject: [PATCH 37/54] ARM: dts: msm: Add fast entry in sun Add CPUCP fast device tree entry to get mailbox channel id and cpus to be controlled with fast. Change-Id: Ibfc2db806adf97985bf3921fac1244032749d61a Signed-off-by: Lingutla Chandrasekhar --- qcom/sun.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index a32f4531..9d2d7217 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -3183,6 +3183,12 @@ }; }; + cpucp_fast: qcom,cpucp_fast { + compatible = "qcom,cpucp_fast"; + mboxes = <&cpucp 7>; + qcom,policy-cpus = < 6 >; + }; + cpucp_log: qcom,cpucp_log@0x81210000 { compatible = "qcom,cpucp-log"; reg = <0x81210000 0x10000>, From c349cbd5633d115fa941f678e8d65a6e27894d00 Mon Sep 17 00:00:00 2001 From: Ajit Pandey Date: Fri, 12 Jul 2024 15:55:57 +0530 Subject: [PATCH 38/54] dt-bindings: clock: qcom: add CAMCC and CAMBISTMCLKCC bindings on tuna Add camera and cambistmclk clock controller bindings on tuna device. While at it, fix existing yaml documentation for dtbs failure. Change-Id: I8484292fe7336f1bdd4d018e1a342da04148efd1 Signed-off-by: Ajit Pandey --- bindings/clock/qcom,cambistmclkcc.yaml | 5 +++-- bindings/clock/qcom,camcc-sun.yaml | 7 +++++-- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/bindings/clock/qcom,cambistmclkcc.yaml b/bindings/clock/qcom,cambistmclkcc.yaml index 41eedd80..1d178d46 100644 --- a/bindings/clock/qcom,cambistmclkcc.yaml +++ b/bindings/clock/qcom,cambistmclkcc.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/qcom,cambistmclkcc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Technologies, Inc. Camera BIST MCLK CC Controller Binding +title: Qualcomm Technologies, Inc. Camera BIST MCLK CC Controller maintainers: - Xubin Bai @@ -18,7 +18,8 @@ description: | properties: compatible: enum: - - qcom,cambistmclkcc-sun + - qcom,sun-cambistmclkcc + - qcom,tuna-cambistmclkcc clocks: items: diff --git a/bindings/clock/qcom,camcc-sun.yaml b/bindings/clock/qcom,camcc-sun.yaml index 31549563..40d1b15d 100644 --- a/bindings/clock/qcom,camcc-sun.yaml +++ b/bindings/clock/qcom,camcc-sun.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/qcom,camcc-sun.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Technologies, Inc. Camera Clock & Reset Controller Binding for SUN +title: Qualcomm Technologies, Inc. Camera Clock & Reset Controller maintainers: - Xubin Bai @@ -18,7 +18,9 @@ description: | properties: compatible: - const: qcom,camcc-sun + enum: + - qcom,sun-camcc + - qcom,tuna-camcc clocks: items: @@ -31,6 +33,7 @@ properties: - const: sleep_clk qcom,cam_crm-crmc: + $ref: /schemas/types.yaml#/definitions/phandle description: Phandle pointer to the CESTA crmc node vdd_mm-supply: From 1a7000b6f302bee9a5797f0fd1d177ccdf81a02d Mon Sep 17 00:00:00 2001 From: Prerna Singh Date: Wed, 24 Jul 2024 10:12:09 +0530 Subject: [PATCH 39/54] dt-bindings: clock: Add cpufreq debug hw bindings Add bindings for qcom-cpufreq-hw-debug controller. Change-Id: I4b388687d51f5c142fa4e3ba17ac3e038b966c2a Signed-off-by: Prerna Singh Signed-off-by: Imran Shaik --- bindings/cpufreq/cpufreq-qcom-hw-debug.yaml | 44 +++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 bindings/cpufreq/cpufreq-qcom-hw-debug.yaml diff --git a/bindings/cpufreq/cpufreq-qcom-hw-debug.yaml b/bindings/cpufreq/cpufreq-qcom-hw-debug.yaml new file mode 100644 index 00000000..869fa54f --- /dev/null +++ b/bindings/cpufreq/cpufreq-qcom-hw-debug.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw-debug.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. CPUFREQ + +maintainers: + - Taniya Das + +description: | + + CPUFREQ HW debug provide support to print the CPUFREQ_HW debug registers. + +properties: + compatible: + oneOf: + - description: v1 of CPUFREQ HW + items: + - const: qcom,cpufreq-hw-debug + + - description: v2 of CPUFREQ HW (EPSS) + items: + - const: qcom,cpufreq-hw-epss-debug + + qcom,freq-hw-domain: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: Frequency HW domain for each cpufreq policy + +required: + - compatible + - qcom,freq-hw-domain + +additionalProperties: false + +examples: + - | + cpufreq_hw_debug: qcom,cpufreq-hw-debug { + compatible = "qcom,cpufreq-hw-debug"; + qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>, + <&cpufreq_hw 2>; + }; +... From 388c7d47658a9d1dfad0647c54d05ff74fd90725 Mon Sep 17 00:00:00 2001 From: Saranya R Date: Thu, 25 Jul 2024 14:35:46 +0530 Subject: [PATCH 40/54] ARM: dts: msm: Define max no.of XHCI interrupters for parrot DWC3 host and XHCI plat now communicates the maximum number of interrupters the XHCI HCD will allocate. Since platforms only require a limited number of interrupters (i.e. 3) make sure XHCI doesn't allocate more than is required. Change-Id: I9f22a477377873284f1d69fe98c9a466ce237184 Signed-off-by: Saranya R --- qcom/parrot-usb.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/parrot-usb.dtsi b/qcom/parrot-usb.dtsi index 93856c1f..1bcd000e 100644 --- a/qcom/parrot-usb.dtsi +++ b/qcom/parrot-usb.dtsi @@ -79,6 +79,7 @@ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; tx-fifo-resize; + num-hc-interrupters = /bits/ 16 <3>; dr_mode = "peripheral"; maximum-speed = "super-speed"; }; From 7d4f9f859df918b8ae66f5d85cf489d4019636d6 Mon Sep 17 00:00:00 2001 From: Pranav Mahesh Phansalkar Date: Fri, 26 Jul 2024 12:21:17 +0530 Subject: [PATCH 41/54] ARM: dts: msm: Add smem nodes for kera Add smem nodes for kera SoC. Change-Id: Icaa26bfe01227bc21e0e3bce324779834f204e68 Signed-off-by: Pranav Mahesh Phansalkar --- qcom/kera-reserved-memory.dtsi | 4 +++- qcom/kera.dtsi | 11 +++++++++++ 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/qcom/kera-reserved-memory.dtsi b/qcom/kera-reserved-memory.dtsi index 8c9df41b..b990fbcb 100644 --- a/qcom/kera-reserved-memory.dtsi +++ b/qcom/kera-reserved-memory.dtsi @@ -66,8 +66,10 @@ }; smem_mem: smem_region@81d00000 { - no-map; + compatible = "qcom,smem"; reg = <0x0 0x81d00000 0x0 0x200000>; + hwlocks = <&tcsr_mutex 3>; + no-map; }; pdp_ns_shared_mem: pdp_ns_shared_region@81f00000 { diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 11101240..d7e6fe69 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -403,6 +403,17 @@ wakeup-parent = <&pdc>; }; + tcsr_mutex_block: syscon@1f40000 { + compatible = "syscon"; + reg = <0x1f40000 0x20000>; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x1000>; + #hwlock-cells = <1>; + }; + ipcc_mproc: qcom,ipcc@406000 { compatible = "qcom,ipcc"; reg = <0x406000 0x1000>; From f99ce7c5c15f165a67d3f2794827b0d7bcb4659f Mon Sep 17 00:00:00 2001 From: Raviteja Laggyshetty Date: Fri, 12 Apr 2024 22:50:05 +0530 Subject: [PATCH 42/54] dt-bindings: interconnect: Add interconnect bindings for TUNA Add interconnect device bindings for TUNA SoC. These devices can be used to describe any RPMH and NoC based interconnect devices. Change-Id: If040c6ebc9457b9385d75cbbe19ad7cd7bcb7994 Signed-off-by: Raviteja Laggyshetty --- bindings/interconnect/qcom,rpmh.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/bindings/interconnect/qcom,rpmh.yaml b/bindings/interconnect/qcom,rpmh.yaml index b8d0f7a8..02e1536b 100644 --- a/bindings/interconnect/qcom,rpmh.yaml +++ b/bindings/interconnect/qcom,rpmh.yaml @@ -184,6 +184,20 @@ properties: - qcom,ravelin-pcie_anoc - qcom,ravelin-system_noc - qcom,ravelin-video_aggre_noc + - qcom,tuna-aggre1_noc + - qcom,tuna-aggre2_noc + - qcom,tuna-clk_virt + - qcom,tuna-cnoc_cfg + - qcom,tuna-cnoc_main + - qcom,tuna-gem_noc + - qcom,tuna-lpass_ag_noc + - qcom,tuna-lpass_lpiaon_noc + - qcom,tuna-lpass_lpicx_noc + - qcom,tuna-mc_virt + - qcom,tuna-mmss_noc + - qcom,tuna-nsp_noc + - qcom,tuna-pcie_anoc + - qcom,tuna-system_noc '#interconnect-cells': true From 9b090db434ce9bb1dc2058efc200d3629b208819 Mon Sep 17 00:00:00 2001 From: Pranav Mahesh Phansalkar Date: Sat, 27 Jul 2024 09:38:20 +0530 Subject: [PATCH 43/54] ARM: dts: qcom: Add aoss, aop and tme nodes for kera Add devicetree nodes to enable qmp communication with aop and tme. Change-Id: I4e30e6854fcb1d29ea3733d9d59bb01acfe6667b Signed-off-by: Pranav Mahesh Phansalkar --- qcom/kera.dtsi | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index d7e6fe69..d75b7787 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -423,6 +423,44 @@ #mbox-cells = <2>; }; + aoss_qmp: power-controller@c300000 { + compatible = "qcom,aoss-qmp"; + reg = <0xc300000 0x400>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_AOP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + qmp_aop: qcom,qmp-aop { + compatible = "qcom,qmp-mbox"; + qcom,qmp = <&aoss_qmp>; + label = "aop"; + #mbox-cells = <1>; + }; + + qmp_tme: qcom,qmp-tme { + compatible = "qcom,qmp-mbox"; + qcom,remote-pid = <14>; + mboxes = <&ipcc_mproc IPCC_CLIENT_TME + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "tme_qmp"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "tme"; + qcom,early-boot; + priority = <0>; + mbox-desc-offset = <0x0>; + #mbox-cells = <1>; + }; + cache-controller@24800000 { compatible = "qcom,kera-llcc"; reg = <0x24800000 0x200000>, <0x24C00000 0x200000>, From adef50b93737126cc5e8e18b68600a2244cd8e45 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Mon, 29 Jul 2024 10:51:37 +0530 Subject: [PATCH 44/54] ARM: dts: msm: Add compatible for CPUFREQ HW DEBUG node on MONACO Add compatible string for CPUFREQ HW DEBUG node on MONACO platform. Change-Id: Ib9e7b96e3cc0a0b5ffb779d8d7e5f47034f30325 Signed-off-by: Imran Shaik --- qcom/monaco.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index ecb440e1..14e2b4b3 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -1143,7 +1143,7 @@ }; qcom,cpufreq-hw-debug@f521000 { - /* compatible = "qcom,cpufreq-hw-debug"; */ + compatible = "qcom,cpufreq-hw-debug"; reg = <0xf521000 0x1400>; reg-names = "domain-top"; qcom,freq-hw-domain = <&cpufreq_hw 0>; From eb19dd58e085c71b6fde4283a8f9589655689224 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Mon, 29 Jul 2024 12:35:00 +0530 Subject: [PATCH 45/54] ARM: dts: msm: Add shutdown ack for each remoteproc processors legacy SoCs had shutdown ack only available to modem DSP since waipio, it is even available for ADSP and CDSP and since we are adding shutdown ack timeout which would wait for these ack interrupts. Let's add them for ADSP and CDSP as well. Change-Id: I75c427be29d8d762617ccc1e595929edb9ff2c3b Signed-off-by: Mukesh Ojha --- qcom/sun.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index 154e21cf..73ea4248 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -2780,13 +2780,15 @@ <&adsp_smp2p_in 0 0>, <&adsp_smp2p_in 2 0>, <&adsp_smp2p_in 1 0>, - <&adsp_smp2p_in 3 0>; + <&adsp_smp2p_in 3 0>, + <&adsp_smp2p_in 7 0>; interrupt-names = "wdog", "fatal", "handover", "ready", - "stop-ack"; + "stop-ack", + "shutdown-ack"; /* Outputs to turing */ qcom,smem-states = <&adsp_smp2p_out 0>; @@ -2930,13 +2932,15 @@ <&cdsp_smp2p_in 0 0>, <&cdsp_smp2p_in 2 0>, <&cdsp_smp2p_in 1 0>, - <&cdsp_smp2p_in 3 0>; + <&cdsp_smp2p_in 3 0>, + <&cdsp_smp2p_in 7 0>; interrupt-names = "wdog", "fatal", "handover", "ready", - "stop-ack"; + "stop-ack", + "shutdown-ack"; /* Outputs to turing */ qcom,smem-states = <&cdsp_smp2p_out 0>; From 781cb25b20ea7d5f8711869d455a8f07aab4ef2f Mon Sep 17 00:00:00 2001 From: Kamal Wadhwa Date: Thu, 18 Jul 2024 17:31:53 +0530 Subject: [PATCH 46/54] ARM: dts: qcom: Add NVMEM cells FMD_CNT2_STOP & FMD_CHG_PON for PMK8550 Add NVMEM cells FMD_CNT2_STOP and FMD_CHG_PON for supporting Find-My-Device(FMD) feature. - FMD_CNT2_STOP controls the number of FMD cycles after which the feature will auto disable to save power in OFF mode. - FMD_CHG_PON can be use to disable USB PON feature for testing purpose. Change-Id: I0f217d413f2ec8c5616956c4e56fd7e469c52d56 Signed-off-by: Kamal Wadhwa --- qcom/pmk8550.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qcom/pmk8550.dtsi b/qcom/pmk8550.dtsi index 866dc1ea..21ddcae1 100644 --- a/qcom/pmk8550.dtsi +++ b/qcom/pmk8550.dtsi @@ -57,6 +57,14 @@ fmd_set: fmd-set@9a { reg = <0x9a 0x1>; }; + + fmd_chg_pon: fmd-chg-pon@9f { + reg = <0x9f 0x1>; + }; + + fmd_cnt2_stop: fmd-cnt2-stop@a2 { + reg = <0xa2 0x1>; + }; }; pmk8550_sdam_5: sdam@7400 { From d139cd2e2d16ab32f41609d475b50b2220368b39 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Tue, 30 Jul 2024 13:50:32 +0530 Subject: [PATCH 47/54] ARM: dts: msm: Remove unused SW DRVs for disp_crm device for sun Remove unused SW DRVs as keeping them makes them register with IRQs and leading to spurious IRQs. Change-Id: Iba8723b7ac734286668158fe793bde97f3f31eda Signed-off-by: Maulik Shah --- qcom/sun.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index 1465c37f..55b4d7cb 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -1385,7 +1385,7 @@ "disp_crm_drv5"; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>; qcom,hw-drv-ids = <0 1 2 3 4 5>; - qcom,sw-drv-ids = <0 1 2 3 4 5>; + qcom,sw-drv-ids = <0 2>; }; cam_crm: crm@adcb000 { From b7ca0a4904108c0b06966cb0ee25ba43d3357a82 Mon Sep 17 00:00:00 2001 From: Huang Yiwei Date: Tue, 30 Jul 2024 18:14:47 +0800 Subject: [PATCH 48/54] dt-bindings: Add new bindings for CPU MPAM Add new bindings for CPU MPAM. Change-Id: I856a137958140d1bc34cdfeadf5ddda4030a5c62 Signed-off-by: Huang Yiwei --- bindings/soc/qcom/qcom,cpu-mpam.yaml | 75 ++++++++++++++++++++++++++++ bindings/soc/qcom/qcom,mpam.yaml | 34 ++----------- 2 files changed, 79 insertions(+), 30 deletions(-) create mode 100644 bindings/soc/qcom/qcom,cpu-mpam.yaml diff --git a/bindings/soc/qcom/qcom,cpu-mpam.yaml b/bindings/soc/qcom/qcom,cpu-mpam.yaml new file mode 100644 index 00000000..f45d6639 --- /dev/null +++ b/bindings/soc/qcom/qcom,cpu-mpam.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,cpu-mpam.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. (QTI) CPU MPAM Driver + +maintainers: + - Huang Yiwei + +description: | + The Qualcomm Technologies, Inc. (QTI) CPU MPAM Driver provides configfs nodes + for userspace clients to set MPAM configuration with CPUCP firmware via + consolidated SCMI protocol. + +properties: + compatible: + items: + - const: qcom,cpu-mpam + + reg: + items: + - description: address and size of CPUCP DTIM area for CPUCP MPAM monitor data + + reg-names: + items: + - const: mon-base + + child-node: + description: | + Available components of the CPU MPAM. + type: object + properties: + qcom,msc-id: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: | + MSC id of the child node. + + qcom,msc-name: + $ref: '/schemas/types.yaml#/definitions/string' + description: | + MSC name of the child node. + + required: + - qcom,msc-id + - qcom,msc-name + + additionalProperties: false + +required: + - compatible + - reg + - reg-names + +additionalProperties: false + +examples: + - | + cpu_mpam: qcom,cpu_mpam { + compatible = "qcom,cpu-mpam"; + reg = <0x17b6f000 0x400>; + reg-names = "mon-base"; + + L2_0 { + qcom,msc-id = <0>; + qcom,msc-name = "L2_0"; + }; + + L2_1 { + qcom,msc-id = <1>; + qcom,msc-name = "L2_1"; + }; + }; +... diff --git a/bindings/soc/qcom/qcom,mpam.yaml b/bindings/soc/qcom/qcom,mpam.yaml index 540f1579..9cea0902 100644 --- a/bindings/soc/qcom/qcom,mpam.yaml +++ b/bindings/soc/qcom/qcom,mpam.yaml @@ -12,29 +12,17 @@ maintainers: - Huang Yiwei description: | - The Qualcomm Technologies, Inc. (QTI) MPAM Driver provides sysfs nodes for - userspace clients to communicate MPAM configuration settings with CPUCP - firmware via consolidated SCMI protocol. + The Qualcomm Technologies, Inc. (QTI) MPAM Driver provides raw APIs to + communicate MPAM configuration settings with CPUCP firmware via + consolidated SCMI protocol. properties: compatible: - enum: - - qcom,cpu-mpam - - qcom,platform-mpam - - qcom,mpam - - reg: items: - - description: address and size of CPUCP DTIM area for MPAM monitor data - - reg-names: - items: - - const: mon-base + - const: qcom,mpam required: - compatible - - reg - - reg-names additionalProperties: false @@ -42,19 +30,5 @@ examples: - | qcom_mpam: qcom,mpam { compatible = "qcom,mpam"; - reg = <0x17b6f000 0x400>; - reg-names = "mon-base"; - }; - - cpu_mpam: qcom,cpu_mpam { - compatible = "qcom,cpu-mpam"; - reg = <0x17b6f400 0x400>; - reg-names = "mon-base"; - }; - - noc_bw_mpam: qcom,noc_bw_mpam { - compatible = "qcom,platform-mpam"; - reg = <0x17b6f800 0x400>; - reg-names = "mon-base"; }; ... From 7a4a20762908960afc94161d2f30df5531ab1074 Mon Sep 17 00:00:00 2001 From: Huang Yiwei Date: Wed, 31 Jul 2024 09:48:38 +0800 Subject: [PATCH 49/54] dt-bindings: Add new bindings for platform MPAM Add new bindings for platform MPAM. Change-Id: I311a902e3135c5a825dcf4d6446d578489498b66 Signed-off-by: Huang Yiwei --- bindings/soc/qcom/qcom,platform-mpam.yaml | 114 ++++++++++++++++++++++ 1 file changed, 114 insertions(+) create mode 100644 bindings/soc/qcom/qcom,platform-mpam.yaml diff --git a/bindings/soc/qcom/qcom,platform-mpam.yaml b/bindings/soc/qcom/qcom,platform-mpam.yaml new file mode 100644 index 00000000..98818c32 --- /dev/null +++ b/bindings/soc/qcom/qcom,platform-mpam.yaml @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,platform-mpam.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. (QTI) Platform MPAM Driver + +maintainers: + - Huang Yiwei + +description: | + The Qualcomm Technologies, Inc. (QTI) Platform MPAM Driver provides configfs + nodes for userspace clients to set MPAM configuration with CPUCP firmware via + consolidated SCMI protocol. + +properties: + compatible: + items: + - const: qcom,platform-mpam + + reg: + items: + - description: address and size of CPUCP DTIM area for Platform MPAM + monitor data + + reg-names: + items: + - const: mon-base + + qcom,msc-id: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: | + MSC id of the component. + + qcom,msc-name: + $ref: '/schemas/types.yaml#/definitions/string' + description: | + MSC name of the component. + + qcom,gears: + $ref: '/schemas/types.yaml#/definitions/string-array' + description: | + Available gear names of the component. + + qcom,gear-id: + $ref: '/schemas/types.yaml#/definitions/uint32-array' + description: | + Available gear ids of the component. + + child-node: + description: | + Available clients of the Platform MPAM. + type: object + properties: + qcom,client-id: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: | + MSC id of the child node. + + qcom,client-name: + $ref: '/schemas/types.yaml#/definitions/string' + description: | + MSC name of the child node. + + required: + - qcom,client-id + - qcom,client-name + + additionalProperties: false + +required: + - compatible + - reg + - reg-names + - qcom,msc-id + - qcom,msc-name + - qcom,gears + - qcom,gear-id + +additionalProperties: false + +examples: + - | + noc_bw_mpam: qcom,noc_bw_mpam { + compatible = "qcom,platform-mpam"; + reg = <0x17b6f400 0x400>; + reg-names = "mon-base"; + qcom,msc-id = <3>; + qcom,msc-name = "noc_bw"; + qcom,gears = "low", "medium", "high", "veryhigh"; + qcom,gear-id = <1>, <2>, <3>, <4>; + + cpu_cluster0 { + qcom,client-id = <0x1>; + qcom,client-name = "cpu_cluster0"; + }; + + cpu_cluster1 { + qcom,client-id = <0x2>; + qcom,client-name = "cpu_cluster1"; + }; + + gpu { + qcom,client-id = <0x10>; + qcom,client-name = "gpu"; + }; + + nsp { + qcom,client-id = <0x100>; + qcom,client-name = "nsp"; + }; + }; +... From 69ee6cf4c799fda547edf790ec2cba1b18f115d2 Mon Sep 17 00:00:00 2001 From: Srinivasarao Pathipati Date: Fri, 12 Jul 2024 14:48:18 +0530 Subject: [PATCH 50/54] ARM: dts: msm: ravelin: Add msgq-names property for ravelin The commit 39dd329a019b ("mem-buf-msgq: Support multiple msgqs") mandates to have 'msgq-names' property in node 'mem-buf-msgq'. Adding default msgq entry to fix probe failure. Change-Id: I9dc802604cabff1b808c08302e1b77bf61fd7b3f Signed-off-by: Srinivasarao Pathipati --- qcom/ravelin.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/ravelin.dtsi b/qcom/ravelin.dtsi index 195d7c36..aaca77c2 100644 --- a/qcom/ravelin.dtsi +++ b/qcom/ravelin.dtsi @@ -807,6 +807,7 @@ qcom,mem-buf-msgq { compatible = "qcom,mem-buf-msgq"; + qcom,msgq-names = "trusted_vm"; }; qcom,rmtfs_sharedmem@0 { From 5f6d4987b102338860476cd3311e9ddc38b73e04 Mon Sep 17 00:00:00 2001 From: Srinivasarao Pathipati Date: Thu, 1 Aug 2024 16:20:04 +0530 Subject: [PATCH 51/54] ARM: dts: msm: ravelin: remove atomic in secure use case for ravelin Atomic and secure domains are not a legal combination so remove atomic entry for secure use case. Change-Id: Ibd163da686e0d982dcb085ab32d4f01cdb4fcf69 Signed-off-by: Srinivasarao Pathipati --- qcom/msm-arm-smmu-ravelin.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/qcom/msm-arm-smmu-ravelin.dtsi b/qcom/msm-arm-smmu-ravelin.dtsi index 6ebf4e64..68f9adeb 100644 --- a/qcom/msm-arm-smmu-ravelin.dtsi +++ b/qcom/msm-arm-smmu-ravelin.dtsi @@ -372,7 +372,6 @@ usecase7_apps_secure { compatible = "qcom,iommu-debug-usecase"; iommus = <&apps_smmu 0x7e0 0>; - qcom,iommu-dma = "atomic"; qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */ }; }; From 20818089aea0aa3a6fc780f7e7d1f2a50deab910 Mon Sep 17 00:00:00 2001 From: Prakash Yadachi Date: Fri, 2 Aug 2024 16:01:07 +0530 Subject: [PATCH 52/54] ARM: dts: qcom: Update bootargs for parrot and ravelin Removed console=ttyMSM0,115200n8 form bootargs for parrot and ravelin targets. Change-Id: I7b1c942343e71e809d234800f7ea6d6469a4c306 Signed-off-by: Prakash Yadachi --- qcom/parrot.dtsi | 2 +- qcom/ravelin.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/parrot.dtsi b/qcom/parrot.dtsi index deda384c..aeebe139 100644 --- a/qcom/parrot.dtsi +++ b/qcom/parrot.dtsi @@ -29,7 +29,7 @@ chosen: chosen { stdout-path = "/soc/qcom,qup_uart@98c000:115200n8"; - bootargs = "console=ttyMSM0,115200n8 loglevel=6 log_buf_len=256K kernel.panic_on_rcu_stall=1 loop.max_part=7 pcie_ports=compat allow_mismatched_32bit_el0 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 ftrace_dump_on_oops pstore.compress=none kpti=0 swiotlb=noforce cgroup.memory=nokmem,nosocket kswapd_per_node=2 slub_debug=- allow_file_spec_access cpufreq.default_governor=performance transparent_hugepage=never page_poison=on can.stats_timer=0 disable_dma32=on android12_only.will_be_removed_soon.memblock_nomap_remove=on"; + bootargs = "loglevel=6 log_buf_len=256K kernel.panic_on_rcu_stall=1 loop.max_part=7 pcie_ports=compat allow_mismatched_32bit_el0 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 ftrace_dump_on_oops pstore.compress=none kpti=0 swiotlb=noforce cgroup.memory=nokmem,nosocket kswapd_per_node=2 slub_debug=- allow_file_spec_access cpufreq.default_governor=performance transparent_hugepage=never page_poison=on can.stats_timer=0 disable_dma32=on android12_only.will_be_removed_soon.memblock_nomap_remove=on"; }; memory { device_type = "memory"; reg = <0 0 0 0>; }; diff --git a/qcom/ravelin.dtsi b/qcom/ravelin.dtsi index 195d7c36..7acf6a47 100644 --- a/qcom/ravelin.dtsi +++ b/qcom/ravelin.dtsi @@ -28,7 +28,7 @@ chosen: chosen { stdout-path = "/soc/qcom,qup_uart@a88000:115200n8"; - bootargs = "console=ttyMSM0,115200n8 loglevel=6 log_buf_len=256K kernel.panic_on_rcu_stall=1 loop.max_part=7 pcie_ports=compat kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 ftrace_dump_on_oops pstore.compress=none kpti=0 swiotlb=noforce cgroup.memory=nokmem,nosocket kswapd_per_node=2 slub_debug=- allow_file_spec_access cpufreq.default_governor=performance transparent_hugepage=never can.stats_timer=0 disable_dma32=on android12_only.will_be_removed_soon.memblock_nomap_remove=on pcie_ports=compat"; + bootargs = "loglevel=6 log_buf_len=256K kernel.panic_on_rcu_stall=1 loop.max_part=7 pcie_ports=compat kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 ftrace_dump_on_oops pstore.compress=none kpti=0 swiotlb=noforce cgroup.memory=nokmem,nosocket kswapd_per_node=2 slub_debug=- allow_file_spec_access cpufreq.default_governor=performance transparent_hugepage=never can.stats_timer=0 disable_dma32=on android12_only.will_be_removed_soon.memblock_nomap_remove=on pcie_ports=compat"; }; memory { device_type = "memory"; reg = <0 0 0 0>; }; From 0f6b6ee49abe47d95d1148d99dcb8898e5007781 Mon Sep 17 00:00:00 2001 From: Huang Yiwei Date: Wed, 31 Jul 2024 10:32:32 +0800 Subject: [PATCH 53/54] dt-bindings: Add new bindings for SLC MPAM Add new bindings for SLC MPAM. Change-Id: I21e19e73ff17916f84a25a52535e81ea97cae8d6 Signed-off-by: Huang Yiwei --- bindings/soc/qcom/qcom,slc-mpam.yaml | 102 +++++++++++++++++++++++++++ 1 file changed, 102 insertions(+) create mode 100644 bindings/soc/qcom/qcom,slc-mpam.yaml diff --git a/bindings/soc/qcom/qcom,slc-mpam.yaml b/bindings/soc/qcom/qcom,slc-mpam.yaml new file mode 100644 index 00000000..f4bf701a --- /dev/null +++ b/bindings/soc/qcom/qcom,slc-mpam.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,slc-mpam.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. (QTI) SLC MPAM Driver + +maintainers: + - Huang Yiwei + +description: | + The Qualcomm Technologies, Inc. (QTI) SLC MPAM Driver provides configfs + nodes for userspace clients to set MPAM configuration with CPUCP firmware via + consolidated SCMI protocol. + +properties: + compatible: + items: + - const: qcom,mpam-slc + + qcom,msc-name: + $ref: '/schemas/types.yaml#/definitions/string' + description: | + MSC name of the component. + + child-node: + description: | + Available clients of the SLC MPAM. + type: object + properties: + qcom,client-id: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: | + MSC id of the child node. + + qcom,client-name: + $ref: '/schemas/types.yaml#/definitions/string' + description: | + MSC name of the child node. + + child-node: + description: | + Available partition of the client. + type: object + properties: + qcom,part-id: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: | + Part-id of the child node. + + required: + - qcom,part-id + + additionalProperties: false + + required: + - qcom,client-id + - qcom,client-name + + additionalProperties: false + +required: + - compatible + - qcom,msc-name + +additionalProperties: false + +examples: + - | + qcom_slc_mpam: qcom,slc_mpam { + compatible = "qcom,mpam-slc"; + qcom,msc-name = "slc"; + + apps { + qcom,client-id = <0>; + qcom,client-name = "apps"; + + part-id0 { + qcom,part-id = <0>; + }; + + part-id1 { + qcom,part-id = <1>; + }; + + part-id2 { + qcom,part-id = <2>; + }; + }; + + gpu { + qcom,client-id = <1>; + qcom,client-name = "gpu"; + }; + + nsp { + qcom,client-id = <2>; + qcom,client-name = "nsp"; + }; + }; +... From 0455109209e41cb71412b3348ef1d2f911f56239 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Tue, 6 Aug 2024 14:06:36 +0530 Subject: [PATCH 54/54] ARM: dts: msm: Add sw drv3 of disp_crm for sun SW drv3 may be used sometimes by display panel. Add it. Change-Id: I03fc0bee08c44447caf689b747b054f4aa62ffca Signed-off-by: Maulik Shah --- qcom/sun.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index d39a5083..19a60eaa 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -1385,7 +1385,7 @@ "disp_crm_drv5"; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>; qcom,hw-drv-ids = <0 1 2 3 4 5>; - qcom,sw-drv-ids = <0 2>; + qcom,sw-drv-ids = <0 2 3>; }; cam_crm: crm@adcb000 {