diff --git a/bindings/clock/qcom,cambistmclkcc.yaml b/bindings/clock/qcom,cambistmclkcc.yaml index 41eedd80..1d178d46 100644 --- a/bindings/clock/qcom,cambistmclkcc.yaml +++ b/bindings/clock/qcom,cambistmclkcc.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/qcom,cambistmclkcc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Technologies, Inc. Camera BIST MCLK CC Controller Binding +title: Qualcomm Technologies, Inc. Camera BIST MCLK CC Controller maintainers: - Xubin Bai @@ -18,7 +18,8 @@ description: | properties: compatible: enum: - - qcom,cambistmclkcc-sun + - qcom,sun-cambistmclkcc + - qcom,tuna-cambistmclkcc clocks: items: diff --git a/bindings/clock/qcom,camcc-sun.yaml b/bindings/clock/qcom,camcc-sun.yaml index 31549563..40d1b15d 100644 --- a/bindings/clock/qcom,camcc-sun.yaml +++ b/bindings/clock/qcom,camcc-sun.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/qcom,camcc-sun.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Technologies, Inc. Camera Clock & Reset Controller Binding for SUN +title: Qualcomm Technologies, Inc. Camera Clock & Reset Controller maintainers: - Xubin Bai @@ -18,7 +18,9 @@ description: | properties: compatible: - const: qcom,camcc-sun + enum: + - qcom,sun-camcc + - qcom,tuna-camcc clocks: items: @@ -31,6 +33,7 @@ properties: - const: sleep_clk qcom,cam_crm-crmc: + $ref: /schemas/types.yaml#/definitions/phandle description: Phandle pointer to the CESTA crmc node vdd_mm-supply: diff --git a/bindings/clock/qcom,gcc-sun.yaml b/bindings/clock/qcom,gcc-sun.yaml index 29ca3d1a..fa5755e4 100644 --- a/bindings/clock/qcom,gcc-sun.yaml +++ b/bindings/clock/qcom,gcc-sun.yaml @@ -22,6 +22,7 @@ properties: enum: - qcom,gcc-sun - qcom,tuna-gcc + - qcom,kera-gcc clocks: items: diff --git a/bindings/clock/qcom,gpucc.yaml b/bindings/clock/qcom,gpucc.yaml index ecf3cd6a..ccdb4c98 100644 --- a/bindings/clock/qcom,gpucc.yaml +++ b/bindings/clock/qcom,gpucc.yaml @@ -26,6 +26,7 @@ description: | dt-bindings/clock/qcom,gpucc-sun.h dt-bindings/clock/qcom,gpucc-parrot.h dt-bindings/clock/qcom,gpucc-monaco.h + dt-bindings/clock/qcom,gpucc-tuna.h properties: compatible: @@ -43,6 +44,7 @@ properties: - qcom,sun-gpucc - qcom,parrot-gpucc - qcom,monaco-gpucc + - qcom,tuna-gpucc clocks: items: diff --git a/bindings/clock/qcom,tcsrcc.yaml b/bindings/clock/qcom,tcsrcc.yaml index 18ada41c..4e0ab14f 100644 --- a/bindings/clock/qcom,tcsrcc.yaml +++ b/bindings/clock/qcom,tcsrcc.yaml @@ -22,6 +22,7 @@ properties: - qcom,pineapple-tcsrcc - qcom,sun-tcsrcc - qcom,tuna-tcsrcc + - qcom,kera-tcsrcc required: - compatible diff --git a/bindings/cpufreq/cpufreq-qcom-hw-debug.yaml b/bindings/cpufreq/cpufreq-qcom-hw-debug.yaml new file mode 100644 index 00000000..869fa54f --- /dev/null +++ b/bindings/cpufreq/cpufreq-qcom-hw-debug.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw-debug.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. CPUFREQ + +maintainers: + - Taniya Das + +description: | + + CPUFREQ HW debug provide support to print the CPUFREQ_HW debug registers. + +properties: + compatible: + oneOf: + - description: v1 of CPUFREQ HW + items: + - const: qcom,cpufreq-hw-debug + + - description: v2 of CPUFREQ HW (EPSS) + items: + - const: qcom,cpufreq-hw-epss-debug + + qcom,freq-hw-domain: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: Frequency HW domain for each cpufreq policy + +required: + - compatible + - qcom,freq-hw-domain + +additionalProperties: false + +examples: + - | + cpufreq_hw_debug: qcom,cpufreq-hw-debug { + compatible = "qcom,cpufreq-hw-debug"; + qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>, + <&cpufreq_hw 2>; + }; +... diff --git a/bindings/input/touchscreen/raydium_ts.yaml b/bindings/input/touchscreen/raydium_ts.yaml new file mode 100644 index 00000000..965b375a --- /dev/null +++ b/bindings/input/touchscreen/raydium_ts.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/touchscreen/raydium_ts.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Raydium WT030 touch controller + +description: The Raydium Touch controller is connected to + the host processor via I2C. The controller generates + interrupts when the user touches the panel. The host + controller is expected to read the touch coordinates over + I2C and pass the coordinates to the rest of the system. + +maintainers: + - Akshay Gola + +allOf: + - $ref: touchscreen.yaml# + +properties: + compatible: + enum: + - raydium,raydium-ts + + reg: + description: i2c slave address of the device. + + interrupt-parent: + description: parent of interrupt. + + raydium,reset-gpio: + description: reset gpio + + raydium,irq-gpio: + description: irq gpio + + vdd_ana-supply: + description: digital voltage power supply needed to power device. + + vcc_i2c-supply: + description: i2c voltage power supply needed to power device. + +unevaluatedProperties: false + +required: + - compatible + - reg + - interrupt-parent + - raydium,irq-gpio + - raydium,reset-gpio + - vdd_ana-supply + - vcc_i2c-supply + +examples: + - | + i2c@78b7000 { + status = "ok"; + raydium_ts@39 { + compatible = "raydium,raydium-ts"; + reg = <0x39>; + interrupt-parent = <&msm_gpio>; + interrupts = <13 0x2008>; + vdd_ana-supply = <&pm8916_l17>; + vcc_i2c-supply = <&pm8916_l6>; + pinctrl-names ="pmx_ts_active","pmx_ts_suspend","pmx_ts_release"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&ts_release>; + raydium,reset-gpio = <&msm_gpio 12 0x00>; + raydium,irq-gpio = <&msm_gpio 13 0x00>; + raydium,num-max-touches = <2>; + raydium,soft-reset-delay-ms = <50>; + raydium,hard-reset-delay-ms = <100>; + raydium,x_max = <390>; + raydium,y_max = <390>; + raydium,display-coords= <0 0 390 390>; + raydium,fw_id = <0x2202> + }; + }; diff --git a/bindings/interconnect/qcom,rpmh.yaml b/bindings/interconnect/qcom,rpmh.yaml index b8d0f7a8..02e1536b 100644 --- a/bindings/interconnect/qcom,rpmh.yaml +++ b/bindings/interconnect/qcom,rpmh.yaml @@ -184,6 +184,20 @@ properties: - qcom,ravelin-pcie_anoc - qcom,ravelin-system_noc - qcom,ravelin-video_aggre_noc + - qcom,tuna-aggre1_noc + - qcom,tuna-aggre2_noc + - qcom,tuna-clk_virt + - qcom,tuna-cnoc_cfg + - qcom,tuna-cnoc_main + - qcom,tuna-gem_noc + - qcom,tuna-lpass_ag_noc + - qcom,tuna-lpass_lpiaon_noc + - qcom,tuna-lpass_lpicx_noc + - qcom,tuna-mc_virt + - qcom,tuna-mmss_noc + - qcom,tuna-nsp_noc + - qcom,tuna-pcie_anoc + - qcom,tuna-system_noc '#interconnect-cells': true diff --git a/bindings/soc/qcom/qcom,bwmon.yaml b/bindings/soc/qcom/qcom,bwmon.yaml index 4bfac87b..ccfbcf48 100644 --- a/bindings/soc/qcom/qcom,bwmon.yaml +++ b/bindings/soc/qcom/qcom,bwmon.yaml @@ -8,7 +8,7 @@ title: Qualcomm Technologies, Inc. (QTI) BWMON Driver maintainers: - avajid@quicinc.com - - gurbaror@quicinc.com + - Shivnandan Kumar description: | The Qualcomm Technologies, Inc. BWMON Driver monitors bandwidth counters that @@ -31,8 +31,15 @@ properties: maxItems: 2 reg-names: - - const: base - - const: global_base + items: + - const: base + - const: global_base + + "#address-cells": + enum: [1, 2] + + "#size-cells": + enum: [1, 2] interrupts: description: Lists the threshold IRQ. @@ -49,7 +56,6 @@ properties: node will be using for voting in the SLOW path. qcom,hw-timer-hz: - $ref: /schemas/types.yaml#/definitions/uint32 description: Hardware sampling rate in Hz. This field must be specified for "qcom,bwmon4" @@ -69,19 +75,34 @@ properties: description: Number of bytes monitor counts in + qcom,map-ne: + type: boolean + description: | + Specify if the bwmon memory region should be mapped as nE (non-Early). + required: - compatible - reg - reg-names - interrupts - - qcom,target-dev + - qcom,mport - qcom,hw-timer-hz + - qcom,count-unit + - qcom,target-dev + - '#address-cells' + - '#size-cells' + +additionalProperties: true examples: - | + #include bwmon_llcc: qcom,bwmon-llcc@90b6400 { compatible = "qcom,bwmon4"; - reg = <0x90b6400 0x300>, <0x90b6300 0x200>; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x90b6400 0x300>, + <0x90b6300 0x200>; reg-names = "base", "global_base"; interrupts = ; qcom,mport = <0>; diff --git a/bindings/soc/qcom/qcom,cpu-mpam.yaml b/bindings/soc/qcom/qcom,cpu-mpam.yaml new file mode 100644 index 00000000..f45d6639 --- /dev/null +++ b/bindings/soc/qcom/qcom,cpu-mpam.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,cpu-mpam.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. (QTI) CPU MPAM Driver + +maintainers: + - Huang Yiwei + +description: | + The Qualcomm Technologies, Inc. (QTI) CPU MPAM Driver provides configfs nodes + for userspace clients to set MPAM configuration with CPUCP firmware via + consolidated SCMI protocol. + +properties: + compatible: + items: + - const: qcom,cpu-mpam + + reg: + items: + - description: address and size of CPUCP DTIM area for CPUCP MPAM monitor data + + reg-names: + items: + - const: mon-base + + child-node: + description: | + Available components of the CPU MPAM. + type: object + properties: + qcom,msc-id: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: | + MSC id of the child node. + + qcom,msc-name: + $ref: '/schemas/types.yaml#/definitions/string' + description: | + MSC name of the child node. + + required: + - qcom,msc-id + - qcom,msc-name + + additionalProperties: false + +required: + - compatible + - reg + - reg-names + +additionalProperties: false + +examples: + - | + cpu_mpam: qcom,cpu_mpam { + compatible = "qcom,cpu-mpam"; + reg = <0x17b6f000 0x400>; + reg-names = "mon-base"; + + L2_0 { + qcom,msc-id = <0>; + qcom,msc-name = "L2_0"; + }; + + L2_1 { + qcom,msc-id = <1>; + qcom,msc-name = "L2_1"; + }; + }; +... diff --git a/bindings/soc/qcom/qcom,cpucp_fast.yaml b/bindings/soc/qcom/qcom,cpucp_fast.yaml new file mode 100644 index 00000000..7269c4cc --- /dev/null +++ b/bindings/soc/qcom/qcom,cpucp_fast.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,cpucp_fast.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. CPUCP FAST driver + +maintainers: + - Chandrasekhar Lingutla + +description: | + This device listens interrupts from CPUCP via mailbox and + sends notification to scheduler. + +properties: + compatible: + const: qcom,cpucp_fast + + mboxes: + description: Mailboxes used for Interrupt from CPUCP + + qcom,policy-cpus: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Base CPU index for cpufreq policy + +required: + - compatible + - mboxes + - qcom,policy-cpus + +additionalProperties: false + +examples: + - | + soc { + cpucp_fast: qcom,cpucp_fast { + compatible = "qcom,cpucp_fast"; + mboxes = <&cpucp 5>; + qcom,policy-cpus = <6>; + }; + }; +... diff --git a/bindings/soc/qcom/qcom,mpam.yaml b/bindings/soc/qcom/qcom,mpam.yaml index 540f1579..9cea0902 100644 --- a/bindings/soc/qcom/qcom,mpam.yaml +++ b/bindings/soc/qcom/qcom,mpam.yaml @@ -12,29 +12,17 @@ maintainers: - Huang Yiwei description: | - The Qualcomm Technologies, Inc. (QTI) MPAM Driver provides sysfs nodes for - userspace clients to communicate MPAM configuration settings with CPUCP - firmware via consolidated SCMI protocol. + The Qualcomm Technologies, Inc. (QTI) MPAM Driver provides raw APIs to + communicate MPAM configuration settings with CPUCP firmware via + consolidated SCMI protocol. properties: compatible: - enum: - - qcom,cpu-mpam - - qcom,platform-mpam - - qcom,mpam - - reg: items: - - description: address and size of CPUCP DTIM area for MPAM monitor data - - reg-names: - items: - - const: mon-base + - const: qcom,mpam required: - compatible - - reg - - reg-names additionalProperties: false @@ -42,19 +30,5 @@ examples: - | qcom_mpam: qcom,mpam { compatible = "qcom,mpam"; - reg = <0x17b6f000 0x400>; - reg-names = "mon-base"; - }; - - cpu_mpam: qcom,cpu_mpam { - compatible = "qcom,cpu-mpam"; - reg = <0x17b6f400 0x400>; - reg-names = "mon-base"; - }; - - noc_bw_mpam: qcom,noc_bw_mpam { - compatible = "qcom,platform-mpam"; - reg = <0x17b6f800 0x400>; - reg-names = "mon-base"; }; ... diff --git a/bindings/soc/qcom/qcom,platform-mpam.yaml b/bindings/soc/qcom/qcom,platform-mpam.yaml new file mode 100644 index 00000000..98818c32 --- /dev/null +++ b/bindings/soc/qcom/qcom,platform-mpam.yaml @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,platform-mpam.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. (QTI) Platform MPAM Driver + +maintainers: + - Huang Yiwei + +description: | + The Qualcomm Technologies, Inc. (QTI) Platform MPAM Driver provides configfs + nodes for userspace clients to set MPAM configuration with CPUCP firmware via + consolidated SCMI protocol. + +properties: + compatible: + items: + - const: qcom,platform-mpam + + reg: + items: + - description: address and size of CPUCP DTIM area for Platform MPAM + monitor data + + reg-names: + items: + - const: mon-base + + qcom,msc-id: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: | + MSC id of the component. + + qcom,msc-name: + $ref: '/schemas/types.yaml#/definitions/string' + description: | + MSC name of the component. + + qcom,gears: + $ref: '/schemas/types.yaml#/definitions/string-array' + description: | + Available gear names of the component. + + qcom,gear-id: + $ref: '/schemas/types.yaml#/definitions/uint32-array' + description: | + Available gear ids of the component. + + child-node: + description: | + Available clients of the Platform MPAM. + type: object + properties: + qcom,client-id: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: | + MSC id of the child node. + + qcom,client-name: + $ref: '/schemas/types.yaml#/definitions/string' + description: | + MSC name of the child node. + + required: + - qcom,client-id + - qcom,client-name + + additionalProperties: false + +required: + - compatible + - reg + - reg-names + - qcom,msc-id + - qcom,msc-name + - qcom,gears + - qcom,gear-id + +additionalProperties: false + +examples: + - | + noc_bw_mpam: qcom,noc_bw_mpam { + compatible = "qcom,platform-mpam"; + reg = <0x17b6f400 0x400>; + reg-names = "mon-base"; + qcom,msc-id = <3>; + qcom,msc-name = "noc_bw"; + qcom,gears = "low", "medium", "high", "veryhigh"; + qcom,gear-id = <1>, <2>, <3>, <4>; + + cpu_cluster0 { + qcom,client-id = <0x1>; + qcom,client-name = "cpu_cluster0"; + }; + + cpu_cluster1 { + qcom,client-id = <0x2>; + qcom,client-name = "cpu_cluster1"; + }; + + gpu { + qcom,client-id = <0x10>; + qcom,client-name = "gpu"; + }; + + nsp { + qcom,client-id = <0x100>; + qcom,client-name = "nsp"; + }; + }; +... diff --git a/bindings/soc/qcom/qcom,slc-mpam.yaml b/bindings/soc/qcom/qcom,slc-mpam.yaml new file mode 100644 index 00000000..f4bf701a --- /dev/null +++ b/bindings/soc/qcom/qcom,slc-mpam.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,slc-mpam.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. (QTI) SLC MPAM Driver + +maintainers: + - Huang Yiwei + +description: | + The Qualcomm Technologies, Inc. (QTI) SLC MPAM Driver provides configfs + nodes for userspace clients to set MPAM configuration with CPUCP firmware via + consolidated SCMI protocol. + +properties: + compatible: + items: + - const: qcom,mpam-slc + + qcom,msc-name: + $ref: '/schemas/types.yaml#/definitions/string' + description: | + MSC name of the component. + + child-node: + description: | + Available clients of the SLC MPAM. + type: object + properties: + qcom,client-id: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: | + MSC id of the child node. + + qcom,client-name: + $ref: '/schemas/types.yaml#/definitions/string' + description: | + MSC name of the child node. + + child-node: + description: | + Available partition of the client. + type: object + properties: + qcom,part-id: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: | + Part-id of the child node. + + required: + - qcom,part-id + + additionalProperties: false + + required: + - qcom,client-id + - qcom,client-name + + additionalProperties: false + +required: + - compatible + - qcom,msc-name + +additionalProperties: false + +examples: + - | + qcom_slc_mpam: qcom,slc_mpam { + compatible = "qcom,mpam-slc"; + qcom,msc-name = "slc"; + + apps { + qcom,client-id = <0>; + qcom,client-name = "apps"; + + part-id0 { + qcom,part-id = <0>; + }; + + part-id1 { + qcom,part-id = <1>; + }; + + part-id2 { + qcom,part-id = <2>; + }; + }; + + gpu { + qcom,client-id = <1>; + qcom,client-name = "gpu"; + }; + + nsp { + qcom,client-id = <2>; + qcom,client-name = "nsp"; + }; + }; +... diff --git a/bindings/sound/qcom,wcd_codec.yaml b/bindings/sound/qcom,wcd_codec.yaml new file mode 100644 index 00000000..e75c3bde --- /dev/null +++ b/bindings/sound/qcom,wcd_codec.yaml @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/qcom,wcd_codec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. WCD audio CODEC + +maintainers: + - Swapnil Kangralkar + +description: + This document defines the bindings for pm5100_spmi child node of SPMI bus + required for besbev codec in order to access SPMI register to reset the + peripheral. + +properties: + compatible: + const: qcom,pm5100-spmi + +required: + - compatible + +additionalProperties: false + +examples: + - | + &spmi_bus { + pm5100_cdc: qcom,pm5100-cdc { + compatible = "qcom,pm5100-spmi"; + }; + }; diff --git a/qcom/Makefile b/qcom/Makefile index 1bcfd1a2..e309beee 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -19,6 +19,7 @@ SUN_BASE_DTB += sun.dtb sun-v2.dtb sun-tp.dtb sun-tp-v2.dtb SUN_APQ_BASE_DTB += sunp.dtb sunp-v2.dtb sunp-tp.dtb sunp-tp-v2.dtb SUN_BOARDS += \ + sun-mtp-3.5mm-kiwi-v8-overlay.dtbo \ sun-mtp-3.5mm-overlay.dtbo \ sun-mtp-kiwi-overlay.dtbo \ sun-mtp-kiwi-v8-overlay.dtbo \ @@ -130,8 +131,8 @@ parrot-dtb-$(CONFIG_ARCH_PARROT) += \ parrot-overlays-dtb-$(CONFIG_ARCH_PARROT) += $(PARROT_BOARDS) $(PARROT_BASE_DTB) $(PARROT_4GB_BOARDS) $(PARROT_4GB_BASE_DTB) dtb-y += $(parrot-dtb-y) -RAVELIN_BASE_DTB += ravelin.dtb ravelinp.dtb -RAVELIN_4GB_BASE_DTB += ravelin-4gb.dtb ravelinp-4gb.dtb +RAVELIN_BASE_DTB += ravelin.dtb ravelinp.dtb ravelin-sg.dtb ravelinp-sg.dtb +RAVELIN_4GB_BASE_DTB += ravelin-4gb.dtb ravelinp-4gb.dtb ravelin-sg.dtb ravelinp-sg.dtb RAVELIN_BOARDS += \ ravelin-rumi-overlay.dtbo \ diff --git a/qcom/kera-dma-heaps.dtsi b/qcom/kera-dma-heaps.dtsi new file mode 100644 index 00000000..6472b080 --- /dev/null +++ b/qcom/kera-dma-heaps.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + qcom,dma-heaps { + compatible = "qcom,dma-heaps"; + depends-on-supply = <&qcom_scm>; + }; +}; diff --git a/qcom/kera-reserved-memory.dtsi b/qcom/kera-reserved-memory.dtsi new file mode 100644 index 00000000..b990fbcb --- /dev/null +++ b/qcom/kera-reserved-memory.dtsi @@ -0,0 +1,236 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gunyah_hyp_mem: gunyah_hyp_region@80000000 { + no-map; + reg = <0x0 0x80000000 0x0 0xe00000>; + }; + + cpusys_vm_mem: cpusys_vm_region@80e00000 { + no-map; + reg = <0x0 0x80e00000 0x0 0x400000>; + }; + + cpucp_pdp_mem: cpucp_region@81200000 { + no-map; + reg = <0x0 0x81200000 0x0 0x200000>; + }; + + /* + * hyp_tags_mem is dynamically removed from the RAM + * partition tables before boot occurs. Size of region + * varies. + */ + + xbl_dtlog_mem: xbl_dtlog_region@81a00000 { + no-map; + reg = <0x0 0x81a00000 0x0 0x40000>; + }; + + aop_image_mem: aop_image_region@81c00000 { + no-map; + reg = <0x0 0x81c00000 0x0 0x60000>; + }; + + aop_cmd_db_mem: aop_cmd_db_region@81c60000 { + compatible = "qcom,cmd-db"; + no-map; + reg = <0x0 0x81c60000 0x0 0x20000>; + }; + + aop_config_mem: aop_config_region@81c80000 { + no-map; + reg = <0x0 0x81c80000 0x0 0x20000>; + }; + + tme_crash_dump_mem: tme_crash_dump_region@81ca0000 { + no-map; + reg = <0x0 0x81ca0000 0x0 0x40000>; + }; + + tme_log_mem: tme_log_region@81ce0000 { + no-map; + reg = <0x0 0x81ce0000 0x0 0x4000>; + }; + + uefi_log_mem: uefi_log_region@81ce4000 { + no-map; + reg = <0x0 0x81ce4000 0x0 0x10000>; + }; + + smem_mem: smem_region@81d00000 { + compatible = "qcom,smem"; + reg = <0x0 0x81d00000 0x0 0x200000>; + hwlocks = <&tcsr_mutex 3>; + no-map; + }; + + pdp_ns_shared_mem: pdp_ns_shared_region@81f00000 { + no-map; + reg = <0x0 0x81f00000 0x0 0x100000>; + }; + + cpucp_scandump_mem: cpucp_scandump_region@82000000 { + no-map; + reg = <0x0 0x82000000 0x0 0x380000>; + }; + + adsp_mhi_mem: adsp_mhi_region@82380000 { + no-map; + reg = <0x0 0x82380000 0x0 0x20000>; + }; + + soccp_sdi_mem: soccp_sdi_region@823a0000 { + no-map; + reg = <0x0 0x823a0000 0x0 0x40000>; + }; + + pmic_minii_dump_mem: pmic_minii_dump_region@823e0000 { + no-map; + reg = <0x0 0x823e0000 0x0 0x80000>; + }; + + pvm_fw_mem: pvm_fw_region@824a0000 { + no-map; + reg = <0x0 0x824a0000 0x0 0x100000>; + }; + + hyp_mem_database_mem: hyp_mem_database_region@825a0000 { + no-map; + reg = <0x0 0x825a0000 0x0 0x60000>; + }; + + global_sync_mem: global_sync_region@82600000 { + no-map; + reg = <0x0 0x82600000 0x0 0x100000>; + }; + + tz_stat_mem: tz_stat_region@82700000 { + no-map; + reg = <0x0 0x82700000 0x0 0x100000>; + }; + + dsm_partition_1_mem: dsm_partition_1_region@84a00000 { + no-map; + reg = <0x0 0x84a00000 0x0 0x4900000>; + }; + + dsm_partition_2_mem: dsm_partition_2_region@89300000 { + no-map; + reg = <0x0 0x89300000 0x0 0xa80000>; + }; + + mpss_mem: mpss_region@89e00000 { + no-map; + reg = <0x0 0x89e00000 0x0 0x11200000>; + }; + + q6_mpss_dtb_mem: q6_mpss_dtb_region@9b000000 { + no-map; + reg = <0x0 0x9b000000 0x0 0x80000>; + }; + + ipa_fw_mem: ipa_fw_region@9b080000 { + no-map; + reg = <0x0 0x9b080000 0x0 0x10000>; + }; + + ipa_gsi_mem: ipa_gsi_region@9b090000 { + no-map; + reg = <0x0 0x9b090000 0x0 0xa000>; + }; + + gpu_microcode_mem: gpu_microcode_region@9b09a000 { + no-map; + reg = <0x0 0x9b09a000 0x0 0x2000>; + }; + + camera_mem: camera_region@9b300000 { + no-map; + reg = <0x0 0x9b300000 0x0 0x800000>; + }; + + camera_2_mem: camera_2_region@9bb00000 { + no-map; + reg = <0x0 0x9bb00000 0x0 0x800000>; + }; + + video_mem: video_region@9c300000 { + no-map; + reg = <0x0 0x9c300000 0x0 0x800000>; + }; + + cvp_mem: cvp_region@9cb00000 { + no-map; + reg = <0x0 0x9cb00000 0x0 0x700000>; + }; + + cdsp_mem: cdsp_region@9d200000 { + no-map; + reg = <0x0 0x9d200000 0x0 0x2000000>; + }; + + q6_cdsp_dtb_mem: q6_cdsp_dtb_region@9f200000 { + no-map; + reg = <0x0 0x9f200000 0x0 0x80000>; + }; + + q6_adsp_dtb_mem: q6_adsp_dtb_region@9f280000 { + no-map; + reg = <0x0 0x9f280000 0x0 0x80000>; + }; + + adspslpi_mem: adspslpi_region@9f300000 { + no-map; + reg = <0x0 0x9f300000 0x0 0x4080000>; + }; + + soccp_mem: soccp_region@a3380000 { + no-map; + reg = <0x0 0xa3380000 0x0 0x180000>; + }; + + wpss_mem: wpss_region@a3500000 { + no-map; + reg = <0x0 0xa3500000 0x0 0x1900000>; + }; + + wlan_msa_mem: wlan_msa_region@a6400000 { + no-map; + reg = <0x0 0xa6400000 0x0 0xc00000>; + }; + + /* uefi region can be reused by apps */ + + /* Linux kernel image is loaded at 0xa8000000 */ + + xbl_ramdump_mem: xbl_ramdump_region@b8000000 { + no-map; + reg = <0x0 0xb8000000 0x0 0x1c0000>; + }; + + /* merged tz_reserved, xbl_sc, and qtee regions */ + tz_merged_mem: tz_merged_region@d8000000 { + no-map; + reg = <0x0 0xd8000000 0x0 0x600000>; + }; + + /* + * ta/tags mem is dynamically removed from the RAM + * partition tables before boot occurs. Size of region + * varies. + */ + + llcc_lpi_mem: llcc_lpi_region@ff800000 { + no-map; + reg = <0x0 0xff800000 0x0 0x400000>; + }; + +}; diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 0036927e..d75b7787 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -212,6 +212,26 @@ }; }; +#include "kera-reserved-memory.dtsi" +#include "msm-arm-smmu-kera.dtsi" +#include "kera-dma-heaps.dtsi" + +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + system_cma: linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2000000>; + linux,cma-default; + }; +}; + &soc { #address-cells = <1>; #size-cells = <1>; @@ -383,6 +403,17 @@ wakeup-parent = <&pdc>; }; + tcsr_mutex_block: syscon@1f40000 { + compatible = "syscon"; + reg = <0x1f40000 0x20000>; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x1000>; + #hwlock-cells = <1>; + }; + ipcc_mproc: qcom,ipcc@406000 { compatible = "qcom,ipcc"; reg = <0x406000 0x1000>; @@ -392,6 +423,44 @@ #mbox-cells = <2>; }; + aoss_qmp: power-controller@c300000 { + compatible = "qcom,aoss-qmp"; + reg = <0xc300000 0x400>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_AOP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + qmp_aop: qcom,qmp-aop { + compatible = "qcom,qmp-mbox"; + qcom,qmp = <&aoss_qmp>; + label = "aop"; + #mbox-cells = <1>; + }; + + qmp_tme: qcom,qmp-tme { + compatible = "qcom,qmp-mbox"; + qcom,remote-pid = <14>; + mboxes = <&ipcc_mproc IPCC_CLIENT_TME + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "tme_qmp"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "tme"; + qcom,early-boot; + priority = <0>; + mbox-desc-offset = <0x0>; + #mbox-cells = <1>; + }; + cache-controller@24800000 { compatible = "qcom,kera-llcc"; reg = <0x24800000 0x200000>, <0x24C00000 0x200000>, diff --git a/qcom/monaco-wdp-v1.dtsi b/qcom/monaco-wdp-v1.dtsi index 85fb6846..9e397a3f 100644 --- a/qcom/monaco-wdp-v1.dtsi +++ b/qcom/monaco-wdp-v1.dtsi @@ -6,3 +6,43 @@ #include "monaco-idp-v1.dtsi" #include "monaco-thermal-wdp.dtsi" + + + + + + + + +&qupv3_se1_i2c { + status = "ok"; + + tsc@24 { + compatible = "parade,pt_i2c_adapter"; + reg = <0x24>; + status = "disabled"; + }; + + raydium_ts@39 { + compatible = "raydium,raydium-ts"; + reg = <0x39>; + status = "ok"; + interrupt-parent = <&tlmm>; + interrupts = <13 0x2008>; + vdd_ana-supply = <&L29A>; + vcc_i2c-supply = <&L21A>; + pinctrl-names = "pmx_ts_active","pmx_ts_suspend","pmx_ts_release"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&ts_release>; + raydium,reset-gpio = <&tlmm 12 0x00>; + raydium,irq-gpio = <&tlmm 13 0x00>; + raydium,num-max-touches = <2>; + raydium,soft-reset-delay-ms = <50>; + raydium,hard-reset-delay-ms = <100>; + raydium,x_max = <320>; + raydium,y_max = <360>; + raydium,display-coords= <0 0 320 360>; + }; +}; + diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 3dbc01e2..14e2b4b3 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -274,9 +274,7 @@ }; dump_mem: mem_dump_region { - compatible = "shared-dma-pool"; alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; size = <0 0x800000>; }; @@ -535,10 +533,6 @@ }; }; - dload_mode { - compatible = "qcom,dload-mode"; - }; - mini_dump_mode { compatible = "qcom,minidump"; status = "ok"; @@ -729,105 +723,110 @@ mem_dump { compatible = "qcom,mem-dump"; + memory-region = <&dump_mem>; - c0_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x0>; - }; + static_dump { + qcom,static-mem-dump; - c1_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x1>; - }; + c0_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x0>; + }; - c2_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x2>; - }; + c1_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x1>; + }; - c3_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x3>; - }; + c2_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x2>; + }; - l1_icache0 { - qcom,dump-size = <0x9040>; - qcom,dump-id = <0x60>; - }; + c3_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x3>; + }; - l1_icache1 { - qcom,dump-size = <0x9040>; - qcom,dump-id = <0x61>; - }; + l1_icache0 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x60>; + }; - l1_icache2 { - qcom,dump-size = <0x9040>; - qcom,dump-id = <0x62>; - }; + l1_icache1 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x61>; + }; - l1_icache3 { - qcom,dump-size = <0x9040>; - qcom,dump-id = <0x63>; - }; + l1_icache2 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x62>; + }; - l1_dcache0 { - qcom,dump-size = <0x9040>; - qcom,dump-id = <0x80>; - }; + l1_icache3 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x63>; + }; - l1_dcache1 { - qcom,dump-size = <0x9040>; - qcom,dump-id = <0x81>; - }; + l1_dcache0 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x80>; + }; - l1_dcache2 { - qcom,dump-size = <0x9040>; - qcom,dump-id = <0x82>; - }; + l1_dcache1 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x81>; + }; - l1_dcache3 { - qcom,dump-size = <0x9040>; - qcom,dump-id = <0x83>; - }; + l1_dcache2 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x82>; + }; - l2_tlb0 { - qcom,dump-size = <0x2000>; - qcom,dump-id = <0x120>; - }; + l1_dcache3 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x83>; + }; - l2_tlb1 { - qcom,dump-size = <0x2000>; - qcom,dump-id = <0x121>; - }; + l2_tlb0 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x120>; + }; - l2_tlb2 { - qcom,dump-size = <0x2000>; - qcom,dump-id = <0x122>; - }; + l2_tlb1 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x121>; + }; - l2_tlb3 { - qcom,dump-size = <0x2000>; - qcom,dump-id = <0x123>; - }; + l2_tlb2 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x122>; + }; - pmic { - qcom,dump-size = <0x200000>; - qcom,dump-id = <0xe4>; - }; + l2_tlb3 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x123>; + }; - tmc_etf { - qcom,dump-size = <0x8000>; - qcom,dump-id = <0xf0>; - }; + pmic { + qcom,dump-size = <0x200000>; + qcom,dump-id = <0xe4>; + }; - etr_reg { - qcom,dump-size = <0x1000>; - qcom,dump-id = <0x100>; - }; + tmc_etf { + qcom,dump-size = <0x8000>; + qcom,dump-id = <0xf0>; + }; - etf_reg { - qcom,dump-size = <0x1000>; - qcom,dump-id = <0x101>; + etr_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x100>; + }; + + etf_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x101>; + }; }; }; @@ -1144,7 +1143,7 @@ }; qcom,cpufreq-hw-debug@f521000 { - /* compatible = "qcom,cpufreq-hw-debug"; */ + compatible = "qcom,cpufreq-hw-debug"; reg = <0xf521000 0x1400>; reg-names = "domain-top"; qcom,freq-hw-domain = <&cpufreq_hw 0>; diff --git a/qcom/msm-arm-smmu-kera.dtsi b/qcom/msm-arm-smmu-kera.dtsi new file mode 100644 index 00000000..a18d50fe --- /dev/null +++ b/qcom/msm-arm-smmu-kera.dtsi @@ -0,0 +1,300 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + kgsl_smmu: kgsl-smmu@3da0000 { + compatible = "qcom,qsmmu-v500", "qcom,adreno-smmu"; + reg = <0x3da0000 0x40000>; + #iommu-cells = <2>; + qcom,use-3-lvl-tables; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + dma-coherent; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + gpu_qtb: gpu_qtb@03de8000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x3de8000 0x1000>; + qcom,stream-id-range = <0x0 0x400>; + qcom,iova-width = <49>; + qcom,num-qtb-ports = <2>; + }; + }; + + apps_smmu: apps-smmu@15000000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15000000 0x100000>; + #iommu-cells = <2>; + qcom,use-3-lvl-tables; + qcom,handoff-smrs = <0x800 0x2>; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + dma-coherent; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + anoc_1_qtb: anoc_1_qtb@16f2000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x16f2000 0x1000>; + qcom,stream-id-range = <0x0 0x400>; + qcom,iova-width = <36>; + qcom,num-qtb-ports = <1>; + }; + + anoc_2_qtb: anoc_2_qtb@171b000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x171b000 0x1000>; + qcom,stream-id-range = <0x400 0x400>; + qcom,iova-width = <36>; + qcom,num-qtb-ports = <1>; + }; + + cam_hf_qtb: cam_hf_qtb@17f7000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x17f7000 0x1000>; + qcom,stream-id-range = <0x1c00 0x400>; + qcom,iova-width = <32>; + qcom,num-qtb-ports = <2>; + }; + + nsp_qtb: nsp_qtb@7d3000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x7d3000 0x1000>; + qcom,stream-id-range = <0xc00 0x400>; + qcom,iova-width = <32>; + qcom,num-qtb-ports = <2>; + }; + + lpass_qtb: lpass_qtb@7b3000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x7b3000 0x1000>; + qcom,stream-id-range = <0x1000 0x400>; + qcom,iova-width = <32>; + qcom,num-qtb-ports = <1>; + }; + + pcie_qtb: pcie_qtb@16cd000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x16cd000 0x1000>; + qcom,stream-id-range = <0x1400 0x400>; + qcom,iova-width = <32>; + qcom,num-qtb-ports = <1>; + qcom,opt-out-tbu-halting; + }; + + sf_qtb: sf_qtb@17b7000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x17b7000 0x1000>; + qcom,stream-id-range = <0x1800 0x400>; + qcom,iova-width = <32>; + qcom,num-qtb-ports = <2>; + }; + + mdp_hf_qtb: mdp_hf_qtb@17f6000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x17f6000 0x1000>; + qcom,stream-id-range = <0x800 0x400>; + qcom,iova-width = <36>; + qcom,num-qtb-ports = <2>; + }; + + }; + + dma_dev { + compatible = "qcom,iommu-dma"; + memory-region = <&system_cma>; + }; + + iommu_test_device { + compatible = "qcom,iommu-debug-test"; + #address-cells = <2>; + #size-cells = <2>; + + usecase0_apps { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x400 0x0>; + }; + + usecase1_apps_fastmap { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x400 0x0>; + qcom,iommu-dma = "fastmap"; + }; + + usecase2_apps_atomic { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x400 0x0>; + qcom,iommu-dma = "atomic"; + }; + + usecase3_apps_dma { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x400 0x0>; + dma-coherent; + }; + + usecase4_apps_secure { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x400 0x0>; + qcom,iommu-vmid = <0xa>; /* VMID_CP_PIXEL */ + }; + + usecase5_kgsl { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&kgsl_smmu 0x7 0x0>; + }; + + usecase6_kgsl_dma { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&kgsl_smmu 0x7 0x0>; + dma-coherent; + }; + }; + +}; diff --git a/qcom/msm-arm-smmu-ravelin.dtsi b/qcom/msm-arm-smmu-ravelin.dtsi index 9a306b02..84e6e1b4 100644 --- a/qcom/msm-arm-smmu-ravelin.dtsi +++ b/qcom/msm-arm-smmu-ravelin.dtsi @@ -374,7 +374,6 @@ usecase7_apps_secure { compatible = "qcom,iommu-debug-usecase"; iommus = <&apps_smmu 0x7e0 0>; - qcom,iommu-dma = "atomic"; qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */ }; }; diff --git a/qcom/msm-arm-smmu-sdxkova.dtsi b/qcom/msm-arm-smmu-sdxkova.dtsi new file mode 100644 index 00000000..66732ae4 --- /dev/null +++ b/qcom/msm-arm-smmu-sdxkova.dtsi @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + apps_smmu: apps-smmu@15000000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15000000 0x40000>; + #iommu-cells = <2>; + qcom,use-3-lvl-tables; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + dma-coherent; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + anoc_1_qtb: anoc_1_qtb@1680000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x1680000 0x1000>; + qcom,stream-id-range = <0x0 0x400>; + qcom,iova-width = <36>; + qcom,num-qtb-ports = <1>; + }; + + ipa_qtb: ipa_qtb@1688000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x1688000 0x1000>; + qcom,stream-id-range = <0x400 0x400>; + qcom,iova-width = <41>; + qcom,num-qtb-ports = <1>; + }; + + pcie_qtb: pcie_qtb@16d0000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x16d0000 0x1000>; + qcom,stream-id-range = <0x800 0x400>; + qcom,iova-width = <36>; + qcom,num-qtb-ports = <1>; + qcom,opt-out-tbu-halting; + }; + }; + + dma_dev { + compatible = "qcom,iommu-dma"; + memory-region = <&system_cma>; + }; + + iommu_test_device { + compatible = "qcom,iommu-debug-test"; + + usecase0_apps { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x3e0 0x0>; + }; + + usecase1_apps_fastmap { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x3e0 0x0>; + qcom,iommu-dma = "fastmap"; + }; + + usecase2_apps_atomic { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x3e0 0x0>; + qcom,iommu-dma = "atomic"; + }; + + usecase3_apps_dma { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x3e0 0x0>; + dma-coherent; + }; + + usecase4_apps_secure { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x3e0 0x0>; + qcom,iommu-vmid = <0x2d>; /* VMID_TUIVM */ + }; + }; +}; diff --git a/qcom/parrot-usb.dtsi b/qcom/parrot-usb.dtsi index 93856c1f..1bcd000e 100644 --- a/qcom/parrot-usb.dtsi +++ b/qcom/parrot-usb.dtsi @@ -79,6 +79,7 @@ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; tx-fifo-resize; + num-hc-interrupters = /bits/ 16 <3>; dr_mode = "peripheral"; maximum-speed = "super-speed"; }; diff --git a/qcom/parrot.dtsi b/qcom/parrot.dtsi index f006351c..aeebe139 100644 --- a/qcom/parrot.dtsi +++ b/qcom/parrot.dtsi @@ -29,7 +29,7 @@ chosen: chosen { stdout-path = "/soc/qcom,qup_uart@98c000:115200n8"; - bootargs = "console=ttyMSM0,115200n8 loglevel=6 log_buf_len=256K kernel.panic_on_rcu_stall=1 loop.max_part=7 pcie_ports=compat allow_mismatched_32bit_el0 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 ftrace_dump_on_oops pstore.compress=none kpti=0 swiotlb=noforce cgroup.memory=nokmem,nosocket kswapd_per_node=2 slub_debug=- allow_file_spec_access cpufreq.default_governor=performance transparent_hugepage=never page_poison=on can.stats_timer=0 disable_dma32=on android12_only.will_be_removed_soon.memblock_nomap_remove=on"; + bootargs = "loglevel=6 log_buf_len=256K kernel.panic_on_rcu_stall=1 loop.max_part=7 pcie_ports=compat allow_mismatched_32bit_el0 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 ftrace_dump_on_oops pstore.compress=none kpti=0 swiotlb=noforce cgroup.memory=nokmem,nosocket kswapd_per_node=2 slub_debug=- allow_file_spec_access cpufreq.default_governor=performance transparent_hugepage=never page_poison=on can.stats_timer=0 disable_dma32=on android12_only.will_be_removed_soon.memblock_nomap_remove=on"; }; memory { device_type = "memory"; reg = <0 0 0 0>; }; @@ -45,6 +45,7 @@ <0x2 0xc0000000 0x1 0x40000000>; granule = <512>; mboxes = <&qmp_aop 0>; + status = "disabled"; }; aliases: aliases { @@ -2037,6 +2038,7 @@ qcom,mem-buf-msgq { compatible = "qcom,mem-buf-msgq"; + qcom,msgq-names = "trusted_vm"; }; trust_ui_vm: qcom,trust_ui_vm@e55fc000 { diff --git a/qcom/pineapple.dtsi b/qcom/pineapple.dtsi index 394325b8..de39ea3a 100644 --- a/qcom/pineapple.dtsi +++ b/qcom/pineapple.dtsi @@ -2389,9 +2389,9 @@ gic-interrupt-router { compatible = "qcom,gic-intr-routing"; /* keep silver core only to avoid wakeup of gold cores */ - qcom,gic-class0-cpus = <0 1>; + qcom,gic-class0-cpus = <&CPU0 &CPU1>; /* keep gold and gold+ cores in class1 */ - qcom,gic-class1-cpus = <2 3 4 5 6 7>; + qcom,gic-class1-cpus = <&CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7>; }; qcom,secure-buffer { diff --git a/qcom/platform_map.bzl b/qcom/platform_map.bzl index 19a77d53..e31044d2 100644 --- a/qcom/platform_map.bzl +++ b/qcom/platform_map.bzl @@ -42,6 +42,7 @@ _platform_map = { {"name": "sun-cdp-no-display-overlay.dtbo"}, {"name": "sun-cdp-overlay.dtbo"}, {"name": "sun-cdp-v8-overlay.dtbo"}, + {"name": "sun-mtp-3.5mm-kiwi-v8-overlay.dtbo"}, {"name": "sun-mtp-3.5mm-overlay.dtbo"}, {"name": "sun-mtp-kiwi-overlay.dtbo"}, {"name": "sun-mtp-kiwi-v8-overlay.dtbo"}, @@ -205,6 +206,8 @@ _platform_map = { {"name": "ravelinp.dtb"}, {"name": "ravelin-4gb.dtb"}, {"name": "ravelinp-4gb.dtb"}, + {"name": "ravelin-sg.dtb"}, + {"name": "ravelinp-sg.dtb"}, ], "dtbo_list": [ # keep sorted diff --git a/qcom/pm5100.dtsi b/qcom/pm5100.dtsi index 3d303c4c..12bdc630 100644 --- a/qcom/pm5100.dtsi +++ b/qcom/pm5100.dtsi @@ -24,7 +24,7 @@ #size-cells = <0>; pon_hlos@1300 { - /* compatible = "qcom,qpnp-power-on"; */ + compatible = "qcom,qpnp-power-on"; reg = <0x1300>; interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>, <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>; @@ -42,7 +42,7 @@ }; pm5100_charger: qcom,qpnp-smblite { - /* compatible = "qcom,qpnp-pm5100-smblite"; */ + compatible = "qcom,qpnp-pm5100-smblite"; #address-cells = <1>; #size-cells = <1>; #cooling-cells = <2>; @@ -240,7 +240,7 @@ }; pm5100_gpios: pinctrl@8800 { - /* compatible = "qcom,pm5100-gpio"; */ + compatible = "qcom,pm5100-gpio"; reg = <0x8800>; gpio-controller; #gpio-cells = <2>; @@ -249,14 +249,14 @@ }; pm5100_rtc: rtc@6400 { - /* compatible = "qcom,pm5100-rtc"; */ + compatible = "qcom,pm5100-rtc"; reg = <0x6400>, <0x6500>; reg-names = "rtc", "alarm"; interrupts = <0x0 0x65 0x1 IRQ_TYPE_EDGE_RISING>; }; pm5100_cdc: qcom,pm5100-cdc { - /* compatible = "qcom,pm5100-spmi"; */ + compatible = "qcom,pm5100-spmi"; }; pm5100_bcl: bcl@4700 { @@ -344,7 +344,7 @@ pm5100_qbg: qpnp,qbg@4f00 { status = "disabled"; - /* compatible = "qcom,qbg"; */ + compatible = "qcom,qbg"; #address-cells = <1>; reg = <0x4f00>; interrupt-names = "qbg-sdam", "qbg-vbatt-empty"; diff --git a/qcom/pmk8550.dtsi b/qcom/pmk8550.dtsi index 866dc1ea..21ddcae1 100644 --- a/qcom/pmk8550.dtsi +++ b/qcom/pmk8550.dtsi @@ -57,6 +57,14 @@ fmd_set: fmd-set@9a { reg = <0x9a 0x1>; }; + + fmd_chg_pon: fmd-chg-pon@9f { + reg = <0x9f 0x1>; + }; + + fmd_cnt2_stop: fmd-cnt2-stop@a2 { + reg = <0xa2 0x1>; + }; }; pmk8550_sdam_5: sdam@7400 { diff --git a/qcom/ravelin-atp-overlay.dts b/qcom/ravelin-atp-overlay.dts index 7ea7d64b..afffb52e 100644 --- a/qcom/ravelin-atp-overlay.dts +++ b/qcom/ravelin-atp-overlay.dts @@ -11,6 +11,6 @@ / { model = "Qualcomm Technologies, Inc. Ravelin ATP"; compatible = "qcom,ravelin-atp", "qcom,ravelin", "qcom,atp"; - qcom,msm-id = <568 0x10000>, <602 0x10000>; + qcom,msm-id = <568 0x10000>, <602 0x10000>, <653 0x10000>, <654 0x10000>; qcom,board-id = <33 0>; }; diff --git a/qcom/ravelin-idp-overlay.dts b/qcom/ravelin-idp-overlay.dts index e46b8a1e..e888ce71 100644 --- a/qcom/ravelin-idp-overlay.dts +++ b/qcom/ravelin-idp-overlay.dts @@ -11,6 +11,6 @@ / { model = "Qualcomm Technologies, Inc. Ravelin IDP"; compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp"; - qcom,msm-id = <568 0x10000>, <602 0x10000>; + qcom,msm-id = <568 0x10000>, <602 0x10000>, <653 0x10000>, <654 0x10000>; qcom,board-id = <34 0>; }; diff --git a/qcom/ravelin-idp-wcn3950-amoled-rcm-overlay.dts b/qcom/ravelin-idp-wcn3950-amoled-rcm-overlay.dts index 8f917453..41248f2a 100644 --- a/qcom/ravelin-idp-wcn3950-amoled-rcm-overlay.dts +++ b/qcom/ravelin-idp-wcn3950-amoled-rcm-overlay.dts @@ -11,6 +11,6 @@ / { model = "Qualcomm Technologies, Inc. Ravelin WCN3950 IDP + AMOLED + RCM"; compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp"; - qcom,msm-id = <568 0x10000>, <602 0x10000>; + qcom,msm-id = <568 0x10000>, <602 0x10000>, <653 0x10000>, <654 0x10000>; qcom,board-id = <34 2>; }; diff --git a/qcom/ravelin-idp-wcn3988-4gb-overlay.dts b/qcom/ravelin-idp-wcn3988-4gb-overlay.dts index cc8bf2e9..8402b692 100644 --- a/qcom/ravelin-idp-wcn3988-4gb-overlay.dts +++ b/qcom/ravelin-idp-wcn3988-4gb-overlay.dts @@ -11,6 +11,6 @@ / { model = "Qualcomm Technologies, Inc. Ravelin IDP 4GB DDR + WCN3988"; compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp"; - qcom,msm-id = <568 0x10000>, <602 0x10000>; + qcom,msm-id = <568 0x10000>, <602 0x10000>, <653 0x10000>, <654 0x10000>; qcom,board-id = <34 0x601>; }; diff --git a/qcom/ravelin-pmic-overlay.dtsi b/qcom/ravelin-pmic-overlay.dtsi index 1f90df0f..915a1d83 100644 --- a/qcom/ravelin-pmic-overlay.dtsi +++ b/qcom/ravelin-pmic-overlay.dtsi @@ -483,16 +483,13 @@ pinctrl-0 = <&pm8010m_active>; pm8010-chip@900 { + compatible = "qcom,pm8008-chip"; reg = <0x900>; PM8010M_EN: qcom,pm8008-chip-en { regulator-name = "pm8010m-chip-en"; }; }; - - qcom,revid@100 { - reg = <0x100>; - }; }; pm8010m@9 { @@ -502,6 +499,7 @@ #size-cells = <0>; qcom,pm8010m-regulator { + compatible = "qcom,pm8010-regulator"; #address-cells = <1>; #size-cells = <0>; @@ -570,16 +568,13 @@ pinctrl-0 = <&pm8010n_active>; pm8010-chip@900 { + compatible = "qcom,pm8008-chip"; reg = <0x900>; PM8010N_EN: qcom,pm8008-chip-en { regulator-name = "pm8010n-chip-en"; }; }; - - qcom,revid@100 { - reg = <0x100>; - }; }; pm8010n@d { @@ -589,6 +584,7 @@ #size-cells = <0>; qcom,pm8010n-regulator { + compatible = "qcom,pm8010-regulator"; #address-cells = <1>; #size-cells = <0>; diff --git a/qcom/ravelin-qrd-4gb-overlay.dts b/qcom/ravelin-qrd-4gb-overlay.dts index ea38d8c4..0909b4cc 100644 --- a/qcom/ravelin-qrd-4gb-overlay.dts +++ b/qcom/ravelin-qrd-4gb-overlay.dts @@ -11,6 +11,6 @@ / { model = "Qualcomm Technologies, Inc. Ravelin QRD 4GB DDR"; compatible = "qcom,ravelin-qrd", "qcom,ravelin", "qcom,qrd"; - qcom,msm-id = <568 0x10000>, <602 0x10000>; + qcom,msm-id = <568 0x10000>, <602 0x10000>, <653 0x10000>, <654 0x10000>; qcom,board-id = <0x1000B 0x600>; }; diff --git a/qcom/ravelin-qrd-overlay.dts b/qcom/ravelin-qrd-overlay.dts index 5de8fb12..762a33d2 100644 --- a/qcom/ravelin-qrd-overlay.dts +++ b/qcom/ravelin-qrd-overlay.dts @@ -11,7 +11,8 @@ / { model = "Qualcomm Technologies, Inc. Ravelin QRD"; compatible = "qcom,ravelin-qrd", "qcom,ravelin", "qcom,qrd"; - qcom,msm-id = <568 0x10000>, <602 0x10000>, <581 0x10000>, <582 0x10000>; + qcom,msm-id = <568 0x10000>, <602 0x10000>, <581 0x10000>, <582 0x10000>, + <653 0x10000>, <654 0x10000>; qcom,board-id = <0x1000B 0>; }; diff --git a/qcom/ravelin-qupv3.dtsi b/qcom/ravelin-qupv3.dtsi index d4e78382..cd4af450 100644 --- a/qcom/ravelin-qupv3.dtsi +++ b/qcom/ravelin-qupv3.dtsi @@ -77,7 +77,7 @@ reg-names = "se_phys"; interrupts-extended = <&intc GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, <&tlmm 17 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "se"; + clock-names = "se-clk"; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = @@ -103,7 +103,7 @@ reg = <0x980000 0x4000>; reg-names = "se_phys"; interrupts = ; - interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, @@ -122,7 +122,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = ; - interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, @@ -143,7 +143,7 @@ reg = <0x984000 0x4000>; #address-cells = <1>; #size-cells = <0>; - interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, @@ -167,7 +167,7 @@ #size-cells = <0>; reg-names = "se_phys"; interrupts = ; - interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, @@ -190,7 +190,7 @@ reg = <0x98c000 0x4000>; #address-cells = <1>; #size-cells = <0>; - interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, @@ -214,7 +214,7 @@ #size-cells = <0>; reg-names = "se_phys"; interrupts = ; - interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, @@ -238,7 +238,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = ; - interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, @@ -261,7 +261,7 @@ #size-cells = <0>; reg-names = "se_phys"; interrupts = ; - interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, @@ -350,7 +350,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = ; - interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, @@ -373,7 +373,7 @@ #size-cells = <0>; reg-names = "se_phys"; interrupts = ; - interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, @@ -397,7 +397,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = ; - interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, @@ -420,7 +420,7 @@ #size-cells = <0>; reg-names = "se_phys"; interrupts = ; - interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, @@ -444,7 +444,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = ; - interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, @@ -468,7 +468,7 @@ #size-cells = <0>; reg-names = "se_phys"; interrupts = ; - interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, @@ -492,7 +492,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = ; - interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, @@ -515,7 +515,7 @@ #size-cells = <0>; reg-names = "se_phys"; interrupts = ; - interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, diff --git a/qcom/ravelin-sg-atp.dts b/qcom/ravelin-sg-atp.dts new file mode 100644 index 00000000..95dec91a --- /dev/null +++ b/qcom/ravelin-sg-atp.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelin-sg.dtsi" +#include "ravelin-sg-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin SG ATP"; + compatible = "qcom,ravelin-atp", "qcom,ravelin", "qcom,atp"; + qcom,board-id = <33 0>; +}; + diff --git a/qcom/ravelin-sg-atp.dtsi b/qcom/ravelin-sg-atp.dtsi new file mode 100644 index 00000000..1a4b89e5 --- /dev/null +++ b/qcom/ravelin-sg-atp.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-atp.dtsi" diff --git a/qcom/ravelin-sg-idp-wcn3950-amoled-rcm.dts b/qcom/ravelin-sg-idp-wcn3950-amoled-rcm.dts new file mode 100644 index 00000000..4026ad8d --- /dev/null +++ b/qcom/ravelin-sg-idp-wcn3950-amoled-rcm.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelin-sg.dtsi" +#include "ravelin-sg-idp-wcn3950-amoled-rcm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin SG WCN3950 IDP + AMOLED + RCM"; + compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp"; + qcom,board-id = <34 2>; +}; diff --git a/qcom/ravelin-sg-idp-wcn3950-amoled-rcm.dtsi b/qcom/ravelin-sg-idp-wcn3950-amoled-rcm.dtsi new file mode 100644 index 00000000..787f9e04 --- /dev/null +++ b/qcom/ravelin-sg-idp-wcn3950-amoled-rcm.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-idp-wcn3950-amoled-rcm.dtsi" + diff --git a/qcom/ravelin-sg-idp-wcn3988-4gb.dts b/qcom/ravelin-sg-idp-wcn3988-4gb.dts new file mode 100644 index 00000000..362958cc --- /dev/null +++ b/qcom/ravelin-sg-idp-wcn3988-4gb.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelin-4gb.dtsi" +#include "ravelin-sg-idp-wcn3988-4gb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin SG IDP 4GB DDR + WCN3988"; + compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp"; + qcom,board-id = <34 0x601>; +}; diff --git a/qcom/ravelin-sg-idp-wcn3988-4gb.dtsi b/qcom/ravelin-sg-idp-wcn3988-4gb.dtsi new file mode 100644 index 00000000..b3eb3adb --- /dev/null +++ b/qcom/ravelin-sg-idp-wcn3988-4gb.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-idp-wcn3988-4gb.dtsi" diff --git a/qcom/ravelin-sg-idp.dts b/qcom/ravelin-sg-idp.dts new file mode 100644 index 00000000..381cdcca --- /dev/null +++ b/qcom/ravelin-sg-idp.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelin-sg.dtsi" +#include "ravelin-sg-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin SG IDP"; + compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp"; + qcom,board-id = <34 0>; +}; + diff --git a/qcom/ravelin-sg-idp.dtsi b/qcom/ravelin-sg-idp.dtsi new file mode 100644 index 00000000..122b06c7 --- /dev/null +++ b/qcom/ravelin-sg-idp.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-idp.dtsi" diff --git a/qcom/ravelin-sg-qrd-4gb.dts b/qcom/ravelin-sg-qrd-4gb.dts new file mode 100644 index 00000000..ce83076c --- /dev/null +++ b/qcom/ravelin-sg-qrd-4gb.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelin-4gb.dtsi" +#include "ravelin-sg-qrd-4gb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin SG QRD 4GB DDR"; + compatible = "qcom,ravelin-qrd", "qcom,ravelin", "qcom,qrd"; + qcom,board-id = <0x1000B 0x600>; +}; + diff --git a/qcom/ravelin-sg-qrd-4gb.dtsi b/qcom/ravelin-sg-qrd-4gb.dtsi new file mode 100644 index 00000000..4b5b6f61 --- /dev/null +++ b/qcom/ravelin-sg-qrd-4gb.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-qrd-4gb.dtsi" + diff --git a/qcom/ravelin-sg-qrd.dts b/qcom/ravelin-sg-qrd.dts new file mode 100644 index 00000000..d52cdc6c --- /dev/null +++ b/qcom/ravelin-sg-qrd.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelin-sg.dtsi" +#include "ravelin-sg-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin SG QRD"; + compatible = "qcom,ravelin-qrd", "qcom,ravelin", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; +}; + + diff --git a/qcom/ravelin-sg-qrd.dtsi b/qcom/ravelin-sg-qrd.dtsi new file mode 100644 index 00000000..c0e0c1bc --- /dev/null +++ b/qcom/ravelin-sg-qrd.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-qrd.dtsi" diff --git a/qcom/ravelin-sg.dts b/qcom/ravelin-sg.dts new file mode 100644 index 00000000..a851c7a8 --- /dev/null +++ b/qcom/ravelin-sg.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelin-sg.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin SG SoC"; + compatible = "qcom,ravelin"; + qcom,board-id = <0 0>; +}; + diff --git a/qcom/ravelin-sg.dtsi b/qcom/ravelin-sg.dtsi new file mode 100644 index 00000000..0981fc84 --- /dev/null +++ b/qcom/ravelin-sg.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin.dtsi" + +/ { + + model = "Qualcomm Technologies, Inc. Ravelin SG"; + compatible = "qcom,ravelin"; + qcom,msm-id = <653 0x10000>; +}; diff --git a/qcom/ravelin.dtsi b/qcom/ravelin.dtsi index 813f3c80..97de0d85 100644 --- a/qcom/ravelin.dtsi +++ b/qcom/ravelin.dtsi @@ -28,7 +28,7 @@ chosen: chosen { stdout-path = "/soc/qcom,qup_uart@a88000:115200n8"; - bootargs = "console=ttyMSM0,115200n8 loglevel=6 log_buf_len=256K kernel.panic_on_rcu_stall=1 loop.max_part=7 pcie_ports=compat kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 ftrace_dump_on_oops pstore.compress=none kpti=0 swiotlb=noforce cgroup.memory=nokmem,nosocket kswapd_per_node=2 slub_debug=- allow_file_spec_access cpufreq.default_governor=performance transparent_hugepage=never can.stats_timer=0 disable_dma32=on android12_only.will_be_removed_soon.memblock_nomap_remove=on pcie_ports=compat"; + bootargs = "loglevel=6 log_buf_len=256K kernel.panic_on_rcu_stall=1 loop.max_part=7 pcie_ports=compat kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 ftrace_dump_on_oops pstore.compress=none kpti=0 swiotlb=noforce cgroup.memory=nokmem,nosocket kswapd_per_node=2 slub_debug=- allow_file_spec_access cpufreq.default_governor=performance transparent_hugepage=never can.stats_timer=0 disable_dma32=on android12_only.will_be_removed_soon.memblock_nomap_remove=on pcie_ports=compat"; }; memory { device_type = "memory"; reg = <0 0 0 0>; }; @@ -44,6 +44,7 @@ <0x2 0xc0000000 0x1 0x40000000>; granule = <512>; mboxes = <&qmp_aop 0>; + status = "disabled"; }; aliases: aliases { @@ -806,6 +807,7 @@ qcom,mem-buf-msgq { compatible = "qcom,mem-buf-msgq"; + qcom,msgq-names = "trusted_vm"; }; qcom,rmtfs_sharedmem@0 { @@ -826,6 +828,7 @@ }; qcom_qseecom: qseecom@c1700000 { + compatible = "qcom,qseecom"; memory-region = <&qseecom_mem>; qseecom_mem = <&qseecom_mem>; qseecom_ta_mem = <&qseecom_ta_mem>; @@ -1081,6 +1084,17 @@ #interrupt-cells = <2>; }; + smp2p_ipa_1_out: qcom,smp2p-ipa-1-out { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + /* ipa - inbound entry from mss */ + smp2p_ipa_1_in: qcom,smp2p-ipa-1-in { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; }; qcom,smp2p-adsp { @@ -1291,6 +1305,13 @@ }; }; + qcom_rng: qrng@10c3000 { + compatible = "qcom,msm-rng"; + reg = <0x10c3000 0x1000>; + qcom,no-qrng-config; + qcom,no-clock-support; + }; + ufsphy_mem: ufsphy_mem@1d87000 { reg = <0x1d87000 0xe10>; reg-names = "phy_mem"; @@ -1317,14 +1338,14 @@ ufshc_mem: ufshc@1d84000 { compatible = "qcom,ufshc"; reg = <0x1d84000 0x3000>, - <0x1d88000 0x8000>, - <0x1d90000 0x9000>; - reg-names = "ufs_mem", "ufs_ice", "ufs_ice_hwkm"; + <0x1d88000 0x18000>; + reg-names = "ufs_mem", "ice"; interrupts = ; phys = <&ufsphy_mem>; phy-names = "ufsphy"; #reset-cells = <1>; + qcom,ice-use-hwkm; lanes-per-direction = <2>; dev-ref-clk-freq = <0>; /* 19.2 MHz */ clock-names = diff --git a/qcom/ravelinp-sg-atp.dts b/qcom/ravelinp-sg-atp.dts new file mode 100644 index 00000000..0b8a551f --- /dev/null +++ b/qcom/ravelinp-sg-atp.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelinp-sg.dtsi" +#include "ravelinp-sg-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. RavelinP SG ATP"; + compatible = "qcom,ravelinp-atp", "qcom,ravelinp", "qcom,atp"; + qcom,board-id = <33 0>; +}; + diff --git a/qcom/ravelinp-sg-atp.dtsi b/qcom/ravelinp-sg-atp.dtsi new file mode 100644 index 00000000..ebb9b984 --- /dev/null +++ b/qcom/ravelinp-sg-atp.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-sg-atp.dtsi" diff --git a/qcom/ravelinp-sg-idp-wcn3950-amoled-rcm.dts b/qcom/ravelinp-sg-idp-wcn3950-amoled-rcm.dts new file mode 100644 index 00000000..8c27ce5f --- /dev/null +++ b/qcom/ravelinp-sg-idp-wcn3950-amoled-rcm.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelinp-sg.dtsi" +#include "ravelinp-sg-idp-wcn3950-amoled-rcm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. RavelinP SG WCN3950 IDP + AMOLED + RCM"; + compatible = "qcom,ravelinp-idp", "qcom,ravelinp", "qcom,idp"; + qcom,board-id = <34 2>; +}; diff --git a/qcom/ravelinp-sg-idp-wcn3950-amoled-rcm.dtsi b/qcom/ravelinp-sg-idp-wcn3950-amoled-rcm.dtsi new file mode 100644 index 00000000..dbc926c2 --- /dev/null +++ b/qcom/ravelinp-sg-idp-wcn3950-amoled-rcm.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-sg-idp-wcn3950-amoled-rcm.dtsi" + diff --git a/qcom/ravelinp-sg-idp-wcn3988-4gb.dts b/qcom/ravelinp-sg-idp-wcn3988-4gb.dts new file mode 100644 index 00000000..26e344ca --- /dev/null +++ b/qcom/ravelinp-sg-idp-wcn3988-4gb.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelinp-4gb.dtsi" +#include "ravelinp-sg-idp-wcn3988-4gb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. RavelinP SG IDP 4GB DDR + WCN3988"; + compatible = "qcom,ravelinp-idp", "qcom,ravelinp", "qcom,idp"; + qcom,board-id = <34 0x601>; +}; diff --git a/qcom/ravelinp-sg-idp-wcn3988-4gb.dtsi b/qcom/ravelinp-sg-idp-wcn3988-4gb.dtsi new file mode 100644 index 00000000..c4d7b514 --- /dev/null +++ b/qcom/ravelinp-sg-idp-wcn3988-4gb.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-sg-idp-wcn3988-4gb.dtsi" diff --git a/qcom/ravelinp-sg-idp.dts b/qcom/ravelinp-sg-idp.dts new file mode 100644 index 00000000..33902723 --- /dev/null +++ b/qcom/ravelinp-sg-idp.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelinp-sg.dtsi" +#include "ravelinp-sg-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. RavelinP SG IDP"; + compatible = "qcom,ravelinp-idp", "qcom,ravelinp", "qcom,idp"; + qcom,board-id = <34 0>; +}; + diff --git a/qcom/ravelinp-sg-idp.dtsi b/qcom/ravelinp-sg-idp.dtsi new file mode 100644 index 00000000..d1626b92 --- /dev/null +++ b/qcom/ravelinp-sg-idp.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-sg-idp.dtsi" diff --git a/qcom/ravelinp-sg-qrd-4gb.dts b/qcom/ravelinp-sg-qrd-4gb.dts new file mode 100644 index 00000000..02ed7743 --- /dev/null +++ b/qcom/ravelinp-sg-qrd-4gb.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelinp-4gb.dtsi" +#include "ravelinp-sg-qrd-4gb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. RavelinP SG QRD 4GB DDR"; + compatible = "qcom,ravelinp-qrd", "qcom,ravelinp", "qcom,qrd"; + qcom,board-id = <0x1000B 0x600>; +}; + diff --git a/qcom/ravelinp-sg-qrd-4gb.dtsi b/qcom/ravelinp-sg-qrd-4gb.dtsi new file mode 100644 index 00000000..0245ec57 --- /dev/null +++ b/qcom/ravelinp-sg-qrd-4gb.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-sg-qrd-4gb.dtsi" + diff --git a/qcom/ravelinp-sg-qrd.dts b/qcom/ravelinp-sg-qrd.dts new file mode 100644 index 00000000..fb97f8b3 --- /dev/null +++ b/qcom/ravelinp-sg-qrd.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelinp-sg.dtsi" +#include "ravelinp-sg-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. RavelinP SG QRD"; + compatible = "qcom,ravelinp-qrd", "qcom,ravelinp", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; +}; + + diff --git a/qcom/ravelinp-sg-qrd.dtsi b/qcom/ravelinp-sg-qrd.dtsi new file mode 100644 index 00000000..e7fa0492 --- /dev/null +++ b/qcom/ravelinp-sg-qrd.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-sg-qrd.dtsi" diff --git a/qcom/ravelinp-sg.dts b/qcom/ravelinp-sg.dts new file mode 100644 index 00000000..3ee5eceb --- /dev/null +++ b/qcom/ravelinp-sg.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelinp-sg.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. RavelinP SG SoC"; + compatible = "qcom,ravelinp"; + qcom,board-id = <0 0>; +}; + diff --git a/qcom/ravelinp-sg.dtsi b/qcom/ravelinp-sg.dtsi new file mode 100644 index 00000000..66a40c4c --- /dev/null +++ b/qcom/ravelinp-sg.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-sg.dtsi" + +/ { + + model = "Qualcomm Technologies, Inc. RavelinP SG"; + compatible = "qcom,ravelinp"; + qcom,msm-id = <654 0x10000>; +}; diff --git a/qcom/sdxkova-idp-cpe.dts b/qcom/sdxkova-idp-cpe.dts index 079b3ec8..a2d3e8c1 100644 --- a/qcom/sdxkova-idp-cpe.dts +++ b/qcom/sdxkova-idp-cpe.dts @@ -7,6 +7,7 @@ #include "sdxkova.dtsi" #include "sdxkova-idp-cpe.dtsi" +#include "sdxkova-reserved-memory.dtsi" / { model = "Qualcomm Technologies, Inc. SDXKOVA IDP CPE"; diff --git a/qcom/sdxkova-idp-mbb.dts b/qcom/sdxkova-idp-mbb.dts index bbe2a28e..18dfa58e 100644 --- a/qcom/sdxkova-idp-mbb.dts +++ b/qcom/sdxkova-idp-mbb.dts @@ -7,6 +7,7 @@ #include "sdxkova.dtsi" #include "sdxkova-idp-mbb.dtsi" +#include "sdxkova-reserved-memory.dtsi" / { model = "Qualcomm Technologies, Inc. SDXKOVA IDP MBB"; diff --git a/qcom/sdxkova-reserved-memory.dtsi b/qcom/sdxkova-reserved-memory.dtsi new file mode 100644 index 00000000..0a6f7f3f --- /dev/null +++ b/qcom/sdxkova-reserved-memory.dtsi @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gunyah_hyp_mem: gunyah_hyp_region@80000000 { + no-map; + reg = <0x0 0x80000000 0x0 0x800000>; + }; + + /* HYP elf package region at 0x80800000 to be shared with Linux */ + + access_control_db_mem: access_control_db_region@81380000 { + no-map; + reg = <0x0 0x81380000 0x0 0x80000>; + }; + + qteetz_mem: qteetz_region@814e0000 { + no-map; + reg = <0x0 0x814e0000 0x0 0x2a0000>; + }; + + trusted_apps_mem: trusted_apps_region@81780000 { + no-map; + reg = <0x0 0x81780000 0x0 0xa00000>; + }; + + /* UEFI region at 0x87100000 is reclaimed by Linux */ + + /* UEFI region at 0x87500000 is reclaimed by Linux */ + + /* ABL region at 0x87900000 is reclaimed by Linux */ + + /* XBL RAMdump at 0x87a00000 to be reused Linux */ + + cpucp_fw_mem: cpucp_fw_region@87c00000 { + no-map; + reg = <0x0 0x87c00000 0x0 0x100000>; + }; + + xbl_dtlog_mem: xbl_dtlog_region@87d00000 { + no-map; + reg = <0x0 0x87d00000 0x0 0x40000>; + }; + + xbl_sc_mem: xbl_sc_region@87d40000 { + no-map; + reg = <0x0 0x87d40000 0x0 0x40000>; + }; + + modem_efs_shared_mem: modem_efs_shared_region@87d80000 { + no-map; + reg = <0x0 0x87d80000 0x0 0x10000>; + }; + + aop_image_mem: aop_image_region@87e00000 { + no-map; + reg = <0x0 0x87e00000 0x0 0x20000>; + }; + + smem_mem: smem_region@87e20000 { + no-map; + reg = <0x0 0x87e20000 0x0 0xc0000>; + }; + + aop_cmd_db_mem: aop_cmd_db_region@87ee0000 { + compatible = "qcom,cmd-db"; + no-map; + reg = <0x0 0x87ee0000 0x0 0x20000>; + }; + + aop_config_mem: aop_config_region@87f00000 { + no-map; + reg = <0x0 0x87f00000 0x0 0x20000>; + }; + + ipa_fw_mem: ipa_fw_region@87f20000 { + no-map; + reg = <0x0 0x87f20000 0x0 0x10000>; + }; + + secdata_mem: secdata_region@87f30000 { + no-map; + reg = <0x0 0x87f30000 0x0 0x1000>; + }; + + tme_crashdump_mem: tme_crashdump_region@87f31000 { + no-map; + reg = <0x0 0x87f31000 0x0 0x40000>; + }; + + tme_log_mem: tme_log_region@87f71000 { + no-map; + reg = <0x0 0x87f71000 0x0 0x4000>; + }; + + /* UEFI region at 0x87f75000 is reclaimed by Linux */ + + qdss_mem: qdss_region@88500000 { + no-map; + reg = <0x0 0x88500000 0x0 0x300000>; + }; + + qlink_logging_mem: qlink_logging_region@88800000 { + no-map; + reg = <0x0 0x88800000 0x0 0x300000>; + }; + + audio_heap_mem: audio_heap_region@88b00000 { + no-map; + reg = <0x0 0x88b00000 0x0 0x400000>; + }; + + dsm_partition_2_mem: dsm_partition_2_region@88f00000 { + no-map; + reg = <0x0 0x88f00000 0x0 0x2500000>; + }; + + dsm_partition_1_mem: dsm_partition_1_region@8b400000 { + no-map; + reg = <0x0 0x8b400000 0x0 0x2b80000>; + }; + + q6_mpss_dtb_mem: q6_mpss_dtb_region@8df80000 { + no-map; + reg = <0x0 0x8df80000 0x0 0x80000>; + }; + + mpssadsp_mem: mpssadsp_region@8e000000 { + no-map; + reg = <0x0 0x8e000000 0x0 0xf100000>; + }; + + /* Linux kernel image is loaded at 0xa8000000 */ + +}; diff --git a/qcom/sdxkova.dtsi b/qcom/sdxkova.dtsi index a4a57891..749406b2 100644 --- a/qcom/sdxkova.dtsi +++ b/qcom/sdxkova.dtsi @@ -4,7 +4,8 @@ */ #include "sdx75.dtsi" - +/delete-node/ &apps_smmu; +#include "msm-arm-smmu-sdxkova.dtsi" / { qcom_tzlog: tz-log@14680720 { compatible = "qcom,tz-log"; @@ -13,4 +14,22 @@ hyplog-address-offset = <0x410>; hyplog-size-offset = <0x414>; }; + +/delete-node/ reserved-memory; + +reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + system_cma: linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2000000>; + linux,cma-default; + }; +}; + }; diff --git a/qcom/sun-mtp-3.5mm-kiwi-v8-overlay.dts b/qcom/sun-mtp-3.5mm-kiwi-v8-overlay.dts new file mode 100644 index 00000000..e6e99360 --- /dev/null +++ b/qcom/sun-mtp-3.5mm-kiwi-v8-overlay.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-mtp-3.5mm-kiwi-v8.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun MTP with 3.5mm Kiwi WLAN V8 Power Grid"; + compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", + "qcom,mtp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; + qcom,board-id = <0x60108 0>; +}; diff --git a/qcom/sun-mtp-3.5mm-kiwi-v8.dtsi b/qcom/sun-mtp-3.5mm-kiwi-v8.dtsi new file mode 100644 index 00000000..70c2649d --- /dev/null +++ b/qcom/sun-mtp-3.5mm-kiwi-v8.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "sun-mtp-kiwi-v8.dtsi" diff --git a/qcom/sun-oemvm.dtsi b/qcom/sun-oemvm.dtsi index 1750a749..0f8177f3 100644 --- a/qcom/sun-oemvm.dtsi +++ b/qcom/sun-oemvm.dtsi @@ -12,7 +12,7 @@ interrupt-parent = <&vgic>; chosen { - bootargs = "nokaslr log_buf_len=256K console=hvc0 loglevel=8 swiotlb=noforce"; + bootargs = "nokaslr log_buf_len=256K console=hvc0 loglevel=8 swiotlb=noforce memhp_default_state=online_movable memory_hotplug.memmap_on_memory=force"; }; cpus { @@ -69,7 +69,7 @@ vendor = "QTI"; image-name = "qcom,oemvm"; qcom,pasid = <0x0 0x22>; - qcom,qtee-config-info = "p=9,39,7C,8F,97,159,7F1,CDF;"; + qcom,qtee-config-info = "p=3,9,39,7C,8F,97,159,7F1,CDF;"; qcom,secdomain-ids = <49>; qcom,primary-vm-index = <0>; vm-uri = "vmuid/oemvm"; diff --git a/qcom/sun-vm.dtsi b/qcom/sun-vm.dtsi index 03b0aa0a..32240b3c 100644 --- a/qcom/sun-vm.dtsi +++ b/qcom/sun-vm.dtsi @@ -15,7 +15,7 @@ interrupt-parent = <&vgic>; chosen { - bootargs = "nokaslr log_buf_len=256K console=hvc0 loglevel=8 swiotlb=noforce memhp_default_state=online_movable"; + bootargs = "nokaslr log_buf_len=256K console=hvc0 loglevel=8 swiotlb=noforce memhp_default_state=online_movable memory_hotplug.memmap_on_memory=force"; }; cpus { diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index fd14768b..19a60eaa 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -719,6 +719,10 @@ }; }; + qcom,glink { + compatible = "qcom,glink"; + }; + qcom,qsee_ipc_irq_bridge { compatible = "qcom,qsee-ipc-irq-bridge"; @@ -924,9 +928,9 @@ gic-interrupt-router { compatible = "qcom,gic-intr-routing"; /* keep a few m cores in class0 only to avoid wakeup of l cores */ - qcom,gic-class0-cpus = <0 1>; + qcom,gic-class0-cpus = <&CPU0 &CPU1>; /* keep other cores in class1 */ - qcom,gic-class1-cpus = <2 3 4 5 6 7>; + qcom,gic-class1-cpus = <&CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7>; }; qcom,secure-buffer { @@ -1381,7 +1385,7 @@ "disp_crm_drv5"; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>; qcom,hw-drv-ids = <0 1 2 3 4 5>; - qcom,sw-drv-ids = <0 1 2 3 4 5>; + qcom,sw-drv-ids = <0 2 3>; }; cam_crm: crm@adcb000 { @@ -2776,13 +2780,15 @@ <&adsp_smp2p_in 0 0>, <&adsp_smp2p_in 2 0>, <&adsp_smp2p_in 1 0>, - <&adsp_smp2p_in 3 0>; + <&adsp_smp2p_in 3 0>, + <&adsp_smp2p_in 7 0>; interrupt-names = "wdog", "fatal", "handover", "ready", - "stop-ack"; + "stop-ack", + "shutdown-ack"; /* Outputs to turing */ qcom,smem-states = <&adsp_smp2p_out 0>; @@ -2926,13 +2932,15 @@ <&cdsp_smp2p_in 0 0>, <&cdsp_smp2p_in 2 0>, <&cdsp_smp2p_in 1 0>, - <&cdsp_smp2p_in 3 0>; + <&cdsp_smp2p_in 3 0>, + <&cdsp_smp2p_in 7 0>; interrupt-names = "wdog", "fatal", "handover", "ready", - "stop-ack"; + "stop-ack", + "shutdown-ack"; /* Outputs to turing */ qcom,smem-states = <&cdsp_smp2p_out 0>; @@ -3179,6 +3187,12 @@ }; }; + cpucp_fast: qcom,cpucp_fast { + compatible = "qcom,cpucp_fast"; + mboxes = <&cpucp 7>; + qcom,policy-cpus = < 6 >; + }; + cpucp_log: qcom,cpucp_log@0x81210000 { compatible = "qcom,cpucp-log"; reg = <0x81210000 0x10000>, @@ -3516,6 +3530,7 @@ reg = <0x240B3400 0x300>, <0x240B3300 0x200>; reg-names = "base", "global_base"; interrupts = ; + qcom,map-ne; qcom,mport = <0>; qcom,hw-timer-hz = <19200000>; qcom,count-unit = <0x10000>; @@ -3839,6 +3854,11 @@ reg = <0x0 0x9eb00000 0x0 0x80000>; }; + lost_reg_mem2 { + no-map; + reg = <0x0 0x9eb80000 0x0 0x80000>; + }; + soccp_mem: soccp_region@9ec00000 { no-map; reg = <0x0 0x9ec00000 0x0 0x180000>; diff --git a/qcom/tuna-usb.dtsi b/qcom/tuna-usb.dtsi index cb065d25..88fa476e 100644 --- a/qcom/tuna-usb.dtsi +++ b/qcom/tuna-usb.dtsi @@ -39,6 +39,11 @@ compatible = "snps,dwc3"; reg = <0xa600000 0xd93c>; + iommus = <&apps_smmu 0x40 0x0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + dma-coherent; + interrupts = ; snps,disable-clk-gating; snps,has-lpm-erratum; diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index a69a186b..65bb5bb8 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -814,8 +814,17 @@ }; gpucc: clock-controller@3d90000 { - compatible = "qcom,dummycc"; - clock-output-names = "gpucc_clocks"; + compatible = "qcom,tuna-gpucc", "syscon"; + reg = <0x3d90000 0x9800>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CPH_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CPH_CLK_SRC>; + clock-names = "bi_tcxo", + "gpll0_out_main", + "gpll0_out_main_div"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -945,12 +954,13 @@ }; &gpu_cc_cx_gdsc { - compatible = "regulator-fixed"; + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>; + parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &gx_clkctl_gx_gdsc { - compatible = "regulator-fixed"; + parent-supply = <&VDD_GFX_MXC_VOTER_LEVEL>; status = "ok"; }; @@ -983,6 +993,7 @@ #include "tuna-stub-regulators.dtsi" #include "tuna-usb.dtsi" #include "tuna-qupv3.dtsi" +#include "msm-rdbg.dtsi" &qupv3_se7_2uart { status = "ok";