From d56825f5c411151d1516280c5e30d7797665bde5 Mon Sep 17 00:00:00 2001 From: Jayaprakash Madisetty Date: Fri, 10 Jan 2025 16:35:04 +0530 Subject: [PATCH 1/4] ARM: dts: msm: add disp_cc io to sde cesta To enable and disable mdp clock gating functionality with cesta immediate vote approach, add disp_cc_io memory to sde cesta. Change-Id: I2bd6d80269a69d870f2c8b4ff0b1bf8b1270aa6f Signed-off-by: Jayaprakash Madisetty Signed-off-by: lnxdisplay --- display/sun-sde.dtsi | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index f1e10426..ebb9dbbd 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -222,8 +222,9 @@ <0xaf33000 0x30>, <0xaf34000 0x30>, <0xaf35000 0x30>, - <0xaf36000 0x30>; - reg-names = "rscc", "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5"; + <0xaf36000 0x30>, + <0xaf0f000 0x10>; + reg-names = "rscc", "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5", "disp_cc"; clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>, From 03f3cfccb929895772920f28ab7eeef11757a226 Mon Sep 17 00:00:00 2001 From: Sailesh Reddy Male Date: Thu, 16 Jan 2025 11:43:28 +0530 Subject: [PATCH 2/4] ARM: dts: msm: enable display cesta on kera target Add display cesta related DT node on kera target. Move the GDSC & MDP core clock from MDP to cesta node, as it will be controlled through cesta. Add the cesta related register offsets in trusted-vm DT. Change-Id: I1f777f3402d8a4d7d57ca889206a4095447abb7d Signed-off-by: Sailesh Reddy Male --- display/kera-sde-display.dtsi | 3 +- display/kera-sde.dtsi | 54 ++++++++++++++++++++++++++++----- display/trustedvm-kera-sde.dtsi | 11 ++++++- 3 files changed, 58 insertions(+), 10 deletions(-) diff --git a/display/kera-sde-display.dtsi b/display/kera-sde-display.dtsi index ee0d4543..5b448fb8 100644 --- a/display/kera-sde-display.dtsi +++ b/display/kera-sde-display.dtsi @@ -87,7 +87,8 @@ }; &mdss_mdp { - connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb2 &sde_dp>; + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb2 &sde_dp + &sde_cesta>; }; &dsi_vtdr6130_amoled_cmd { diff --git a/display/kera-sde.dtsi b/display/kera-sde.dtsi index bb73d70f..8c06d42e 100644 --- a/display/kera-sde.dtsi +++ b/display/kera-sde.dtsi @@ -207,27 +207,65 @@ clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "mdp_core_clk"; }; + + sde_cesta: qcom,sde_cesta@0x0af30000 { + cell-index = <0>; + compatible = "qcom,sde-cesta"; + reg = <0x0af20000 0x850>, + <0xaf30000 0x60>, + <0xaf31000 0x30>, + <0xaf32000 0x30>, + <0xaf33000 0x30>, + <0xaf34000 0x30>, + <0xaf35000 0x30>, + <0xaf36000 0x30>; + reg-names = "rscc", "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5"; + + clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; + + clock-names = "branch_clk", "core_clk"; + clock-rate = <660000000 660000000>; + clock-max-rate = <660000000 660000000>; + clock-mmrm = <0 DISP_CC_MDSS_MDP_CLK_SRC>; + + interconnects = <&mmss_noc MASTER_MDP_DISP_CRM_HW_0 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_0>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_1 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_1>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_2 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_2>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_3 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_3>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_4 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_4>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_5 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_5>, + <&mmss_noc MASTER_MDP_DISP_CRM_SW_0 + &mc_virt SLAVE_EBI1_DISP_CRM_SW_0>; + interconnect-names = "qcom,sde-data-bus-hw-0", "qcom,sde-data-bus-hw-1", + "qcom,sde-data-bus-hw-2", "qcom,sde-data-bus-hw-3", + "qcom,sde-data-bus-hw-4", "qcom,sde-data-bus-hw-5", + "qcom,sde-data-bus-sw-0"; + + power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; + }; }; &mdss_mdp { clocks = <&gcc GCC_DISP_HF_AXI_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>, <&dispcc DISP_CC_MDSS_VSYNC_CLK>, <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; clock-names = "gcc_bus", - "iface_clk", "branch_clk", "core_clk", "vsync_clk", - "lut_clk"; - clock-rate = <0 0 660000000 660000000 19200000 660000000>; - clock-max-rate = <0 0 660000000 660000000 19200000 660000000>; + "iface_clk", "vsync_clk", "lut_clk"; + clock-rate = <0 0 19200000 660000000>; + clock-max-rate = <0 0 19200000 660000000>; qcom,hw-fence-sw-version = <0x1>; - power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; - qti,smmu-proxy-cb-id = ; qcom,sde-vm-exclude-reg-names = "ipcc_reg", "swfuse_phys"; diff --git a/display/trustedvm-kera-sde.dtsi b/display/trustedvm-kera-sde.dtsi index 3740746b..05d3d958 100644 --- a/display/trustedvm-kera-sde.dtsi +++ b/display/trustedvm-kera-sde.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -36,6 +36,15 @@ "sid_phys"; qcom,sde-vm-exclude-reg-names = "sid_phys"; + + qcom,tvm-include-reg = <0x0af20000 0x850>, + <0xaf30000 0x60>, + <0xaf31000 0x30>, + <0xaf32000 0x30>, + <0xaf33000 0x30>, + <0xaf34000 0x30>, + <0xaf35000 0x30>, + <0xaf36000 0x30>; qcom,sde-hw-version = <0xC0040000>; clocks = <&clock_cpucc GCC_DISP_AHB_CLK>, From 709107dd1c60bdfce13389caf134fb4f4af43148 Mon Sep 17 00:00:00 2001 From: Sailesh Reddy Male Date: Mon, 20 Jan 2025 15:07:40 +0530 Subject: [PATCH 3/4] ARM: dts: msm: add xo clock in sde_cesta for kera target Add xo clock in sde_cesta for kera target. This will help to vote for xo frequency during cesta idle time. Change-Id: Ic4370c8a49ffbec2743c022e438280d371a5a968 Signed-off-by: Sailesh Reddy Male --- display/kera-sde.dtsi | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/display/kera-sde.dtsi b/display/kera-sde.dtsi index 8c06d42e..1148e017 100644 --- a/display/kera-sde.dtsi +++ b/display/kera-sde.dtsi @@ -222,12 +222,13 @@ reg-names = "rscc", "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5"; clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>, + <&dispcc DISP_CC_XO_CLK_SRC>; - clock-names = "branch_clk", "core_clk"; - clock-rate = <660000000 660000000>; - clock-max-rate = <660000000 660000000>; - clock-mmrm = <0 DISP_CC_MDSS_MDP_CLK_SRC>; + clock-names = "branch_clk", "core_clk", "xo"; + clock-rate = <660000000 660000000 19200000>; + clock-max-rate = <660000000 660000000 19200000>; + clock-mmrm = <0 DISP_CC_MDSS_MDP_CLK_SRC 0>; interconnects = <&mmss_noc MASTER_MDP_DISP_CRM_HW_0 &mc_virt SLAVE_EBI1_DISP_CRM_HW_0>, From 4648e8647fbbd3d2adb983711a54a1c67b7e2bd0 Mon Sep 17 00:00:00 2001 From: Sailesh Reddy Male Date: Tue, 11 Feb 2025 15:22:29 +0530 Subject: [PATCH 4/4] ARM: dts: msm: add disp_cc io to cesta and ctl hyp to mdss_mdp device To enable and disable mdp clock gating functionality with cesta immediate vote approach, add disp_cc_io memory to sde cesta. Add changes to enable ctl hyp property for reserve reservation on datapath used in a VM. Change-Id: Id10875ecb90acb8a922ef4e4788da13a764ea102 Signed-off-by: Sailesh Reddy Male --- display/kera-sde-common.dtsi | 5 ++++- display/kera-sde.dtsi | 6 ++++-- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/display/kera-sde-common.dtsi b/display/kera-sde-common.dtsi index a2822e3e..94e9cdb8 100644 --- a/display/kera-sde-common.dtsi +++ b/display/kera-sde-common.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -31,6 +31,9 @@ qcom,sde-off = <0x1000>; qcom,sde-len = <0x488>; + qcom,sde-ctl-hyp-off = <0x15000>; + qcom,sde-ctl-hyp-size = <0xc00>; + qcom,sde-ctl-off = <0x16000 0x17000 0x18000 0x19000>; qcom,sde-ctl-size = <0x1000>; qcom,sde-ctl-display-pref = "primary", "none", "none", "none"; diff --git a/display/kera-sde.dtsi b/display/kera-sde.dtsi index 1148e017..f2714059 100644 --- a/display/kera-sde.dtsi +++ b/display/kera-sde.dtsi @@ -218,8 +218,10 @@ <0xaf33000 0x30>, <0xaf34000 0x30>, <0xaf35000 0x30>, - <0xaf36000 0x30>; - reg-names = "rscc", "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5"; + <0xaf36000 0x30>, + <0xaf0f000 0x10>; + reg-names = "rscc", "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5", + "disp_cc"; clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>,