diff --git a/qcom/kera-rumi.dtsi b/qcom/kera-rumi.dtsi
index e05aabe2..7beb68b6 100644
--- a/qcom/kera-rumi.dtsi
+++ b/qcom/kera-rumi.dtsi
@@ -180,3 +180,11 @@
 &disp_cc_mdss_core_int2_gdsc {
 	status = "ok";
 };
+
+&gpu_cc_cx_gdsc {
+	status = "ok";
+};
+
+&gpu_cc_gx_gdsc {
+	status = "ok";
+};
diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi
index 1f4c8f2c..1840e347 100644
--- a/qcom/kera.dtsi
+++ b/qcom/kera.dtsi
@@ -1872,14 +1872,18 @@
 		reg-name = "cc_base";
 		vdd_cx-supply = <&VDD_CX_LEVEL>;
 		vdd_mx-supply = <&VDD_MX_LEVEL>;
+		vdd_gx-supply = <&VDD_GFX_LEVEL>;
 		clocks = <&rpmhcc RPMH_CXO_CLK>,
+			<&rpmhcc RPMH_CXO_CLK_A>,
 			 <&gcc GCC_GPU_GPLL0_CPH_CLK_SRC>,
 			 <&gcc GCC_GPU_GPLL0_DIV_CPH_CLK_SRC>;
 		clock-names = "bi_tcxo",
+			      "bi_tcxo_ao",
 			      "gpll0_out_main",
 			      "gpll0_out_main_div";
 		#clock-cells = <1>;
 		#reset-cells = <1>;
+		#power-domain-cells = <1>;
 	};
 
 	tcsrcc: clock-controller@1f40000 {
@@ -3259,14 +3263,12 @@
 	parent-supply = <&VDD_CX_LEVEL>;
 	clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
 	clock-names = "ahb_clk";
-	status = "ok";
 };
 
 &gpu_cc_gx_gdsc {
 	parent-supply = <&VDD_GFX_LEVEL>;
 	clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
 	clock-names = "ahb_clk";
-	status = "ok";
 };
 
 &video_cc_mvs0_gdsc {