From f12b2d8069ea5d9843e7178d6d8f10c99faa5902 Mon Sep 17 00:00:00 2001 From: Saranya R Date: Tue, 2 Jul 2024 18:47:27 +0530 Subject: [PATCH] ARM: dts: msm: Use "iommu-addresses" property for ravelin dwc3 Use upstream compatible DT property "iommu-addresses" instead of "qcom,iommu-dma-addr-pool" for dwc3 which describes the addresses that dwc3 cannot use. Extend the address and size cells to ensure that IOMMU returns a 32 bit address, in order to define a region that will block 0xf0000000--0xffffffffffffffff. Change-Id: I211ba1b8bd1f7717f639d91dddb8adb86f17b42e Signed-off-by: Saranya R --- qcom/ravelin-usb.dtsi | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/qcom/ravelin-usb.dtsi b/qcom/ravelin-usb.dtsi index 3038be02..bd29bc5e 100644 --- a/qcom/ravelin-usb.dtsi +++ b/qcom/ravelin-usb.dtsi @@ -12,8 +12,8 @@ reg = <0xa600000 0x100000>; reg-names = "core_base"; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; ranges; USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>; @@ -58,13 +58,13 @@ extcon = <&eud>; - dwc3@a600000 { + dwc3_0: dwc3@a600000 { compatible = "snps,dwc3"; - reg = <0xa600000 0xd800>; + reg = <0x0 0xa600000 0x0 0xd800>; iommus = <&apps_smmu 0x540 0x0>; qcom,iommu-dma = "atomic"; - qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + memory-region = <&dwc3_mem_region>; dma-coherent; interrupts = ; @@ -89,6 +89,11 @@ }; }; + dwc3_mem_region: dwc3_mem_region { + iommu-addresses = <&dwc3_0 0x0 0x0 0x0 0x90000000>, + <&dwc3_0 0x0 0xf0000000 0xffffffff 0x10000000>; + }; + /* USB port related High Speed PHY */ usb2_phy0: hsphy@88e3000 { compatible = "qcom,usb-hsphy-snps-femto";