From f28b0bdded5243670d1cf9e6a2da0773ee5e200a Mon Sep 17 00:00:00 2001 From: Anaadi Mishra Date: Wed, 28 Aug 2024 14:16:14 +0530 Subject: [PATCH 1/3] ARM: dts: msm: Update gpucc node as GenPD provider Mark gpucc clock node as GenPD provider and disable the graphics GDSC regulator nodes. While at it, keep the gdsc's as it is on rumi platform. Change-Id: I91b4915723e26685e950de3ae575540ac3940036 Signed-off-by: Anaadi Mishra --- qcom/kera-rumi.dtsi | 8 ++++++++ qcom/kera.dtsi | 6 ++++-- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/qcom/kera-rumi.dtsi b/qcom/kera-rumi.dtsi index c3ef9498..343aecd6 100644 --- a/qcom/kera-rumi.dtsi +++ b/qcom/kera-rumi.dtsi @@ -180,3 +180,11 @@ &disp_cc_mdss_core_int2_gdsc { status = "ok"; }; + +&gpu_cc_cx_gdsc { + status = "ok"; +}; + +&gpu_cc_gx_gdsc { + status = "ok"; +}; diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index cef15bc2..c107ded7 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -1853,14 +1853,18 @@ reg-name = "cc_base"; vdd_cx-supply = <&VDD_CX_LEVEL>; vdd_mx-supply = <&VDD_MX_LEVEL>; + vdd_gx-supply = <&VDD_GFX_LEVEL>; clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, <&gcc GCC_GPU_GPLL0_CPH_CLK_SRC>, <&gcc GCC_GPU_GPLL0_DIV_CPH_CLK_SRC>; clock-names = "bi_tcxo", + "bi_tcxo_ao", "gpll0_out_main", "gpll0_out_main_div"; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>; }; tcsrcc: clock-controller@1f40000 { @@ -3225,14 +3229,12 @@ parent-supply = <&VDD_CX_LEVEL>; clocks = <&gcc GCC_GPU_CFG_AHB_CLK>; clock-names = "ahb_clk"; - status = "ok"; }; &gpu_cc_gx_gdsc { parent-supply = <&VDD_GFX_LEVEL>; clocks = <&gcc GCC_GPU_CFG_AHB_CLK>; clock-names = "ahb_clk"; - status = "ok"; }; &video_cc_mvs0_gdsc { From 7037f12c766641d1de718bf322bda90daf909088 Mon Sep 17 00:00:00 2001 From: Anaadi Mishra Date: Thu, 12 Dec 2024 15:57:48 +0530 Subject: [PATCH 2/3] ARM: dts: msm: Move the pcie_1 clocks to protected-clocks Mark the pcie_1 clocks as protected and remove the pcie_1 gdsc nodes. Change-Id: I3102a52895a6531fb82a411bdb760073fc3c28f3 Signed-off-by: Anaadi Mishra --- qcom/kera.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index c107ded7..0cfad6d4 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -1843,6 +1843,12 @@ "ufs_phy_rx_symbol_1_clk", "ufs_phy_tx_symbol_0_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk"; + protected-clocks = <&gcc GCC_PCIE_1_AUX_CLK>, <&gcc GCC_PCIE_1_AUX_CLK_SRC>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_1_PHY_RCHNG_CLK_SRC>, + <&gcc GCC_PCIE_1_PIPE_CLK>, <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, + <&gcc GCC_PCIE_1_PIPE_DIV2_CLK>, <&gcc GCC_PCIE_1_PIPE_DIV2_CLK_SRC>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; #clock-cells = <1>; #reset-cells = <1>; }; @@ -3192,12 +3198,10 @@ &gcc_pcie_1_gdsc { parent-supply = <&VDD_CX_LEVEL>; - status = "ok"; }; &gcc_pcie_1_phy_gdsc { parent-supply = <&VDD_MX_LEVEL>; - status = "ok"; }; &gcc_ufs_mem_phy_gdsc { From 6c751c7e73cac130025fec1168c65d45b8b1d1fa Mon Sep 17 00:00:00 2001 From: Ajit Pandey Date: Fri, 25 Oct 2024 10:16:16 +0530 Subject: [PATCH 3/3] ARM: dts: msm: Add support for cpufreq_hw node on KERA Add support for cpufreq_hw and cpufreq_hw_debug nodes on kera platform. While at it, set the default governor to performance on kera platform. Change-Id: Id6fd146d3c80f686780591e5efa594bd76155bcd Signed-off-by: Ajit Pandey --- qcom/kera.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 0cfad6d4..a6c5b1f9 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -101,6 +101,7 @@ cpu-idle-states = <&SILVER_OFF &SILVER_RAIL_OFF>; power-domains = <&CPU_PD0>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&L2_0>; #cooling-cells = <2>; dynamic-power-coefficient = <100>; @@ -125,6 +126,7 @@ cpu-idle-states = <&SILVER_OFF &SILVER_RAIL_OFF>; power-domains = <&CPU_PD1>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&L2_0>; dynamic-power-coefficient = <100>; capacity-dmips-mhz = <1024>; @@ -139,6 +141,7 @@ cpu-idle-states = <&SILVER_OFF &SILVER_RAIL_OFF>; power-domains = <&CPU_PD2>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&L2_2>; #cooling-cells = <2>; dynamic-power-coefficient = <100>; @@ -158,6 +161,7 @@ cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; power-domains = <&CPU_PD3>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; next-level-cache = <&L2_3>; #cooling-cells = <2>; dynamic-power-coefficient = <263>; @@ -177,6 +181,7 @@ cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; power-domains = <&CPU_PD4>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; next-level-cache = <&L2_4>; #cooling-cells = <2>; dynamic-power-coefficient = <263>; @@ -196,6 +201,7 @@ cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; power-domains = <&CPU_PD5>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; next-level-cache = <&L2_5>; #cooling-cells = <2>; dynamic-power-coefficient = <263>; @@ -215,6 +221,7 @@ cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; power-domains = <&CPU_PD6>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; next-level-cache = <&L2_6>; #cooling-cells = <2>; dynamic-power-coefficient = <263>; @@ -234,6 +241,7 @@ cpu-idle-states = <&GOLD_PLUS_OFF &GOLD_PLUS_RAIL_OFF>; power-domains = <&CPU_PD7>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 2>; next-level-cache = <&L2_7>; #cooling-cells = <2>; dynamic-power-coefficient = <289>; @@ -1905,6 +1913,24 @@ compatible = "smmu-proxy-sender"; }; + cpufreq_hw: qcom,cpufreq-hw { + compatible = "qcom,cpufreq-epss"; + reg = <0x17d91000 0x1000>, <0x17d92000 0x1000>, <0x17d93000 0x1000>; + reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + interrupts = , + , + ; + interrupt-names = "dcvsh0_int", "dcvsh1_int", "dcvsh2_int"; + #freq-domain-cells = <1>; + }; + + qcom,cpufreq-hw-debug { + compatible = "qcom,cpufreq-hw-epss-debug"; + qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>, <&cpufreq_hw 2>; + }; + clk_virt: interconnect@0 { compatible = "qcom,kera-clk_virt"; #interconnect-cells = <1>;