From eca7fe7ef3eb23b3ef35cca0805d2c24c4df6eb1 Mon Sep 17 00:00:00 2001
From: Anaadi Mishra <quic_anaadim@quicinc.com>
Date: Wed, 25 Sep 2024 16:36:41 +0530
Subject: [PATCH] ARM: dts: msm: Update dispcc clock node as GenPD provider on
 Kera

Mark dispcc clock node as GenPD provider and disable the display GDSC
regulator nodes for kera platform.
While at it, keep the gdsc's as it is on kera-rumi platform and update
the compatible to align with freq plan.

Change-Id: If01f876b3d160cf5c1cfe6be13e3e4b42f62cfa6
Signed-off-by: Anaadi Mishra <quic_anaadim@quicinc.com>
---
 qcom/kera-rumi.dtsi | 8 ++++++++
 qcom/kera.dtsi      | 5 ++---
 2 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/qcom/kera-rumi.dtsi b/qcom/kera-rumi.dtsi
index 76d7f98c..e05aabe2 100644
--- a/qcom/kera-rumi.dtsi
+++ b/qcom/kera-rumi.dtsi
@@ -172,3 +172,11 @@
 &video_cc_mvs0c_gdsc {
 	status = "ok";
 };
+
+&disp_cc_mdss_core_gdsc {
+	status = "ok";
+};
+
+&disp_cc_mdss_core_int2_gdsc {
+	status = "ok";
+};
diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi
index ac2ac1de..efcb4f6d 100644
--- a/qcom/kera.dtsi
+++ b/qcom/kera.dtsi
@@ -1798,7 +1798,7 @@
 	};
 
 	dispcc: clock-controller@af00000 {
-		compatible = "qcom,tuna-dispcc", "syscon";
+		compatible = "qcom,kera-dispcc", "syscon";
 		reg = <0xaf00000 0x20000>;
 		reg-name = "cc_base";
 		vdd_mm-supply = <&VDD_CX_LEVEL>;
@@ -1814,6 +1814,7 @@
 		qcom,disp_crm-crmc = <&dispcc_crm>;
 		#clock-cells = <1>;
 		#reset-cells = <1>;
+		#power-domain-cells = <1>;
 	};
 
 	gcc: clock-controller@100000 {
@@ -3163,13 +3164,11 @@
 &disp_cc_mdss_core_gdsc {
 	clocks = <&gcc GCC_DISP_AHB_CLK>;
 	parent-supply = <&VDD_CX_LEVEL>;
-	status = "ok";
 };
 
 &disp_cc_mdss_core_int2_gdsc {
 	clocks = <&gcc GCC_DISP_AHB_CLK>;
 	parent-supply = <&VDD_CX_LEVEL>;
-	status = "ok";
 };
 
 &gcc_pcie_0_gdsc {