dt-bindings: Add devicetree bindings for qcedev
Add snapshot of devicetree bindings from commit (bb95f5ff94: "ARM: dts: msm: Add probe dependency to PMIC PON Log driver") for qcedev. Update the bindings from .txt to .yaml. Change-Id: I7e46035c6ac66c14e932c009d4a1291ec6127001 Signed-off-by: Daniel Perez-Zoghbi <quic_dperezzo@quicinc.com>
This commit is contained in:
Daniel Perez-Zoghbi
335
bindings/crypto/qcom,qce.yaml
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335
bindings/crypto/qcom,qce.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/crypto/qcom,qce.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: QTI Crypto Engine Device
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maintainers:
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- Daniel Perez-Zoghbi <quic_dperezzo@quicinc.com>
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- Gaurav Kashyap <quic_gaurkash@quicinc.com>
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- Arun Menon <quic_avmenon@quicinc.com>
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- Udit Tiwari <quic_utiwari@quicinc.com>
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- Om Prakash Singh <quic_pbhavara@quicinc.com>
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description: |
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This driver provides IOCTLS for user space application to access crypto
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engine hardware for the qcedev crypto services. The driver supports the
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following crypto algorithms
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- AES-128, AES-256 (ECB, CBC and CTR mode)
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- AES-192, (ECB, CBC and CTR mode)
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(support exists on platform supporting CE 3.x hardware)
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- SHA1/SHA256
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- AES-128, AES-256 (XTS), AES CMAC, SHA1/SHA256 HMAC
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(support exists on platform supporting CE 4.x hardware)
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properties:
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compatible:
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const: "qcom,qcedev"
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reg:
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oneOf:
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- items:
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- description: crypto base registers
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- items:
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- description: crypto base registers
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- description: crypto bam base registers
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reg-names:
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oneOf:
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- items:
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- const: crypto-base
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- items:
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- const: crypto-base
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- const: crypto-bam-base
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interconnects:
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minItems: 1
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interconnect-names:
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const: data_path
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interrupts:
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maxItems: 1
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iommus:
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maxItems: 2
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qcom,iommu-dma:
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description: |
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default
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Standard iommu translation behaviour. Calling iommu and DMA apis in
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atomic context is not allowed.
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bypass
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DMA APIs will use 1-to-1 translation between dma_addr and phys_addr.
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fastmap
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DMA APIs will run faster, but use several orders of magnitude more
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memory. Also allows using iommu and DMA apis in atomic context.
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atomic
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Allows using iommu and DMA apis in atomic context.
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disabled
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The iommu client is responsible for allocating an iommu domain.
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enum:
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- default
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- bypass
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- fastmap
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- atomic
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- disabled
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dma-coherent: true
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qcom_cedev_ns_cb:
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description: |
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a non-secure context bank
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type: object
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properties:
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compatible:
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const: qcom,qcedev,context-bank
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label:
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description: |
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A string name for the context bank
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minItems: 1
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iommus:
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maxItems: 1
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dma-coherent: true
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required:
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- compatible
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- label
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- iommus
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- dma-coherent
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additionalProperties: false
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qcom_cedev_s_cb:
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description: |
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a secure context bank
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type: object
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properties:
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compatible:
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const: qcom,qcedev,context-bank
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label:
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description: |
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A string name for the context bank
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minItems: 1
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iommus:
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maxItems: 1
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dma-coherent: true
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qcom,iommu-vmid:
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$ref: '/schemas/types.yaml#/definitions/uint32'
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description: |
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An identifier indicating the security state of the client.
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qcom,secure-context-bank:
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description: Identify if the context bank is secure
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type: boolean
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required:
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- compatible
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- label
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- iommus
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- dma-coherent
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- qcom,iommu-vmid
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- qcom,secure-context-bank
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additionalProperties: false
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qcom,bam-pipe-pair:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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An integer corresponding to the pipe number for general purpose
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use for HLOS kernel operations.
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qcom,offload-ops-support:
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description: Allow offload operations and load the offload pipes
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type: boolean
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qcom,bam-pipe-offload-cpb-hlos:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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An integer corresponding to the pipe number for operations
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from a content protected buffer (cpb) to an hlos buffer.
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qcom,bam-pipe-offload-hlos-cpb:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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An integer corresponding to the pipe number for operations
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from an hlos buffer to a content protected buffer (cpb).
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qcom,bam-pipe-offload-hlos-cpb-1:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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An integer corresponding to the second pipe number for operations
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from an hlos buffer to a content protected buffer (cpb).
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qcom,bam-pipe-offload-hlos-hlos:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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An integer corresponding to the pipe number for operations
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from an hlos buffer to an hlos buffer.
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qcom,bam-pipe-offload-hlos-hlos-1:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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An integer corresponding to the second pipe number for operations
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from an hlos buffer to an hlos buffer.
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qcom,ce-hw-instance:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Instance number for device
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minimum: 0
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maximum: 1
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qcom,ce-device:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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uid number for the device
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qcom,ce-hw-shared:
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description: Determines if the crypto engine is being shared.
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type: boolean
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qcom,bam-ee:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Determines the Execution Environment (EE) of BAM.
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This is defaulted to 1.
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qcom,smmu-s1-enable:
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description: Enable/Disable the SMMU.
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type: boolean
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qcom,no-clock-support:
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description: Disables crypto engine clocks
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type: boolean
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# all below are optional, some above are optional
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qcom,icc_avg_bw:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Average bandwidth. Used to set clocks.
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Default 384 (low)
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qcom,icc_peak_bw:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Peak bandwidth. Used to set clocks.
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Default 384 (low)
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qcom,use-sw-aes-cbc-ecb-ctr-algo:
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description: Use software for CBC, ECB, and CTR modes in AES.
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type: boolean
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qcom,use-sw-aead-algo:
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description: Use software for AEAD algorithms.
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type: boolean
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qcom,use-sw-aes-xts-algo:
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description: Use software for AES XTS
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type: boolean
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qcom,use-sw-ahash-algo:
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description: Use software for ahash
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type: boolean
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qcom,use-sw-hmac-algo:
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description: Use software for hmac
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type: boolean
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qcom,use-sw-aes-ccm-algo:
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description: Use software for AES CCM
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type: boolean
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qcom,clk-mgmt-sus-res:
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description: Use clock management suspend request
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type: boolean
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qcom,support-core-clk-only:
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description: Only use the core clock
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type: boolean
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qcom,request-bw-before-clk:
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description: Request bw before setting clock rate on init
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type: boolean
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required:
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- compatible
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- reg
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- reg-names
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- interrupts
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- interconnects
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- interconnect-names
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- qcom_cedev_ns_cb
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- qcom_cedev_s_cb
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- qcom,bam-pipe-pair
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- qcom,ce-hw-instance
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- qcom,ce-device
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interconnect/qcom,sun.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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qcedev@1de0000 {
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compatible = "qcom,qcedev";
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reg = <0x1de0000 0x20000>,
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<0x1dc4000 0x28000>;
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reg-names = "crypto-base","crypto-bam-base";
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interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
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qcom,bam-pipe-pair = <2>;
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qcom,offload-ops-support;
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qcom,bam-pipe-offload-cpb-hlos = <1>;
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qcom,bam-pipe-offload-hlos-cpb = <3>;
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qcom,bam-pipe-offload-hlos-cpb-1 = <8>;
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qcom,bam-pipe-offload-hlos-hlos = <4>;
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qcom,bam-pipe-offload-hlos-hlos-1 = <9>;
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qcom,ce-hw-instance = <0>;
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qcom,ce-device = <0>;
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qcom,ce-hw-shared;
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qcom,bam-ee = <0>;
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qcom,smmu-s1-enable;
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qcom,no-clock-support;
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interconnect-names = "data_path";
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interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
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iommus = <&apps_smmu 0x0480 0x0>,
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<&apps_smmu 0x0481 0x0>;
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qcom,iommu-dma = "atomic";
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dma-coherent;
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qcom_cedev_ns_cb {
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compatible = "qcom,qcedev,context-bank";
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label = "ns_context";
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iommus = <&apps_smmu 0x0481 0x0>;
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dma-coherent;
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};
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qcom_cedev_s_cb {
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compatible = "qcom,qcedev,context-bank";
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label = "secure_context";
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iommus = <&apps_smmu 0x0483 0x0>;
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qcom,iommu-vmid = <0x9>;
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qcom,secure-context-bank;
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dma-coherent;
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};
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};
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};
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