diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi
index 37250471..838d234e 100644
--- a/qcom/sun.dtsi
+++ b/qcom/sun.dtsi
@@ -2324,67 +2324,6 @@
 		      <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
 		interconnect-names = "ufs-ddr", "cpu-ufs";
 
-		qcom,ufs-bus-bw,name = "ufshc_mem";
-		qcom,ufs-bus-bw,num-cases = <30>;
-		qcom,ufs-bus-bw,num-paths = <2>;
-		qcom,ufs-bus-bw,vectors-KBps =
-		/*
-		 * During HS G3 UFS runs at nominal voltage corner, vote
-		 * higher bandwidth to push other buses in the data path
-		 * to run at nominal to achieve max throughput.
-		 * 4GBps pushes BIMC to run at nominal.
-		 * 200MBps pushes CNOC to run at nominal.
-		 * Vote for half of this bandwidth for HS G3 1-lane.
-		 * For max bandwidth, vote high enough to push the buses
-		 * to run in turbo voltage corner.
-		 */
-		<0 0>, <0 0>,          /* No vote */
-		<922 0>, <1000 0>,     /* PWM G1 */
-		<1844 0>, <1000 0>,    /* PWM G2 */
-		<3688 0>, <1000 0>,    /* PWM G3 */
-		<7376 0>, <1000 0>,    /* PWM G4 */
-		<14752 0>, <1000 0>,   /* PWM G5 */
-		<1844 0>, <1000 0>,    /* PWM G1 L2 */
-		<3688 0>, <1000 0>,    /* PWM G2 L2 */
-		<7376 0>, <1000 0>,    /* PWM G3 L2 */
-		<14752 0>, <1000 0>,   /* PWM G4 L2 */
-		<29504 0>, <1000 0>,   /* PWM G5 L2 */
-		<127796 0>, <1000 0>,  /* HS G1 RA */
-		<255591 0>, <1000 0>,  /* HS G2 RA */
-		<1492582 0>, <102400 0>,  /* HS G3 RA */
-		<2915200 0>, <204800 0>,  /* HS G4 RA */
-		<255591 0>, <1000 0>,  /* HS G1 RA L2 */
-		<511181 0>, <1000 0>,  /* HS G2 RA L2 */
-		<1492582 0>, <204800 0>, /* HS G3 RA L2 */
-		<2915200 0>, <409600 0>, /* HS G4 RA L2 */
-		<149422 0>, <1000 0>,  /* HS G1 RB */
-		<298189 0>, <1000 0>,  /* HS G2 RB */
-		<1492582 0>, <102400 0>,  /* HS G3 RB */
-		<2915200 0>, <204800 0>,  /* HS G4 RB */
-		<298189 0>, <1000 0>,  /* HS G1 RB L2 */
-		<596378 0>, <1000 0>,  /* HS G2 RB L2 */
-		/* As UFS working in HS G3 RB L2 mode, aggregated
-		 * bandwidth (AB) should take care of providing
-		 * optimum throughput requested. However, as tested,
-		 * in order to scale up CNOC clock, instantaneous
-		 * bindwidth (IB) needs to be given a proper value too.
-		 */
-		<1492582 0>, <204800 409600>, /* HS G3 RB L2 KBPs */
-		<2915200 0>, <409600 409600>, /* HS G4 RB L2 */
-		<5836800 0>, <819200 0>,      /* HS G5 RA L2*/
-		<5836800 0>, <819200 0>,      /* HS G5 RB L2 */
-		<7643136 0>, <819200 0>;      /* Max. bandwidth */
-
-		qcom,bus-vector-names = "MIN",
-		"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", "PWM_G5_L1",
-		"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", "PWM_G5_L2",
-		"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1",
-		"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2",
-		"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1",
-		"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2",
-		"HS_RA_G5_L2", "HS_RB_G5_L2",
-		"MAX";
-
 		/* set the dependency that smmu being probed before ufs */
 		depends-on-supply = <&apps_smmu>;