From bc6d0ca2a931217d2e0c5fd624faaee28edb43d9 Mon Sep 17 00:00:00 2001 From: Prudhvi Yarlagadda Date: Mon, 9 Oct 2023 18:23:20 -0700 Subject: [PATCH] ARM: dts: msm: Add device_type property for pcie node Add device_type property for the pcie devicetree nodes in sun. This is needed to make sure that the pcie devicetree node is associated with the pci bus when ranges property gets parsed by the of/address.c driver. And this change is mandatory for pci devicetree nodes with the introduction of the following change in of/address.c upstream commit <3d5089c4263d> "of/address: Add support for 3 address cell bus". Without this change, BAR address allocation failure will happen as error logs below as the flags cell in ranges property in devicetree will be read wrong. pci-msm 1c00000.qcom,pcie:err 0x0060200000..0x00602fffff -> 0x0060200000. pci-msm 1c00000.qcom,pcie:err 0x0060300000..0x0063ffffff -> 0x0060300000. pci-msm 1c00000.qcom,pcie: non-prefetchable memory resource required. pci 0000:00:00.0: BAR 0: no space for [mem size 0x00001000 64bit]. pci 0000:00:00.0: BAR 0: failed to assign [mem size 0x00001000 64bit]. Change-Id: I8b1591ea83784ffc19c928e1af73117657ac7f15 Signed-off-by: Prudhvi Yarlagadda --- qcom/sun-pcie.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sun-pcie.dtsi b/qcom/sun-pcie.dtsi index ff6e6c5d..4f578c14 100644 --- a/qcom/sun-pcie.dtsi +++ b/qcom/sun-pcie.dtsi @@ -9,6 +9,7 @@ &soc { pcie0: qcom,pcie@1c00000 { compatible = "qcom,pci-msm"; + device_type = "pci"; reg = <0x01c00000 0x3000>, <0x01c06000 0x2000>,