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ARM: dts: msm: Add snapshot of pineapple device tree

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Add snapshot of pineapple device tree files as of devicetree/qcom-6.1
commit 8bc1219b2b23 ("Merge "ARM: dts: msm: update memlat tables for
pineapple"").

Change-Id: If62ee45b1f3e7e8a5744f25b8c67a9768950c960
Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
This commit is contained in:
Mukesh Ojha
2023-05-18 18:19:01 +05:30
parent d86fa8483b
commit e9b9d27ee3
50 changed files with 27977 additions and 0 deletions
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23
qcom/Makefile
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@@ -30,6 +30,29 @@ sun-dtb-$(CONFIG_ARCH_SUN) += \
$(call add-overlays, $(SUN_BOARDS) $(APQ_SUN_BOARDS),$(SUN_APQ_BASE_DTB)) $(call add-overlays, $(SUN_BOARDS) $(APQ_SUN_BOARDS),$(SUN_APQ_BASE_DTB))
sun-overlays-dtb-$(CONFIG_ARCH_SUN) += $(SUN_BOARDS) $(NOAPQ_SUN_BOARDS) $(SUN_BASE_DTB) $(SUN_APQ_BASE_DTB) sun-overlays-dtb-$(CONFIG_ARCH_SUN) += $(SUN_BOARDS) $(NOAPQ_SUN_BOARDS) $(SUN_BASE_DTB) $(SUN_APQ_BASE_DTB)
dtb-y += $(sun-dtb-y) dtb-y += $(sun-dtb-y)
PINEAPPLE_BASE_DTB += pineapple.dtb pineapple-v2.dtb
PINEAPPLE_APQ_BASE_DTB += pineapplep.dtb pineapplep-v2.dtb
PINEAPPLE_BOARDS += \
pineapple-mtp-overlay.dtbo \
pineapple-mtp-nfc-overlay.dtbo \
pineapple-cdp-overlay.dtbo \
pineapple-cdp-nfc-overlay.dtbo \
pineapple-qrd-overlay.dtbo \
pineapple-qrd-sku2-overlay.dtbo \
pineapple-rcm-overlay.dtbo \
pineapple-atp-overlay.dtbo
NOAPQ_PINEAPPLE_BOARDS += \
pineapple-rumi-overlay.dtbo
pineapple-dtb-$(CONFIG_ARCH_PINEAPPLE) += \
$(call add-overlays, $(PINEAPPLE_BOARDS) $(NOAPQ_PINEAPPLE_BOARDS),$(PINEAPPLE_BASE_DTB))\
$(call add-overlays, $(PINEAPPLE_BOARDS) $(APQ_PINEAPPLE_BOARDS),$(PINEAPPLE_APQ_BASE_DTB))
pineapple-overlays-dtb-$(CONFIG_ARCH_PINEAPPLE) += $(PINEAPPLE_BOARDS) $(NOAPQ_PINEAPPLE_BOARDS) $(PINEAPPLE_BASE_DTB) $(PINEAPPLE_APQ_BASE_DTB)
dtb-y += $(pineapple-dtb-y)
endif endif
always-y := $(dtb-y) always-y := $(dtb-y)

36
qcom/ipcc-test.dtsi Normal file
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@@ -0,0 +1,36 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/soc/qcom,ipcc.h>
&soc {
ipcc_self_ping_apss: ipcc-self-ping-apss {
compatible = "qcom,ipcc-self-ping";
interrupts-extended = <&ipcc_mproc IPCC_CLIENT_APSS
IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_LEVEL_HIGH>;
mboxes = <&ipcc_mproc IPCC_CLIENT_APSS IPCC_MPROC_SIGNAL_SMP2P>;
};
ipcc_self_ping_cdsp: ipcc-self-ping-cdsp {
compatible = "qcom,ipcc-self-ping";
interrupts-extended = <&ipcc_mproc IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_PING IRQ_TYPE_LEVEL_HIGH>;
mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_PING>;
};
ipcc_self_ping_adsp: ipcc-self-ping-adsp {
compatible = "qcom,ipcc-self-ping";
interrupts-extended = <&ipcc_mproc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_PING IRQ_TYPE_LEVEL_HIGH>;
mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_PING>;
};
ipcc_self_ping_slpi: ipcc-self-ping-slpi {
compatible = "qcom,ipcc-self-ping";
interrupts-extended = <&ipcc_mproc IPCC_CLIENT_SLPI
IPCC_MPROC_SIGNAL_PING IRQ_TYPE_LEVEL_HIGH>;
mboxes = <&ipcc_mproc IPCC_CLIENT_SLPI IPCC_MPROC_SIGNAL_PING>;
};
};

414
qcom/msm-arm-smmu-pineapple.dtsi Normal file
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@@ -0,0 +1,414 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
&soc {
kgsl_smmu: kgsl-smmu@3da0000 {
compatible = "qcom,qsmmu-v500", "qcom,adreno-smmu";
reg = <0x3da0000 0x40000>;
#iommu-cells = <2>;
qcom,use-3-lvl-tables;
#global-interrupts = <1>;
#size-cells = <1>;
#address-cells = <1>;
ranges;
dma-coherent;
qcom,regulator-names = "vdd";
vdd-supply = <&gpu_cc_cx_gdsc>;
clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
<&gpucc GPU_CC_AHB_CLK>;
clock-names =
"gpu_cc_hlos1_vote_gpu_smmu",
"gcc_gpu_memnoc_gfx",
"gcc_gpu_snoc_dvm_gfx",
"gpu_cc_ahb";
qcom,actlr =
/* All CBs of GFX: +15 deep PF */
<0x000 0x3ff 0x32B>;
interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>;
gpu_qtb: gpu_qtb@3de8000 {
compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
reg = <0x3de8000 0x1000>;
qcom,stream-id-range = <0x0 0x400>;
qcom,iova-width = <49>;
interconnects = <&gem_noc MASTER_GPU_TCU &mc_virt SLAVE_EBI1>;
qcom,num-qtb-ports = <2>;
};
};
ubwcp_smmu: ubwcp-smmu@179a0000 {
compatible = "qcom,qsmmu-v500";
reg = <0x179a0000 0x10000>;
#iommu-cells = <2>;
qcom,use-3-lvl-tables;
#global-interrupts = <1>;
#size-cells = <1>;
#address-cells = <1>;
ranges;
dma-coherent;
qcom,regulator-names = "vdd";
vdd-supply = <&apss_ubwcp_pwr_ctrl>;
qcom,actlr =
/* All CBs of UBWC-P: +15 deep PF */
<0x000 0x3ff 0x32B>;
qcom,ignore-numpagendxb;
interrupts = <GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 746 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 748 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 749 IRQ_TYPE_LEVEL_HIGH>;
ubwcp_qtb: ubwcp_qtb@179e8000 {
compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
reg = <0x179e8000 0x1000>;
qcom,stream-id-range = <0x0 0x2>;
qcom,iova-width = <36>;
qcom,num-qtb-ports = <1>;
};
};
apps_smmu: apps-smmu@15000000 {
compatible = "qcom,qsmmu-v500";
reg = <0x15000000 0x100000>;
#iommu-cells = <2>;
qcom,use-3-lvl-tables;
qcom,handoff-smrs = <0x1c00 0x2>;
#global-interrupts = <1>;
#size-cells = <1>;
#address-cells = <1>;
ranges;
dma-coherent;
qcom,actlr =
/* Camera IFE */
<0x0800 0x0020 0x00000001>,
/* Camera SBI */
<0x0840 0x0000 0x00000103>,
/* Camera IPE, BPS, CDM and ICP */
<0x1800 0x0000 0x00000001>,
<0x1820 0x0000 0x00000001>,
<0x1840 0x0000 0x00000001>,
<0x1860 0x0000 0x00000001>,
<0x1880 0x0000 0x00000001>,
<0x18c0 0x0000 0x00000001>,
/* Camera JPEG */
<0x18a0 0x0040 0x00000103>,
/* Compute */
<0x0c01 0x0020 0x00000303>,
<0x0c02 0x0020 0x00000303>,
<0x0c03 0x0020 0x00000303>,
<0x0c04 0x0020 0x00000303>,
<0x0c05 0x0020 0x00000303>,
<0x0c06 0x0020 0x00000303>,
<0x0c07 0x0020 0x00000303>,
<0x0c08 0x0020 0x00000303>,
<0x0c09 0x0020 0x00000303>,
<0x0c0c 0x0020 0x00000303>,
<0x0c0d 0x0020 0x00000303>,
<0x0c0e 0x0020 0x00000303>,
<0x1961 0x0000 0x00000303>,
<0x1962 0x0000 0x00000303>,
<0x1963 0x0000 0x00000303>,
<0x1964 0x0000 0x00000303>,
<0x1965 0x0000 0x00000303>,
<0x1966 0x0000 0x00000303>,
<0x1967 0x0000 0x00000303>,
<0x1968 0x0000 0x00000303>,
<0x1969 0x0000 0x00000303>,
<0x196c 0x0000 0x00000303>,
<0x196d 0x0000 0x00000303>,
<0x196e 0x0000 0x00000303>,
<0x19c1 0x0000 0x00000303>,
<0x19c2 0x0000 0x00000303>,
<0x19c3 0x0000 0x00000303>,
<0x19c4 0x0000 0x00000303>,
<0x19c5 0x0000 0x00000303>,
<0x19c6 0x0000 0x00000303>,
<0x19c7 0x0000 0x00000303>,
<0x19c8 0x0000 0x00000303>,
<0x19c9 0x0000 0x00000303>,
<0x19cc 0x0000 0x00000303>,
<0x19cd 0x0000 0x00000303>,
<0x19ce 0x0000 0x00000303>,
/* Display */
<0x1c00 0x0002 0x00000001>,
<0x1c01 0x0000 0x00000001>,
/* EVA */
<0x1920 0x0000 0x00000103>,
<0x1923 0x0000 0x00000103>,
<0x1924 0x0000 0x00000103>,
/* Video */
<0x1940 0x0000 0x00000103>,
<0x1941 0x0004 0x00000103>,
<0x1943 0x0000 0x00000103>,
<0x1944 0x0000 0x00000103>,
<0x1947 0x0000 0x00000103>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>;
anoc_1_qtb: anoc_1_qtb@16f1000 {
compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
reg = <0x16f1000 0x1000>;
qcom,stream-id-range = <0x0 0x400>;
qcom,iova-width = <36>;
interconnects = <&system_noc MASTER_A1NOC_SNOC &mc_virt SLAVE_EBI1>;
qcom,num-qtb-ports = <1>;
};
anoc_2_qtb: anoc_2_qtb@171a000 {
compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
reg = <0x171a000 0x1000>;
qcom,stream-id-range = <0x400 0x400>;
qcom,iova-width = <36>;
interconnects = <&system_noc MASTER_A2NOC_SNOC &mc_virt SLAVE_EBI1>;
qcom,num-qtb-ports = <1>;
};
cam_hf_qtb: cam_hf_qtb@17d2000 {
compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
reg = <0x17d2000 0x1000>;
qcom,stream-id-range = <0x800 0x400>;
qcom,iova-width = <36>;
interconnects = <&mmss_noc MASTER_CAMNOC_HF &mc_virt SLAVE_EBI1>;
qcom,num-qtb-ports = <2>;
};
nsp_qtb: nsp_qtb@7d3000 {
compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
reg = <0x7d3000 0x1000>;
qcom,stream-id-range = <0xc00 0x400>;
qcom,iova-width = <34>;
interconnects = <&nsp_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>;
qcom,num-qtb-ports = <2>;
};
lpass_qtb: lpass_qtb@7b3000 {
compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
reg = <0x7b3000 0x1000>;
qcom,stream-id-range = <0x1000 0x400>;
qcom,iova-width = <32>;
interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC &mc_virt SLAVE_EBI1>;
qcom,num-qtb-ports = <1>;
};
pcie_qtb: pcie_qtb@16cd000 {
compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
reg = <0x16cd000 0x1000>;
qcom,stream-id-range = <0x1400 0x400>;
qcom,iova-width = <36>;
interconnects = <&pcie_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
qcom,num-qtb-ports = <1>;
qcom,opt-out-tbu-halting;
};
sf_qtb: sf_qtb@17d1000 {
compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
reg = <0x17d1000 0x1000>;
qcom,stream-id-range = <0x1800 0x400>;
qcom,iova-width = <36>;
interconnects = <&mmss_noc MASTER_VIDEO &mc_virt SLAVE_EBI1>;
qcom,num-qtb-ports = <2>;
};
mdp_hf_qtb: mdp_hf_qtb@17d0000 {
compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
reg = <0x17d0000 0x1000>;
qcom,stream-id-range = <0x1c00 0x400>;
qcom,iova-width = <32>;
interconnects = <&mmss_noc MASTER_MDP &mc_virt SLAVE_EBI1>;
qcom,num-qtb-ports = <2>;
};
};
dma_dev {
compatible = "qcom,iommu-dma";
memory-region = <&system_cma>;
};
iommu_test_device {
compatible = "qcom,iommu-debug-test";
usecase0_apps {
compatible = "qcom,iommu-debug-usecase";
iommus = <&apps_smmu 0x400 0x0>;
};
usecase1_apps_fastmap {
compatible = "qcom,iommu-debug-usecase";
iommus = <&apps_smmu 0x400 0x0>;
qcom,iommu-dma = "fastmap";
};
usecase2_apps_atomic {
compatible = "qcom,iommu-debug-usecase";
iommus = <&apps_smmu 0x400 0x0>;
qcom,iommu-dma = "atomic";
};
usecase3_apps_dma {
compatible = "qcom,iommu-debug-usecase";
iommus = <&apps_smmu 0x400 0x0>;
dma-coherent;
};
usecase4_apps_secure {
compatible = "qcom,iommu-debug-usecase";
iommus = <&apps_smmu 0x400 0x0>;
qcom,iommu-vmid = <0xa>; /* VMID_CP_PIXEL */
};
usecase5_kgsl {
compatible = "qcom,iommu-debug-usecase";
iommus = <&kgsl_smmu 0x7 0x0>;
};
usecase6_kgsl_dma {
compatible = "qcom,iommu-debug-usecase";
iommus = <&kgsl_smmu 0x7 0x0>;
dma-coherent;
};
};
};

31
qcom/msm-rdbg.dtsi Normal file
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@@ -0,0 +1,31 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&soc {
/* smp2p information */
qcom,smp2p_interrupt_rdbg_2_out {
compatible = "qcom,smp2p-interrupt-rdbg-2-out";
qcom,smem-states = <&smp2p_rdbg2_out 0>;
qcom,smem-state-names = "rdbg-smp2p-out";
};
qcom,smp2p_interrupt_rdbg_2_in {
compatible = "qcom,smp2p-interrupt-rdbg-2-in";
interrupts-extended = <&smp2p_rdbg2_in 0 0>;
interrupt-names = "rdbg-smp2p-in";
};
qcom,smp2p_interrupt_rdbg_5_out {
compatible = "qcom,smp2p-interrupt-rdbg-5-out";
qcom,smem-states = <&smp2p_rdbg5_out 0>;
qcom,smem-state-names = "rdbg-smp2p-out";
};
qcom,smp2p_interrupt_rdbg_5_in {
compatible = "qcom,smp2p-interrupt-rdbg-5-in";
interrupts-extended = <&smp2p_rdbg5_in 0 0>;
interrupt-names = "rdbg-smp2p-in";
};
};

16
qcom/pineapple-atp-overlay.dts Normal file
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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "pineapple-atp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Pineapple ATP";
compatible = "qcom,pineapple-atp", "qcom,pineapple", "qcom,pineapplep-atp", "qcom,pineapple", "qcom,atp";
qcom,msm-id = <557 0x10000>, <557 0x20000>, <577 0x10000>, <577 0x20000>;
qcom,board-id = <0x10021 0>;
};

6
qcom/pineapple-atp.dtsi Normal file
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@@ -0,0 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "pineapple-mtp.dtsi"

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "pineapple-cdp-nfc.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Pineapple CDP ST54L NFC";
compatible = "qcom,pineapple-cdp", "qcom,pineapple", "qcom,pineapplep-cdp", "qcom,pineapplep", "qcom,cdp";
qcom,msm-id = <557 0x10000>, <557 0x20000>, <577 0x10000>, <577 0x20000>;
qcom,board-id = <0x50001 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "pineapple-cdp.dtsi"

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "pineapple-cdp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Pineapple CDP";
compatible = "qcom,pineapple-cdp", "qcom,pineapple", "qcom,pineapplep-cdp", "qcom,pineapplep", "qcom,cdp";
qcom,msm-id = <557 0x10000>, <557 0x20000>, <577 0x10000>, <577 0x20000>;
qcom,board-id = <1 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/clock/qcom,gcc-pineapple.h>
#include "pineapple-pmic-overlay.dtsi"
#include "pineapple-thermal-overlay.dtsi"
&sdhc_2 {
status = "ok";
vdd-supply = <&pm_humu_l9>;
qcom,vdd-voltage-level = <2950000 2960000>;
qcom,vdd-current-level = <0 800000>;
vdd-io-supply = <&pm_humu_l8>;
qcom,vdd-io-voltage-level = <1800000 2960000>;
qcom,vdd-io-current-level = <0 10000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>, <&sd_card_det_default>;
pinctrl-1 = <&sdc2_off>, <&sd_card_det_default>;
cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_LOW>;
resets = <&gcc GCC_SDCC2_BCR>;
reset-names = "core_reset";
qcom,iommu-dma = "fastmap";
};
&soc {
gpio_keys {
compatible = "gpio-keys";
label = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&key_vol_up_default>;
vol_up {
label = "volume_up";
gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
linux,code = <KEY_VOLUMEUP>;
gpio-key,wakeup;
debounce-interval = <15>;
linux,can-disable;
};
};
};
&ufsphy_mem {
compatible = "qcom,ufs-phy-qmp-v4-pineapple";
/* VDDA_UFS_CORE */
vdda-phy-supply = <&pm_v6d_l1>;
vdda-phy-max-microamp = <211000>;
/* VDDA_UFS_0_1P2 */
vdda-pll-supply = <&pm_v8_l3>;
vdda-pll-max-microamp = <18300>;
/* Phy GDSC for VDD_MX, always on */
vdd-phy-gdsc-supply = <&gcc_ufs_mem_phy_gdsc>;
/* Qref power supply, Refer Qref diagram */
vdda-qref-supply = <&pm_v8_l1>;
vdda-qref-max-microamp = <64500>;
status = "ok";
};
&ufshc_mem {
vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
vcc-supply = <&pm_humu_l17>;
vcc-max-microamp = <1300000>;
vccq-supply = <&pm_v6c_l1>;
vccq-max-microamp = <1200000>;
/* VDD_PX10 is voted for the ufs_reset_n */
qcom,vddp-ref-clk-supply = <&pm_v6c_l3>;
qcom,vddp-ref-clk-max-microamp = <100>;
qcom,vccq-parent-supply = <&pm_v6c_s1>;
qcom,vccq-parent-max-microamp = <210000>;
reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
resets = <&gcc GCC_UFS_PHY_BCR>;
reset-names = "rst";
status = "ok";
};
&pm8550_switch0 {
qcom,led-mask = <9>; /* Channels 1 & 4 */
qcom,symmetry-en;
};
&pm8550_switch1 {
qcom,led-mask = <6>; /* Channels 2 & 3 */
qcom,symmetry-en;
};
&pm8550_switch2 {
qcom,led-mask = <15>; /* All Channels */
qcom,symmetry-en;
};
&pm8550_flash {
status = "ok";
};
&eusb2_phy0 {
dummy-supply = <&pm8550b_eusb2_repeater>;
usb-repeater = <&pm8550b_eusb2_repeater>;
};
&usb0 {
usb-role-switch;
port {
usb_port0: endpoint {
remote-endpoint = <&usb_port0_connector>;
};
};
};
&ucsi {
connector {
port {
usb_port0_connector: endpoint {
remote-endpoint = <&usb_port0>;
};
};
};
};
&qupv3_se4_spi {
#address-cells = <1>;
#size-cells = <0>;
status = "ok";
qcom,touch-active = "goodix,gt9916S";
qcom,la-vm;
goodix-berlin@0 {
compatible = "goodix,gt9916S";
reg = <0>;
spi-max-frequency = <1000000>;
goodix,avdd-name = "avdd";
goodix,iovdd-name = "iovdd";
avdd-supply = <&L14B>;
iovdd-supply = <&L12B>;
interrupt-parent = <&tlmm>;
interrupts = <162 0x2008>;
goodix,reset-gpio = <&tlmm 161 0x00>;
goodix,irq-gpio = <&tlmm 162 0x2008>;
goodix,irq-flags = <2>;
goodix,panel-max-x = <1080>;
goodix,panel-max-y = <2400>;
goodix,panel-max-w = <255>;
goodix,panel-max-p = <4096>;
goodix,firmware-name = "goodix_firmware_spi.bin";
goodix,config-name = "goodix_cfg_group_spi.bin";
goodix,touch-type = "primary";
goodix,qts_en;
qts,trusted-touch-mode = "vm_mode";
qts,touch-environment = "pvm";
qts,trusted-touch-type = "primary";
qts,trusted-touch-spi-irq = <598>;
qts,trusted-touch-io-bases = <0xa90000>;
qts,trusted-touch-io-sizes = <0x1000>;
qts,trusted-touch-vm-gpio-list = <&tlmm 48 0 &tlmm 49 0 &tlmm 50 0
&tlmm 51 0 &tlmm 161 0 &tlmm 162 0x2008>;
};
};
&qupv3_se7_spi {
#address-cells = <1>;
#size-cells = <0>;
status = "ok";
qcom,touch-active = "goodix,gt9916S2";
qcom,la-vm;
goodix-berlin@0 {
compatible = "goodix,gt9916S2";
reg = <0>;
spi-max-frequency = <1000000>;
goodix,avdd-name = "avdd";
goodix,iovdd-name = "iovdd";
avdd-supply = <&L14B>;
iovdd-supply = <&L12B>;
interrupt-parent = <&tlmm>;
interrupts = <88 0x2008>;
goodix,reset-gpio = <&tlmm 91 0x00>;
goodix,irq-gpio = <&tlmm 88 0x2008>;
goodix,irq-flags = <2>;
goodix,panel-max-x = <1080>;
goodix,panel-max-y = <2400>;
goodix,panel-max-w = <255>;
goodix,panel-max-p = <4096>;
goodix,firmware-name = "goodix_firmware_spi.bin";
goodix,config-name = "goodix_cfg_group_spi.bin";
goodix,touch-type = "secondary";
goodix,qts_en;
qts,trusted-touch-mode = "vm_mode";
qts,touch-environment = "pvm";
qts,trusted-touch-type = "secondary";
qts,trusted-touch-spi-irq = <657>;
qts,trusted-touch-io-bases = <0xa90000>;
qts,trusted-touch-io-sizes = <0x1000>;
qts,trusted-touch-vm-gpio-list = <&tlmm 60 0 &tlmm 61 0 &tlmm 62 0
&tlmm 63 0 &tlmm 91 0 &tlmm 88 0x2008>;
};
};
&regulator_ocp_notifier {
periph-1c1-supply = <&L1B>;
periph-1c2-supply = <&L2B>;
periph-1c5-supply = <&L5B>;
periph-1c6-supply = <&L6B>;
periph-1c7-supply = <&L7B>;
periph-1c8-supply = <&L8B>;
periph-1c9-supply = <&L9B>;
periph-1ca-supply = <&L10B>;
periph-1cb-supply = <&L11B>;
periph-1cc-supply = <&L12B>;
periph-1cd-supply = <&L13B>;
periph-1ce-supply = <&L14B>;
periph-1cf-supply = <&L15B>;
periph-1d0-supply = <&L16B>;
periph-1d1-supply = <&L17B>;
periph-1e4-supply = <&BOB1>;
periph-1e6-supply = <&BOB2>;
periph-29b-supply = <&S1C>;
periph-29e-supply = <&S2C>;
periph-2a1-supply = <&S3C>;
periph-2a4-supply = <&S4C>;
periph-2a7-supply = <&S5C>;
periph-2aa-supply = <&S6C>;
periph-2c1-supply = <&L1C>;
periph-2c2-supply = <&L2C>;
periph-2c3-supply = <&L3C>;
periph-3a1-supply = <&S3D_LEVEL>;
periph-3a4-supply = <&S4D_LEVEL>;
periph-3a7-supply = <&S5D_LEVEL>;
periph-3c1-supply = <&L1D>;
periph-3c2-supply = <&L2D_LEVEL>;
periph-3c3-supply = <&L3D>;
periph-4c2-supply = <&L2E>;
periph-4c3-supply = <&L3E>;
periph-69b-supply = <&S1G_LEVEL>;
periph-6a1-supply = <&S3G>;
periph-6a4-supply = <&S4G_LEVEL>;
periph-6a7-supply = <&S5G_LEVEL>;
periph-6c1-supply = <&L1G>;
periph-6c2-supply = <&L2G>;
periph-6c3-supply = <&L3G>;
periph-89b-supply = <&S1I_LEVEL>;
periph-8a1-supply = <&S3I_LEVEL>;
periph-8a4-supply = <&S4I>;
periph-8a7-supply = <&S5I>;
periph-8aa-supply = <&S6I_LEVEL>;
periph-8b0-supply = <&S8I_LEVEL>;
periph-8c1-supply = <&L1I>;
periph-8c2-supply = <&L2I>;
periph-8c3-supply = <&L3I>;
periph-ac1-supply = <&L1K>;
periph-ac2-supply = <&L2K>;
periph-ac3-supply = <&L3K>;
periph-ac4-supply = <&L4K>;
periph-ac5-supply = <&L5K>;
periph-ac6-supply = <&L6K>;
periph-ac7-supply = <&L7K>;
periph-c40-supply = <&L1M>;
periph-c41-supply = <&L2M>;
periph-c42-supply = <&L3M>;
periph-c43-supply = <&L4M>;
periph-c44-supply = <&L5M>;
periph-c45-supply = <&L6M>;
periph-c46-supply = <&L7M>;
periph-d40-supply = <&L1N>;
periph-d41-supply = <&L2N>;
periph-d42-supply = <&L3N>;
periph-d43-supply = <&L4N>;
periph-d44-supply = <&L5N>;
periph-d45-supply = <&L6N>;
periph-d46-supply = <&L7N>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/arm/msm/qcom_dma_heap_dt_constants.h>
&soc {
qcom,dma-heaps {
compatible = "qcom,dma-heaps";
qcom,display {
qcom,dma-heap-name = "qcom,display";
qcom,dma-heap-type = <HEAP_TYPE_CMA>;
qcom,max-align = <9>;
memory-region = <&non_secure_display_memory>;
};
qcom,qseecom {
qcom,dma-heap-name = "qcom,qseecom";
qcom,dma-heap-type = <HEAP_TYPE_CMA>;
memory-region = <&qseecom_mem>;
};
qcom,qseecom_ta {
qcom,dma-heap-name = "qcom,qseecom-ta";
qcom,dma-heap-type = <HEAP_TYPE_CMA>;
memory-region = <&qseecom_ta_mem>;
};
qcom,sp_hlos {
qcom,dma-heap-name = "qcom,sp-hlos";
qcom,dma-heap-type = <HEAP_TYPE_CMA>;
memory-region = <&sp_mem>;
};
qcom,secure_sp_modem {
qcom,dma-heap-name = "qcom,secure-sp-modem";
qcom,dma-heap-type = <HEAP_TYPE_SECURE_CARVEOUT>;
memory-region = <&spu_modem_shared_mem>;
qcom,token = <0x10800000>;
};
qcom,secure_cdsp {
qcom,dma-heap-name = "qcom,cma-secure-cdsp";
qcom,dma-heap-type = <HEAP_TYPE_CMA>;
memory-region = <&cdsp_secure_heap_cma>;
};
qcom,secure_sp_tz {
qcom,dma-heap-name = "qcom,secure-sp-tz";
qcom,dma-heap-type = <HEAP_TYPE_SECURE_CARVEOUT>;
memory-region = <&spu_tz_shared_mem>;
qcom,token = <0x01000000>;
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&soc {
/* CAM_CC GDSCs */
cam_cc_bps_gdsc: qcom,gdsc@adf0004 {
compatible = "qcom,gdsc";
reg = <0xadf0004 0x4>;
regulator-name = "cam_cc_bps_gdsc";
qcom,retain-regs;
qcom,support-hw-trigger;
qcom,support-cfg-gdscr;
status = "disabled";
};
cam_cc_ife_0_gdsc: qcom,gdsc@adf1004 {
compatible = "qcom,gdsc";
reg = <0xadf1004 0x4>;
regulator-name = "cam_cc_ife_0_gdsc";
qcom,retain-regs;
qcom,support-cfg-gdscr;
status = "disabled";
};
cam_cc_ife_1_gdsc: qcom,gdsc@adf2004 {
compatible = "qcom,gdsc";
reg = <0xadf2004 0x4>;
regulator-name = "cam_cc_ife_1_gdsc";
qcom,retain-regs;
qcom,support-cfg-gdscr;
status = "disabled";
};
cam_cc_ife_2_gdsc: qcom,gdsc@adf2054 {
compatible = "qcom,gdsc";
reg = <0xadf2054 0x4>;
regulator-name = "cam_cc_ife_2_gdsc";
qcom,retain-regs;
qcom,support-cfg-gdscr;
status = "disabled";
};
cam_cc_ipe_0_gdsc: qcom,gdsc@adf0080 {
compatible = "qcom,gdsc";
reg = <0xadf0080 0x4>;
regulator-name = "cam_cc_ipe_0_gdsc";
qcom,retain-regs;
qcom,support-hw-trigger;
qcom,support-cfg-gdscr;
status = "disabled";
};
cam_cc_sbi_gdsc: qcom,gdsc@adf00e4 {
compatible = "qcom,gdsc";
reg = <0xadf00e4 0x4>;
regulator-name = "cam_cc_sbi_gdsc";
qcom,retain-regs;
qcom,support-cfg-gdscr;
status = "disabled";
};
cam_cc_sfe_0_gdsc: qcom,gdsc@adf3058 {
compatible = "qcom,gdsc";
reg = <0xadf3058 0x4>;
regulator-name = "cam_cc_sfe_0_gdsc";
qcom,retain-regs;
qcom,support-cfg-gdscr;
status = "disabled";
};
cam_cc_sfe_1_gdsc: qcom,gdsc@adf30a8 {
compatible = "qcom,gdsc";
reg = <0xadf30a8 0x4>;
regulator-name = "cam_cc_sfe_1_gdsc";
qcom,retain-regs;
qcom,support-cfg-gdscr;
status = "disabled";
};
cam_cc_sfe_2_gdsc: qcom,gdsc@adf30f8 {
compatible = "qcom,gdsc";
reg = <0xadf30f8 0x4>;
regulator-name = "cam_cc_sfe_2_gdsc";
qcom,retain-regs;
qcom,support-cfg-gdscr;
status = "disabled";
};
cam_cc_titan_top_gdsc: qcom,gdsc@adf32bc {
compatible = "qcom,gdsc";
reg = <0xadf32bc 0x4>;
regulator-name = "cam_cc_titan_top_gdsc";
qcom,retain-regs;
qcom,support-cfg-gdscr;
status = "disabled";
};
/* DISP_CC GDSCs */
disp_cc_mdss_core_gdsc: qcom,gdsc@af09000 {
compatible = "qcom,gdsc";
reg = <0xaf09000 0x4>;
regulator-name = "disp_cc_mdss_core_gdsc";
proxy-supply = <&disp_cc_mdss_core_gdsc>;
qcom,proxy-consumer-enable;
qcom,support-hw-trigger;
qcom,retain-regs;
qcom,support-cfg-gdscr;
status = "disabled";
};
disp_cc_mdss_core_int2_gdsc: qcom,gdsc@af0b000 {
compatible = "qcom,gdsc";
reg = <0xaf0b000 0x4>;
regulator-name = "disp_cc_mdss_core_int2_gdsc";
qcom,support-hw-trigger;
qcom,retain-regs;
qcom,support-cfg-gdscr;
status = "disabled";
};
gcc_apcs_gdsc_vote_ctrl: syscon@15214c {
compatible = "syscon";
reg = <0x15214c 0x4>;
};
apss_ubwcp_pwr_ctrl: qcom,gdsc@17891000 {
compatible = "qcom,gdsc";
reg = <0x17891000 0x4>;
regulator-name = "apss_ubwcp_pwr_ctrl";
qcom,no-status-check-on-disable;
status = "disabled";
};
/* GCC GDSCs */
gcc_pcie_0_gdsc: qcom,gdsc@16b004 {
compatible = "qcom,gdsc";
reg = <0x16b004 0x4>;
regulator-name = "gcc_pcie_0_gdsc";
qcom,retain-regs;
qcom,no-status-check-on-disable;
qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 0>;
qcom,support-cfg-gdscr;
status = "disabled";
};
gcc_pcie_0_phy_gdsc: qcom,gdsc@16c000 {
compatible = "qcom,gdsc";
reg = <0x16c000 0x4>;
regulator-name = "gcc_pcie_0_phy_gdsc";
qcom,retain-regs;
qcom,no-status-check-on-disable;
qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 3>;
qcom,support-cfg-gdscr;
status = "disabled";
};
gcc_pcie_1_gdsc: qcom,gdsc@18d004 {
compatible = "qcom,gdsc";
reg = <0x18d004 0x4>;
regulator-name = "gcc_pcie_1_gdsc";
qcom,retain-regs;
qcom,no-status-check-on-disable;
qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 1>;
qcom,support-cfg-gdscr;
status = "disabled";
};
gcc_pcie_1_phy_gdsc: qcom,gdsc@18e000 {
compatible = "qcom,gdsc";
reg = <0x18e000 0x4>;
regulator-name = "gcc_pcie_1_phy_gdsc";
qcom,retain-regs;
qcom,no-status-check-on-disable;
qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 4>;
qcom,support-cfg-gdscr;
status = "disabled";
};
gcc_ufs_mem_phy_gdsc: qcom,gdsc@19e000 {
compatible = "qcom,gdsc";
reg = <0x19e000 0x4>;
regulator-name = "gcc_ufs_mem_phy_gdsc";
proxy-supply = <&gcc_ufs_mem_phy_gdsc>;
qcom,proxy-consumer-enable;
qcom,retain-regs;
qcom,support-cfg-gdscr;
status = "disabled";
};
gcc_ufs_phy_gdsc: qcom,gdsc@177004 {
compatible = "qcom,gdsc";
reg = <0x177004 0x4>;
regulator-name = "gcc_ufs_phy_gdsc";
proxy-supply = <&gcc_ufs_phy_gdsc>;
qcom,proxy-consumer-enable;
qcom,retain-regs;
qcom,support-cfg-gdscr;
status = "disabled";
};
gcc_usb30_prim_gdsc: qcom,gdsc@139004 {
compatible = "qcom,gdsc";
reg = <0x139004 0x4>;
regulator-name = "gcc_usb30_prim_gdsc";
proxy-supply = <&gcc_usb30_prim_gdsc>;
qcom,proxy-consumer-enable;
qcom,retain-regs;
qcom,support-cfg-gdscr;
status = "disabled";
};
gcc_usb3_phy_gdsc: qcom,gdsc@150018 {
compatible = "qcom,gdsc";
reg = <0x150018 0x4>;
regulator-name = "gcc_usb3_phy_gdsc";
proxy-supply = <&gcc_usb3_phy_gdsc>;
qcom,proxy-consumer-enable;
qcom,retain-regs;
qcom,support-cfg-gdscr;
status = "disabled";
};
/* GPU_CC GDSCs */
gpu_cc_cx_gdsc_hw_ctrl: syscon@3d99168 {
compatible = "syscon";
reg = <0x3d99168 0x4>;
};
gpu_cc_cx_gdsc: qcom,gdsc@3d99108 {
compatible = "qcom,gdsc";
reg = <0x3d99108 0x4>;
regulator-name = "gpu_cc_cx_gdsc";
hw-ctrl-addr = <&gpu_cc_cx_gdsc_hw_ctrl>;
qcom,no-status-check-on-disable;
qcom,clk-dis-wait-val = <8>;
qcom,retain-regs;
qcom,support-cfg-gdscr;
status = "disabled";
};
gpu_cc_gx_domain_addr: syscon@3d99504 {
compatible = "syscon";
reg = <0x3d99504 0x4>;
};
gpu_cc_gx_sw_reset: syscon@3d99058 {
compatible = "syscon";
reg = <0x3d99058 0x4>;
};
gpu_cc_gx_acd_reset: syscon@3d99358 {
compatible = "syscon";
reg = <0x3d99358 0x4>;
};
gpu_cc_gx_acd_iroot_reset: syscon@3d9958c {
compatible = "syscon";
reg = <0x3d9958c 0x4>;
};
gpu_cc_gx_gdsc: qcom,gdsc@3d9905c {
compatible = "qcom,gdsc";
reg = <0x3d9905c 0x4>;
regulator-name = "gpu_cc_gx_gdsc";
domain-addr = <&gpu_cc_gx_domain_addr>;
sw-reset = <&gpu_cc_gx_sw_reset>,
<&gpu_cc_gx_acd_reset>,
<&gpu_cc_gx_acd_iroot_reset>;
qcom,reset-aon-logic;
qcom,retain-regs;
qcom,support-cfg-gdscr;
status = "disabled";
};
/* VIDEO_CC GDSCs */
video_cc_mvs0_gdsc: qcom,gdsc@aaf80a4 {
compatible = "qcom,gdsc";
reg = <0xaaf80a4 0x4>;
regulator-name = "video_cc_mvs0_gdsc";
qcom,retain-regs;
qcom,support-hw-trigger;
qcom,support-cfg-gdscr;
status = "disabled";
};
video_cc_mvs0c_gdsc: qcom,gdsc@aaf804c {
compatible = "qcom,gdsc";
reg = <0xaaf804c 0x4>;
regulator-name = "video_cc_mvs0c_gdsc";
qcom,retain-regs;
qcom,support-cfg-gdscr;
status = "disabled";
};
video_cc_mvs1_gdsc: qcom,gdsc@aaf80cc {
compatible = "qcom,gdsc";
reg = <0xaaf80cc 0x4>;
regulator-name = "video_cc_mvs1_gdsc";
qcom,retain-regs;
qcom,support-hw-trigger;
qcom,support-cfg-gdscr;
status = "disabled";
};
video_cc_mvs1c_gdsc: qcom,gdsc@aaf8078 {
compatible = "qcom,gdsc";
reg = <0xaaf8078 0x4>;
regulator-name = "video_cc_mvs1c_gdsc";
qcom,retain-regs;
qcom,support-cfg-gdscr;
status = "disabled";
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "pineapple-mtp-nfc.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Pineapple MTP ST54L NFC";
compatible = "qcom,pineapple-mtp", "qcom,pineapple", "qcom,pineapplep-mtp", "qcom,pineapplep", "qcom,mtp";
qcom,msm-id = <557 0x10000>, <557 0x20000>, <577 0x10000>, <577 0x20000>;
qcom,board-id = <0x50008 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "pineapple-mtp.dtsi"

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "pineapple-mtp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Pineapple MTP";
compatible = "qcom,pineapple-mtp", "qcom,pineapple", "qcom,pineapplep-mtp", "qcom,pineapplep", "qcom,mtp";
qcom,msm-id = <557 0x10000>, <557 0x20000>, <577 0x10000>, <577 0x20000>;
qcom,board-id = <8 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/clock/qcom,gcc-pineapple.h>
#include "pineapple-pmic-overlay.dtsi"
#include "pineapple-thermal-overlay.dtsi"
&sdhc_2 {
status = "ok";
vdd-supply = <&pm_humu_l9>;
qcom,vdd-voltage-level = <2950000 2960000>;
qcom,vdd-current-level = <0 800000>;
vdd-io-supply = <&pm_humu_l8>;
qcom,vdd-io-voltage-level = <1800000 2960000>;
qcom,vdd-io-current-level = <0 10000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>, <&sd_card_det_default>;
pinctrl-1 = <&sdc2_off>, <&sd_card_det_default>;
cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_LOW>;
resets = <&gcc GCC_SDCC2_BCR>;
reset-names = "core_reset";
qcom,iommu-dma = "fastmap";
};
&soc {
gpio_keys {
compatible = "gpio-keys";
label = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&key_vol_up_default>;
vol_up {
label = "volume_up";
gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
linux,code = <KEY_VOLUMEUP>;
gpio-key,wakeup;
debounce-interval = <15>;
linux,can-disable;
};
};
};
&ufsphy_mem {
compatible = "qcom,ufs-phy-qmp-v4-pineapple";
/* VDDA_UFS_CORE */
vdda-phy-supply = <&pm_v6d_l1>;
vdda-phy-max-microamp = <211000>;
/* VDDA_UFS_0_1P2 */
vdda-pll-supply = <&pm_v8_l3>;
vdda-pll-max-microamp = <18300>;
/* Phy GDSC for VDD_MX, always on */
vdd-phy-gdsc-supply = <&gcc_ufs_mem_phy_gdsc>;
/* Qref power supply, Refer Qref diagram */
vdda-qref-supply = <&pm_v8_l1>;
vdda-qref-max-microamp = <64500>;
status = "ok";
};
&ufshc_mem {
vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
vcc-supply = <&pm_humu_l17>;
vcc-max-microamp = <1300000>;
vccq-supply = <&pm_v6c_l1>;
vccq-max-microamp = <1200000>;
/* VDD_PX10 is voted for the ufs_reset_n */
qcom,vddp-ref-clk-supply = <&pm_v6c_l3>;
qcom,vddp-ref-clk-max-microamp = <100>;
qcom,vccq-parent-supply = <&pm_v6c_s1>;
qcom,vccq-parent-max-microamp = <210000>;
reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
resets = <&gcc GCC_UFS_PHY_BCR>;
reset-names = "rst";
status = "ok";
};
&pm8550_switch0 {
qcom,led-mask = <9>; /* Channels 1 & 4 */
qcom,symmetry-en;
};
&pm8550_switch1 {
qcom,led-mask = <6>; /* Channels 2 & 3 */
qcom,symmetry-en;
};
&pm8550_switch2 {
qcom,led-mask = <15>; /* All Channels */
qcom,symmetry-en;
};
&pm8550_flash {
status = "ok";
};
&battery_charger {
qcom,wireless-fw-name = "idt9418.bin";
qcom,thermal-mitigation = <3000000 1500000 1000000 500000>;
#cooling-cells = <2>;
};
&pmic_glink_debug {
i2c@107 {
reg = <0x107>; /* I2C instance 7 in ADSP for SE6 */
#address-cells = <1>;
#size-cells = <0>;
qcom,bus-type = "i2c";
qcom,smb1502@68 {
compatible = "qcom,i2c-pmic";
reg = <0x68>;
qcom,can-sleep;
};
qcom,smb1502@69 {
compatible = "qcom,i2c-pmic";
reg = <0x69>;
qcom,can-sleep;
};
qcom,idt9418@3b {
compatible = "qcom,i2c-pmic";
reg = <0x3b>;
qcom,can-sleep;
};
};
};
&pmic_glink_adc {
status = "ok";
smb1502_1_iin {
reg = <0x1076801>;
label = "smb1502_1_iin";
};
smb1502_1_ichg {
reg = <0x1076802>;
label = "smb1502_1_ichg";
};
smb1502_1_die_temp {
reg = <0x1076803>;
label = "smb1502_1_die_temp";
};
smb1502_2_iin {
reg = <0x1076901>;
label = "smb1502_2_iin";
};
smb1502_2_ichg {
reg = <0x1076902>;
label = "smb1502_2_ichg";
};
smb1502_2_die_temp {
reg = <0x1076903>;
label = "smb1502_2_die_temp";
};
};
&eusb2_phy0 {
dummy-supply = <&pm8550b_eusb2_repeater>;
usb-repeater = <&pm8550b_eusb2_repeater>;
};
&usb0 {
usb-role-switch;
port {
usb_port0: endpoint {
remote-endpoint = <&usb_port0_connector>;
};
};
};
&ucsi {
connector {
port {
usb_port0_connector: endpoint {
remote-endpoint = <&usb_port0>;
};
};
};
};
&qupv3_se4_spi {
#address-cells = <1>;
#size-cells = <0>;
status = "ok";
qcom,touch-active = "goodix,gt9916S";
qcom,la-vm;
goodix-berlin@0 {
compatible = "goodix,gt9916S";
reg = <0>;
spi-max-frequency = <1000000>;
interrupt-parent = <&tlmm>;
interrupts = <162 0x2008>;
goodix,reset-gpio = <&tlmm 161 0x00>;
goodix,irq-gpio = <&tlmm 162 0x2008>;
goodix,irq-flags = <2>;
goodix,panel-max-x = <1080>;
goodix,panel-max-y = <2400>;
goodix,panel-max-w = <255>;
goodix,panel-max-p = <4096>;
goodix,firmware-name = "goodix_firmware_spi.bin";
goodix,config-name = "goodix_cfg_group_spi.bin";
goodix,avdd-name = "avdd";
goodix,iovdd-name = "iovdd";
avdd-supply = <&L14B>;
iovdd-supply = <&L12B>;
goodix,touch-type = "primary";
goodix,qts_en;
qts,trusted-touch-mode = "vm_mode";
qts,touch-environment = "pvm";
qts,trusted-touch-type = "primary";
qts,trusted-touch-spi-irq = <598>;
qts,trusted-touch-io-bases = <0xa90000>;
qts,trusted-touch-io-sizes = <0x1000>;
qts,trusted-touch-vm-gpio-list = <&tlmm 48 0 &tlmm 49 0 &tlmm 50 0
&tlmm 51 0 &tlmm 161 0 &tlmm 162 0x2008>;
};
};
&regulator_ocp_notifier {
periph-1c1-supply = <&L1B>;
periph-1c2-supply = <&L2B>;
periph-1c5-supply = <&L5B>;
periph-1c6-supply = <&L6B>;
periph-1c7-supply = <&L7B>;
periph-1c8-supply = <&L8B>;
periph-1c9-supply = <&L9B>;
periph-1ca-supply = <&L10B>;
periph-1cb-supply = <&L11B>;
periph-1cc-supply = <&L12B>;
periph-1cd-supply = <&L13B>;
periph-1ce-supply = <&L14B>;
periph-1cf-supply = <&L15B>;
periph-1d0-supply = <&L16B>;
periph-1d1-supply = <&L17B>;
periph-1e4-supply = <&BOB1>;
periph-1e6-supply = <&BOB2>;
periph-29b-supply = <&S1C>;
periph-29e-supply = <&S2C>;
periph-2a1-supply = <&S3C>;
periph-2a4-supply = <&S4C>;
periph-2a7-supply = <&S5C>;
periph-2aa-supply = <&S6C>;
periph-2c1-supply = <&L1C>;
periph-2c2-supply = <&L2C>;
periph-2c3-supply = <&L3C>;
periph-3a1-supply = <&S3D_LEVEL>;
periph-3a4-supply = <&S4D_LEVEL>;
periph-3a7-supply = <&S5D_LEVEL>;
periph-3c1-supply = <&L1D>;
periph-3c2-supply = <&L2D_LEVEL>;
periph-3c3-supply = <&L3D>;
periph-4c2-supply = <&L2E>;
periph-4c3-supply = <&L3E>;
periph-69b-supply = <&S1G_LEVEL>;
periph-6a1-supply = <&S3G>;
periph-6a4-supply = <&S4G_LEVEL>;
periph-6a7-supply = <&S5G_LEVEL>;
periph-6c1-supply = <&L1G>;
periph-6c2-supply = <&L2G>;
periph-6c3-supply = <&L3G>;
periph-89b-supply = <&S1I_LEVEL>;
periph-8a1-supply = <&S3I_LEVEL>;
periph-8a4-supply = <&S4I>;
periph-8a7-supply = <&S5I>;
periph-8aa-supply = <&S6I_LEVEL>;
periph-8b0-supply = <&S8I_LEVEL>;
periph-8c1-supply = <&L1I>;
periph-8c2-supply = <&L2I>;
periph-8c3-supply = <&L3I>;
periph-ac1-supply = <&L1K>;
periph-ac2-supply = <&L2K>;
periph-ac3-supply = <&L3K>;
periph-ac4-supply = <&L4K>;
periph-ac5-supply = <&L5K>;
periph-ac6-supply = <&L6K>;
periph-ac7-supply = <&L7K>;
periph-c40-supply = <&L1M>;
periph-c41-supply = <&L2M>;
periph-c42-supply = <&L3M>;
periph-c43-supply = <&L4M>;
periph-c44-supply = <&L5M>;
periph-c45-supply = <&L6M>;
periph-c46-supply = <&L7M>;
periph-d40-supply = <&L1N>;
periph-d41-supply = <&L2N>;
periph-d42-supply = <&L3N>;
periph-d43-supply = <&L4N>;
periph-d44-supply = <&L5N>;
periph-d45-supply = <&L6N>;
periph-d46-supply = <&L7N>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/clock/qcom,gcc-pineapple.h>
#include <dt-bindings/gpio/gpio.h>
&soc {
pcie0: qcom,pcie@1c00000 {
compatible = "qcom,pci-msm";
reg = <0x01c00000 0x3000>,
<0x01c06000 0x2000>,
<0x60000000 0xf1d>,
<0x60000f20 0xa8>,
<0x60001000 0x1000>,
<0x60100000 0x100000>,
<0x01D07000 0x7000>;
reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf",
"pcie_sm";
cell-index = <0>;
linux,pci-domain = <0>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>,
<0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
"int_d";
msi-map = <0x0 &gic_its 0x1400 0x1>,
<0x100 &gic_its 0x1401 0x1>; /* 32 event IDs */
qcom,pcie-clkreq-gpio = <95>;
perst-gpio = <&tlmm 94 GPIO_ACTIVE_HIGH>;
wake-gpio = <&tlmm 96 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pcie0_perst_default
&pcie0_clkreq_default
&pcie0_wake_default>;
pinctrl-1 = <&pcie0_perst_default
&pcie0_clkreq_sleep
&pcie0_wake_default>;
qcom,bw-scale = /* Gen1 */
<RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
19200000
/* Gen2 */
RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
19200000
/* Gen3 */
RPMH_REGULATOR_LEVEL_NOM
RPMH_REGULATOR_LEVEL_NOM
100000000>;
interconnect-names = "icc_path";
interconnects = <&pcie_noc MASTER_PCIE_0_PCIE_CRM_HW_0
&mc_virt SLAVE_EBI1_PCIE_CRM_HW_0>;
gdsc-phy-vdd-supply = <&gcc_pcie_0_phy_gdsc>;
clocks = <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;
clock-names = "gcc_cnoc_pcie_sf_axi_clk";
clock-frequency = <0>;
clock-suppressible = <1>;
resets = <&gcc GCC_PCIE_0_BCR>,
<&gcc GCC_PCIE_0_PHY_BCR>;
reset-names = "pcie_0_core_reset",
"pcie_0_phy_reset";
dma-coherent;
qcom,smmu-sid-base = <0x1400>;
iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
<0x100 &apps_smmu 0x1401 0x1>;
qcom,boot-option = <0x1>;
qcom,aux-clk-freq = <20>; /* 19.2 MHz */
qcom,drv-supported;
qcom,drv-l1ss-timeout-us = <5000>;
qcom,l1-2-th-scale = <2>;
qcom,l1-2-th-value = <150>;
qcom,slv-addr-space-size = <0x4000000>;
qcom,ep-latency = <10>;
qcom,num-parf-testbus-sel = <0xb9>;
qcom,pcie-phy-ver = <104>;
qcom,phy-status-offset = <0x214>;
qcom,phy-status-bit = <6>;
qcom,phy-power-down-offset = <0x240>;
qcom,phy-sequence = <0x0240 0x03 0x0
0x00c0 0x01 0x0
0x00cc 0x62 0x0
0x00d0 0x02 0x0
0x0060 0xf8 0x0
0x0064 0x01 0x0
0x0000 0x93 0x0
0x0004 0x01 0x0
0x00e0 0x90 0x0
0x00e4 0x82 0x0
0x00f4 0x07 0x0
0x0070 0x02 0x0
0x0010 0x02 0x0
0x0074 0x16 0x0
0x0014 0x16 0x0
0x0078 0x36 0x0
0x0018 0x36 0x0
0x0110 0x08 0x0
0x00bc 0x0a 0x0
0x0120 0x42 0x0
0x0080 0x04 0x0
0x0084 0x0d 0x0
0x0020 0x0a 0x0
0x0024 0x1a 0x0
0x0088 0x41 0x0
0x0028 0x34 0x0
0x0090 0xab 0x0
0x0094 0xaa 0x0
0x0098 0x01 0x0
0x0030 0x55 0x0
0x0034 0x55 0x0
0x0038 0x01 0x0
0x0140 0x14 0x0
0x0164 0x34 0x0
0x003c 0x01 0x0
0x001c 0x04 0x0
0x0174 0x16 0x0
0x01bc 0x0f 0x0
0x0170 0xa0 0x0
0x11a4 0x38 0x0
0x10dc 0x11 0x0
0x1160 0xbf 0x0
0x1164 0xbf 0x0
0x1168 0xb7 0x0
0x116c 0xea 0x0
0x115c 0x3f 0x0
0x1174 0x5c 0x0
0x1178 0x9c 0x0
0x117c 0x1a 0x0
0x1180 0x89 0x0
0x1170 0xdc 0x0
0x1188 0x94 0x0
0x118c 0x5b 0x0
0x1190 0x1a 0x0
0x1194 0x89 0x0
0x10cc 0x00 0x0
0x1008 0x09 0x0
0x1014 0x05 0x0
0x104c 0x08 0x0
0x1050 0x08 0x0
0x10d8 0x0f 0x0
0x1118 0x1c 0x0
0x10f8 0x07 0x0
0x11f8 0x08 0x0
0x1600 0x00 0x0
0x0e84 0x15 0x0
0x0e90 0x3f 0x0
0x0ee4 0x02 0x0
0x0e40 0x09 0x0
0x0e3c 0x15 0x0
0x19a4 0x38 0x0
0x18dc 0x11 0x0
0x1960 0xbf 0x0
0x1964 0xbf 0x0
0x1968 0xb7 0x0
0x196c 0xea 0x0
0x195c 0x3f 0x0
0x1974 0x5c 0x0
0x1978 0x9c 0x0
0x197c 0x1a 0x0
0x1980 0x89 0x0
0x1970 0xdc 0x0
0x1988 0x94 0x0
0x198c 0x5b 0x0
0x1990 0x1a 0x0
0x1994 0x89 0x0
0x18cc 0x00 0x0
0x1808 0x09 0x0
0x1814 0x05 0x0
0x184c 0x08 0x0
0x1850 0x08 0x0
0x18d8 0x0f 0x0
0x1918 0x1c 0x0
0x18f8 0x07 0x0
0x19f8 0x08 0x0
0x1684 0x15 0x0
0x1690 0x3f 0x0
0x16e4 0x02 0x0
0x1640 0x09 0x0
0x163c 0x15 0x0
0x02dc 0x05 0x0
0x0388 0x77 0x0
0x0398 0x0b 0x0
0x06a4 0x1e 0x0
0x06f4 0x27 0x0
0x03e0 0x0f 0x0
0x060c 0x1d 0x0
0x0614 0x07 0x0
0x0620 0xc1 0x0
0x0694 0x00 0x0
0x03d0 0x8c 0x0
0x0368 0x17 0x0
0x0200 0x00 0x0
0x0244 0x03 0x0>;
qcom,parf-debug-reg = <0x01b0 0x0024 0x0028 0x0224 0x0500
0x04d0 0x04d4 0x03c0 0x0630 0x0230
0x0000>;
qcom,dbi-debug-reg = <0x0104 0x0110 0x0080 0x01f4 0x0730
0x0734 0x0738 0x073c>;
qcom,phy-debug-reg = <0x01cc 0x01d0 0x01d4 0x01d8 0x01dc
0x01e0 0x01e4 0x01f8 0x0ed0 0x16d0
0x0edc 0x16dc 0x11e0 0x19e0 0x0a00
0x1200 0x0a04 0x1204 0x0a08 0x1208
0x0a0c 0x120c 0x0a10 0x1210 0x0a14
0x1214 0x0a18 0x1218 0x0c20 0x1420
0x0214 0x0218 0x021c 0x0220 0x0224
0x0228 0x022c 0x0230 0x0234 0x0238
0x023c 0x0600 0x0604>;
qcom,pcie-sm-branch-offset = <0x1000>;
qcom,pcie-sm-start-offset = <0x1090>;
qcom,pcie-sm-seq = <0x1c018081>, <0x70074002>, <0x50028000>,
<0x28007003>, <0x80804002>, <0x70021c01>,
<0x18001802>, <0x70005000>, <0x10004000>,
<0x80814002>, <0x18001c01>, <0x1c018080>,
<0x0000100>;
qcom,pcie-sm-branch-seq = <0x4>, <0x1c>, <0x24>, <0x2c>, <0x0>,
<0x0>, <0x0>;
qcom,pcie-sm-debug = <0x1040>, /* PCIE_SMs_SEQ_OVERRIDE_PWR_CTRL_VAL */
<0x1048>, /* PCIE_SMs_SEQ_OVERRIDE_PWR_CTRL_MASK */
<0x1050>, /* PCIE_SMs_SEQ_OVERRIDE_WAIT_EVENT_VAL */
<0x1058>, /* PCIE_SMs_SEQ_OVERRIDE_WAIT_EVENT_MASK */
<0x1060>, /* PCIE_SMs_SEQ_OVERRIDE_BR_EVENT_VAL */
<0x1068>, /* PCIE_SMs_SEQ_OVERRIDE_BR_EVENT_MASK */
<0x1070>, /* PCIE_SMs_SEQ_PWR_CTRL_STATUS */
<0x1078>, /* PCIE_SMs_SEQ_WAIT_EVENT_STATUS */
<0x1080>, /* PCIE_SMs_SEQ_BR_EVENT_STATUS */
<0x1088>, /* PCIE_SMs_SEQ_PC_VAL */
<0x1090>, /* PCIE_SMs_SEQ_START */
<0x1094>, /* PCIE_SMs_CLKREQ_GATE */
<0x1098>, /* PCIE_SMs_CLKREQ_UNGATE */
<0x109C>; /* PCIE_SMs_CLKREQ_GATE_REQ_STATUS */
pcie0_rp: pcie0_rp {
reg = <0 0 0 0 0>;
};
};
pcie0_msi: qcom,pcie0_msi@0x17110040 {
compatible = "qcom,pci-msi";
msi-controller;
reg = <0x17110040 0x0>;
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
pcie1: qcom,pcie@1c08000 {
compatible = "qcom,pci-msm";
reg = <0x01c08000 0x3000>,
<0x01c0e000 0x2000>,
<0x40000000 0xf1d>,
<0x40000f20 0xa8>,
<0x40001000 0x1000>,
<0x40100000 0x100000>;
reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";
cell-index = <1>;
linux,pci-domain = <1>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>,
<0x02000000 0x0 0x40300000 0x40300000 0x0 0x1fd00000>;
interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
"int_d";
msi-map = <0x0 &gic_its 0x1480 0x1>,
<0x100 &gic_its 0x1481 0x1>; /* 32 event IDs */
perst-gpio = <&tlmm 97 0>;
wake-gpio = <&tlmm 99 0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pcie1_perst_default
&pcie1_clkreq_default
&pcie1_wake_default>;
pinctrl-1 = <&pcie1_perst_default
&pcie1_clkreq_sleep
&pcie1_wake_default>;
gdsc-core-vdd-supply = <&gcc_pcie_1_gdsc>;
gdsc-phy-vdd-supply = <&gcc_pcie_1_phy_gdsc>;
vreg-1p2-supply = <&pm_v8_l3>;
vreg-0p9-supply = <&pm_v6e_l3>;
vreg-qref-supply = <&pm_v8_l1>;
vreg-cx-supply = <&VDD_CX_LEVEL>;
vreg-mx-supply = <&VDD_MXA_LEVEL>;
qcom,vreg-1p2-voltage-level = <1200000 1200000 26100>;
qcom,vreg-0p9-voltage-level = <912000 880000 193000>;
qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
RPMH_REGULATOR_LEVEL_NOM 0>;
qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
RPMH_REGULATOR_LEVEL_NOM 0>;
qcom,vreg-qref-voltage-level = <880000 880000 25700>;
qcom,bw-scale = /* Gen1 */
<RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
19200000
/* Gen2 */
RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
19200000
/* Gen3 */
RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
100000000
/* Gen4 */
RPMH_REGULATOR_LEVEL_NOM
RPMH_REGULATOR_LEVEL_NOM
100000000>;
interconnect-names = "icc_path";
interconnects = <&pcie_noc MASTER_PCIE_1 &mc_virt SLAVE_EBI1>;
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_PCIE_1_AUX_CLK>,
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
<&tcsrcc TCSR_PCIE_1_CLKREF_EN>,
<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
<&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
<&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
<&gcc GCC_CNOC_PCIE_SF_AXI_CLK>,
<&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
<&pcie_1_pipe_clk>,
<&gcc GCC_PCIE_1_PHY_AUX_CLK>;
clock-names = "pcie_pipe_clk", "pcie_ref_clk_src",
"pcie_aux_clk", "pcie_cfg_ahb_clk",
"pcie_mstr_axi_clk", "pcie_slv_axi_clk",
"pcie_clkref_en", "pcie_slv_q2a_axi_clk",
"pcie_rate_change_clk",
"gcc_ddrss_pcie_sf_qtb_clk",
"pcie_aggre_noc_axi_clk",
"gcc_cnoc_pcie_sf_axi_clk", "pcie_pipe_clk_mux",
"pcie_pipe_clk_ext_src", "pcie_phy_aux_clk";
clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>, <0>,
<0>, <100000000>, <0>, <0>, <0>, <0>, <0>, <0>;
clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>,
<0>, <0>, <0>, <1>, <0>, <0>, <0>;
resets = <&gcc GCC_PCIE_1_BCR>,
<&gcc GCC_PCIE_1_PHY_BCR>,
<&gcc GCC_PCIE_1_LINK_DOWN_BCR>,
<&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>;
reset-names = "pcie_1_core_reset",
"pcie_1_phy_reset",
"pcie_1_link_down_reset",
"pcie_1_phy_nocsr_com_phy_reset";
dma-coherent;
qcom,smmu-sid-base = <0x1480>;
iommu-map = <0x0 &apps_smmu 0x1480 0x1>,
<0x100 &apps_smmu 0x1481 0x1>;
qcom,boot-option = <0x1>;
qcom,aux-clk-freq = <17>; /* 16.6 MHz */
qcom,drv-name = "lpass";
qcom,drv-l1ss-timeout-us = <5000>;
qcom,eq-fmdc-t-min-phase23 = <1>;
qcom,slv-addr-space-size = <0x20000000>;
qcom,ep-latency = <10>;
qcom,num-parf-testbus-sel = <0xb9>;
qcom,l1-2-th-scale = <2>;
qcom,l1-2-th-value = <150>;
qcom,pcie-clkreq-offset = <0x2c48>;
qcom,pcie-phy-ver = <106>;
qcom,phy-status-offset = <0x1214>;
qcom,phy-status-bit = <7>;
qcom,phy-power-down-offset = <0x1240>;
qcom,phy-sequence = <0x1240 0x03 0x0
0x0030 0x1d 0x0
0x0034 0x03 0x0
0x0078 0x01 0x0
0x007c 0x00 0x0
0x0080 0x51 0x0
0x00ac 0x34 0x0
0x0208 0x0c 0x0
0x020c 0x0a 0x0
0x0218 0x04 0x0
0x0220 0x16 0x0
0x0234 0x00 0x0
0x029c 0x80 0x0
0x02a0 0x7c 0x0
0x02b4 0x05 0x0
0x02e8 0x0a 0x0
0x030c 0x0d 0x0
0x0320 0x0b 0x0
0x0348 0x1c 0x0
0x0388 0x20 0x0
0x0394 0x30 0x0
0x03dc 0x09 0x0
0x03f4 0x14 0x0
0x03f8 0xb3 0x0
0x03fc 0x58 0x0
0x0400 0x9a 0x0
0x0404 0x26 0x0
0x0408 0xb6 0x0
0x040c 0xee 0x0
0x0410 0xdb 0x0
0x0414 0xdb 0x0
0x0418 0xa0 0x0
0x041c 0xdf 0x0
0x0420 0x78 0x0
0x0424 0x76 0x0
0x0428 0xff 0x0
0x0830 0x1d 0x0
0x0834 0x03 0x0
0x0878 0x01 0x0
0x087c 0x00 0x0
0x0880 0x51 0x0
0x08ac 0x34 0x0
0x0a08 0x0c 0x0
0x0a0c 0x0a 0x0
0x0a18 0x04 0x0
0x0a20 0x16 0x0
0x0a34 0x00 0x0
0x0a9c 0x80 0x0
0x0aa0 0x7c 0x0
0x0ab4 0x05 0x0
0x0ae8 0x0a 0x0
0x0b0c 0x0d 0x0
0x0b20 0x0b 0x0
0x0b48 0x1c 0x0
0x0b88 0x20 0x0
0x0b94 0x30 0x0
0x0bdc 0x09 0x0
0x0bf4 0x14 0x0
0x0bf8 0xb3 0x0
0x0bfc 0x58 0x0
0x0c00 0x9a 0x0
0x0c04 0x26 0x0
0x0c08 0xb6 0x0
0x0c0c 0xee 0x0
0x0c10 0xdb 0x0
0x0c14 0xdb 0x0
0x0c18 0xa0 0x0
0x0c1c 0xdf 0x0
0x0c20 0x78 0x0
0x0c24 0x76 0x0
0x0c28 0xff 0x0
0x0ea0 0x01 0x0
0x0eb4 0x00 0x0
0x0ec4 0x00 0x0
0x0ec8 0x1f 0x0
0x0ed4 0x12 0x0
0x0ed8 0x12 0x0
0x0edc 0xdb 0x0
0x0ee0 0x9a 0x0
0x0ee4 0x38 0x0
0x0ee8 0xb6 0x0
0x0eec 0x64 0x0
0x0ef0 0x1f 0x0
0x0ef4 0x1f 0x0
0x0ef8 0x1f 0x0
0x0efc 0x1f 0x0
0x0f00 0x1f 0x0
0x0f04 0x1f 0x0
0x0f0c 0x1f 0x0
0x0f14 0x1f 0x0
0x0f1c 0x1f 0x0
0x0f28 0x5b 0x0
0x1000 0x26 0x0
0x1004 0x03 0x0
0x1010 0x06 0x0
0x1014 0x16 0x0
0x1018 0x36 0x0
0x101c 0x04 0x0
0x1020 0x0a 0x0
0x1024 0x1a 0x0
0x1028 0x68 0x0
0x1030 0xab 0x0
0x1034 0xaa 0x0
0x1038 0x02 0x0
0x103c 0x12 0x0
0x1060 0xf8 0x0
0x1064 0x01 0x0
0x1070 0x06 0x0
0x1074 0x16 0x0
0x1078 0x36 0x0
0x107c 0x0a 0x0
0x1080 0x04 0x0
0x1084 0x0d 0x0
0x1088 0x41 0x0
0x1090 0xab 0x0
0x1094 0xaa 0x0
0x1098 0x01 0x0
0x109c 0x00 0x0
0x10bc 0x0a 0x0
0x10c0 0x01 0x0
0x10cc 0x62 0x0
0x10d0 0x02 0x0
0x10d8 0x40 0x0
0x10dc 0x14 0x0
0x10e0 0x90 0x0
0x10e4 0x82 0x0
0x10f4 0x0f 0x0
0x1110 0x08 0x0
0x1120 0x46 0x0
0x1124 0x04 0x0
0x1140 0x14 0x0
0x1164 0x34 0x0
0x1170 0xa0 0x0
0x1174 0x06 0x0
0x1184 0x88 0x0
0x1188 0x14 0x0
0x1198 0x0f 0x0
0x129c 0x87 0x0
0x12a0 0x05 0x0
0x12a4 0xa1 0x0
0x1378 0x2e 0x0
0x1390 0xcc 0x0
0x13f8 0x00 0x0
0x13fc 0x22 0x0
0x141c 0xc1 0x0
0x1450 0x0f 0x0
0x1490 0x00 0x0
0x14a0 0x16 0x0
0x14f0 0x27 0x0
0x14f4 0x27 0x0
0x1508 0x02 0x0
0x155c 0x2e 0x0
0x157c 0x03 0x0
0x1584 0x28 0x0
0x13dc 0x04 0x0
0x13e0 0x02 0x0
0x1418 0xc0 0x0
0x140c 0x1d 0x0
0x158c 0x0f 0x0
0x15ac 0xf2 0x0
0x15c0 0xf2 0x0
0x1370 0x17 0x0
0x1200 0x00 0x0
0x1244 0x03 0x0>;
qcom,parf-debug-reg = <0x01b0 0x0024 0x0028 0x0224 0x0500
0x04d0 0x04d4 0x03c0 0x0630 0x0230
0x0000>;
qcom,dbi-debug-reg = <0x0104 0x0110 0x0080 0x01f4 0x0730
0x0734 0x0738 0x073c>;
qcom,phy-debug-reg = <0x11cc 0x11d0 0x11d4 0x11d8 0x11dc
0x11e0 0x11e4 0x11f8 0x00b8 0x08b8
0x00c4 0x08c4 0x0464 0x0c64 0x1800
0x1c00 0x1804 0x1c04 0x1808 0x1c08
0x180c 0x1c0c 0x1810 0x1c10 0x1814
0x1c14 0x1818 0x1c18 0x1a20 0x1e20
0x1214 0x1218 0x121c 0x1220 0x1224
0x1228 0x122c 0x1230 0x1234 0x1238
0x123c 0x1400 0x1404>;
pcie1_rp: pcie1_rp {
reg = <0 0 0 0 0>;
};
};
};

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qcom/pineapple-pmic-overlay.dtsi Normal file
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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/gpio/gpio.h>
#include "pm8010.dtsi"
#include "pm8550.dtsi"
#include "pm8550b.dtsi"
#include "pm8550ve.dtsi"
#include "pm8550vs.dtsi"
#include "pmk8550.dtsi"
#include "pmr735d.dtsi"
&pm8550_gpios {
key_vol_up {
key_vol_up_default: key_vol_up_default {
pins = "gpio6";
function = "normal";
input-enable;
bias-pull-up;
power-source = <1>;
};
};
sd_card_det {
sd_card_det_default: sd_card_det_default {
pins = "gpio12";
function = "normal";
input-enable;
output-disable;
bias-pull-up;
power-source = <1>; /* 1.8 V */
};
};
};
&pm8550_tz {
io-channels = <&pmk8550_vadc PM8550_ADC5_GEN3_DIE_TEMP>;
io-channel-names = "thermal";
};
&pm8550b_tz {
io-channels = <&pmk8550_vadc PM8550B_ADC5_GEN3_DIE_TEMP>;
io-channel-names = "thermal";
};
&pm8550b_lite_tz {
io-channels = <&pmk8550_vadc PM8550B_ADC5_GEN3_TEMP_ALARM_LITE>;
io-channel-names = "thermal";
};
&pm8550vs_c_tz {
io-channels = <&pmk8550_vadc PM8550VS_C_ADC5_GEN3_DIE_TEMP>;
io-channel-names = "thermal";
};
&pm8550vs_d_tz {
io-channels = <&pmk8550_vadc PM8550VS_D_ADC5_GEN3_DIE_TEMP>;
io-channel-names = "thermal";
};
&pm8550vs_e_tz {
io-channels = <&pmk8550_vadc PM8550VS_E_ADC5_GEN3_DIE_TEMP>;
io-channel-names = "thermal";
};
&pm8550vs_g_tz {
io-channels = <&pmk8550_vadc PM8550VS_G_ADC5_GEN3_DIE_TEMP>;
io-channel-names = "thermal";
};
&pm8550ve_tz {
io-channels = <&pmk8550_vadc PM8550VE_ADC5_GEN3_DIE_TEMP>;
io-channel-names = "thermal";
};
&pmk8550_vadc {
pmk8550_xo_therm {
reg = <PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_100K_PU>;
label = "pmk8550_xo_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
qcom,adc-tm-type = <1>;
};
pm8550_msm_therm {
reg = <PM8550_ADC5_GEN3_AMUX_THM1_100K_PU>;
label = "pm8550_msm_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
qcom,adc-tm-type = <1>;
};
pm8550_cam_flash_therm {
reg = <PM8550_ADC5_GEN3_AMUX_THM2_100K_PU>;
label = "pm8550_cam_flash_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
qcom,adc-tm-type = <1>;
};
pm8550_wlan_therm {
reg = <PM8550_ADC5_GEN3_AMUX_THM3_100K_PU>;
label = "pm8550_wlan_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
qcom,adc-tm-type = <1>;
};
pm8550_pa_therm1 {
reg = <PM8550_ADC5_GEN3_AMUX_THM4_100K_PU>;
label = "pm8550_pa_therm_1";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
qcom,adc-tm-type = <1>;
};
pm8550_rear_tof_therm {
reg = <PM8550_ADC5_GEN3_AMUX_THM5_100K_PU>;
label = "pm8550_rear_tof_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
qcom,adc-tm-type = <1>;
};
pm8550b_usb_therm {
reg = <PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_100K_PU>;
label = "pm8550b_usb_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
qcom,adc-tm-type = <1>;
};
pm8550b_wls_therm {
reg = <PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_100K_PU>;
label = "pm8550b_wls_therm";
qcom,ratiometric;
qcom,pre-scaling = <1 1>;
qcom,adc-tm-type = <1>;
};
pm8550b_chg_temp {
reg = <PM8550B_ADC5_GEN3_CHG_TEMP>;
label = "pm8550b_chg_temp";
};
pm8550b_iin_fb {
reg = <PM8550B_ADC5_GEN3_IIN_FB>;
label = "pm8550b_iin_fb";
};
pm8550b_ichg_fb {
reg = <PM8550B_ADC5_GEN3_ICHG_FB>;
label = "pm8550b_ichg_fb";
};
};
&pmk8550_gpios {
pinctrl-0 = <&alt_sleep_clk_default>;
pinctrl-names = "default";
alt_sleep_clk {
alt_sleep_clk_default: alt_sleep_clk_default {
pins = "gpio3";
function = "func1";
input-disable;
output-enable;
bias-disable;
power-source = <0>;
};
};
};
&thermal_zones {
skin-msm-therm {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8550_vadc PM8550_ADC5_GEN3_AMUX_THM1_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
cam-flash-therm {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8550_vadc PM8550_ADC5_GEN3_AMUX_THM2_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
wlan-therm {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8550_vadc PM8550_ADC5_GEN3_AMUX_THM3_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
pa-therm-1 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8550_vadc PM8550_ADC5_GEN3_AMUX_THM4_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
rear-tof-therm {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8550_vadc PM8550_ADC5_GEN3_AMUX_THM5_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
usb-therm {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8550_vadc PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
wls-therm {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8550_vadc PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
xo-therm {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8550_vadc PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
xo_config0: xo-config0 {
temperature = <78000>;
hysteresis = <8000>;
type = "passive";
};
xo_config1: xo-config1 {
temperature = <80000>;
hysteresis = <10000>;
type = "passive";
};
display_test_config1: display-test-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
display_test_config2: display-test-config2 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
display_test_config3: display-test-config3 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
display_test_config4: display-test-config4 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
};
&pm8550b_eusb2_repeater {
vdd18-supply = <&pm_humu_l15>;
vdd3-supply = <&pm_humu_l5>;
};
&soc {
reboot_reason {
compatible = "qcom,reboot-reason";
nvmem-cells = <&restart_reason>;
nvmem-cell-names = "restart_reason";
};
DBO3: regulator-dbo3 {
compatible = "qti-regulator-fixed";
regulator-name = "dbo3";
regulator-min-microvolt = <3600000>;
regulator-max-microvolt = <3600000>;
gpio = <&pm8550_gpios 9 GPIO_ACTIVE_HIGH>;
regulator-enable-ramp-delay = <1500>;
enable-active-high;
};
pmic-pon-log {
compatible = "qcom,pmic-pon-log";
nvmem = <&pmk8550_sdam_5>, <&pmk8550_sdam_6>;
nvmem-names = "pon_log0", "pon_log1";
};
regulator_ocp_notifier: regulator-ocp-notifier {
compatible = "qcom,regulator-ocp-notifier";
interrupt-parent = <&spmi_bus>;
interrupts = <0x0 0x71 0x1 IRQ_TYPE_EDGE_RISING>,
<0x0 0x85 0x1 IRQ_TYPE_EDGE_RISING>;
nvmem-cells = <&ocp_log>, <&alarm_log>;
nvmem-cell-names = "ocp_log", "alarm_log";
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "pineapple-qrd.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Pineapple QRD";
compatible = "qcom,pineapple-qrd", "qcom,pineapple", "qcom,pineapplep-qrd", "qcom,pineapplep", "qcom,qrd";
qcom,msm-id = <557 0x10000>, <557 0x20000>, <577 0x10000>, <577 0x20000>;
qcom,board-id = <0x1000B 0>, <0xB 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "pineapple-qrd.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Pineapple QRD";
compatible = "qcom,pineapple-qrd", "qcom,pineapple", "qcom,pineapplep-qrd", "qcom,pineapplep", "qcom,qrd";
qcom,msm-id = <557 0x10000>, <557 0x20000>, <577 0x10000>, <577 0x20000>;
qcom,board-id = <0x5000B 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/clock/qcom,gcc-pineapple.h>
#include "pineapple-pmic-overlay.dtsi"
#include "pineapple-thermal-overlay.dtsi"
&sdhc_2 {
status = "ok";
vdd-supply = <&pm_humu_l9>;
qcom,vdd-voltage-level = <2950000 2960000>;
qcom,vdd-current-level = <0 800000>;
vdd-io-supply = <&pm_humu_l8>;
qcom,vdd-io-voltage-level = <1800000 2960000>;
qcom,vdd-io-current-level = <0 10000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>, <&sd_card_det_default>;
pinctrl-1 = <&sdc2_off>, <&sd_card_det_default>;
cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_LOW>;
resets = <&gcc GCC_SDCC2_BCR>;
reset-names = "core_reset";
qcom,iommu-dma = "fastmap";
};
&soc {
gpio_keys {
compatible = "gpio-keys";
label = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&key_vol_up_default>;
vol_up {
label = "volume_up";
gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
linux,code = <KEY_VOLUMEUP>;
gpio-key,wakeup;
debounce-interval = <15>;
linux,can-disable;
};
};
};
&ufsphy_mem {
compatible = "qcom,ufs-phy-qmp-v4-pineapple";
/* VDDA_UFS_CORE */
vdda-phy-supply = <&pm_v6d_l1>;
vdda-phy-max-microamp = <211000>;
/* VDDA_UFS_0_1P2 */
vdda-pll-supply = <&pm_v8_l3>;
vdda-pll-max-microamp = <18300>;
/* Phy GDSC for VDD_MX, always on */
vdd-phy-gdsc-supply = <&gcc_ufs_mem_phy_gdsc>;
/* Qref power supply, Refer Qref diagram */
vdda-qref-supply = <&pm_v8_l1>;
vdda-qref-max-microamp = <64500>;
status = "ok";
};
&ufshc_mem {
vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
vcc-supply = <&pm_humu_l17>;
vcc-max-microamp = <1300000>;
vccq-supply = <&pm_v6c_l1>;
vccq-max-microamp = <1200000>;
/* VDD_PX10 is voted for the ufs_reset_n */
qcom,vddp-ref-clk-supply = <&pm_v6c_l3>;
qcom,vddp-ref-clk-max-microamp = <100>;
qcom,vccq-parent-supply = <&pm_v6c_s1>;
qcom,vccq-parent-max-microamp = <210000>;
reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
resets = <&gcc GCC_UFS_PHY_BCR>;
reset-names = "rst";
status = "ok";
};
&pm8550_switch0 {
qcom,led-mask = <9>; /* Channels 1 & 4 */
qcom,symmetry-en;
};
&pm8550_switch1 {
qcom,led-mask = <6>; /* Channels 2 & 3 */
qcom,symmetry-en;
};
&pm8550_switch2 {
qcom,led-mask = <15>; /* All Channels */
qcom,symmetry-en;
};
&pm8550_flash {
status = "ok";
};
&pmic_glink_debug {
i2c@107 {
reg = <0x107>; /* I2C instance 7 in ADSP for SE6 */
#address-cells = <1>;
#size-cells = <0>;
qcom,bus-type = "i2c";
qcom,smb1396@34 {
compatible = "qcom,i2c-pmic";
reg = <0x34>;
qcom,can-sleep;
};
qcom,smb1396@35 {
compatible = "qcom,i2c-pmic";
reg = <0x35>;
qcom,can-sleep;
};
qcom,idt9418@3b {
compatible = "qcom,i2c-pmic";
reg = <0x3b>;
qcom,can-sleep;
};
};
/* SPMI bridge bus 0 with SMB1510 device */
spmi@200 {
reg = <0x200>;
#address-cells = <2>;
#size-cells = <0>;
qcom,bus-type = "spmi";
qcom,smb1510@d {
compatible = "qcom,spmi-pmic";
reg = <0xd SPMI_USID>;
qcom,can-sleep;
};
};
};
&pmic_glink_adc {
status = "ok";
smb1396_1_iin {
reg = <0x1073401>;
label = "smb1396_1_iin";
};
smb1396_1_ichg {
reg = <0x1073402>;
label = "smb1396_1_ichg";
};
smb1396_1_die_temp {
reg = <0x1073403>;
label = "smb1396_1_die_temp";
};
smb1396_2_iin {
reg = <0x1073501>;
label = "smb1396_2_iin";
};
smb1396_2_ichg {
reg = <0x1073502>;
label = "smb1396_2_ichg";
};
smb1396_2_die_temp {
reg = <0x1073503>;
label = "smb1396_2_die_temp";
};
};
&qupv3_se4_spi {
#address-cells = <1>;
#size-cells = <0>;
status = "ok";
qcom,touch-active = "goodix,gt9916S";
qcom,la-vm;
goodix-berlin@0 {
compatible = "goodix,gt9916S";
reg = <0>;
spi-max-frequency = <1000000>;
goodix,avdd-name = "avdd";
avdd-supply = <&L14B>;
interrupt-parent = <&tlmm>;
interrupts = <162 0x2008>;
goodix,reset-gpio = <&tlmm 161 0x00>;
goodix,irq-gpio = <&tlmm 162 0x2008>;
goodix,irq-flags = <2>;
goodix,panel-max-x = <1080>;
goodix,panel-max-y = <2400>;
goodix,panel-max-w = <255>;
goodix,panel-max-p = <4096>;
goodix,firmware-name = "goodix_firmware_spi.bin";
goodix,config-name = "goodix_cfg_group_spi.bin";
pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", "pmx_ts_release";
pinctrl-0 = <&ts_active>;
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
pinctrl-2 = <&ts_release>;
goodix,touch-type = "primary";
goodix,qts_en;
qts,trusted-touch-mode = "vm_mode";
qts,touch-environment = "pvm";
qts,trusted-touch-type = "primary";
qts,trusted-touch-spi-irq = <598>;
qts,trusted-touch-io-bases = <0xa90000>;
qts,trusted-touch-io-sizes = <0x1000>;
qts,trusted-touch-vm-gpio-list = <&tlmm 48 0 &tlmm 49 0 &tlmm 50 0
&tlmm 51 0 &tlmm 161 0 &tlmm 162 0x2008>;
};
};
&pm8550b_haptics {
qcom,vmax-mv = <1700>;
qcom,lra-period-us = <5880>;
effect_0 {
/* CLICK */
qcom,wf-vmax-mv = <1800>;
qcom,wf-pattern-period-us = <5880>;
};
effect_1 {
/* DOUBLE_CLICK */
qcom,wf-vmax-mv = <1800>;
qcom,wf-pattern-period-us = <5880>;
};
effect_2 {
/* TICK */
qcom,wf-vmax-mv = <1800>;
qcom,wf-pattern-period-us = <5880>;
};
effect_3 {
/* THUD */
qcom,wf-vmax-mv = <1800>;
qcom,wf-pattern-period-us = <5880>;
};
effect_4 {
/* POP */
qcom,wf-vmax-mv = <1800>;
qcom,wf-pattern-period-us = <5880>;
};
effect_5 {
/* HEAVY CLICK */
qcom,wf-vmax-mv = <1800>;
qcom,wf-pattern-period-us = <5880>;
};
primitive_0 {
/* NOOP */
qcom,wf-vmax-mv = <1800>;
qcom,wf-pattern-period-us = <5880>;
};
primitive_1 {
/* CLICK */
qcom,wf-vmax-mv = <1800>;
qcom,wf-pattern-period-us = <5880>;
};
primitive_2 {
/* THUD */
qcom,wf-vmax-mv = <1800>;
qcom,wf-pattern-period-us = <5880>;
};
primitive_3 {
/* SPIN */
qcom,wf-vmax-mv = <1800>;
qcom,wf-pattern-period-us = <5880>;
};
primitive_4 {
/* QUICK_RISE */
qcom,wf-vmax-mv = <1800>;
qcom,wf-pattern-period-us = <5880>;
};
primitive_5 {
/* SLOW_RISE */
qcom,wf-vmax-mv = <1800>;
qcom,wf-pattern-period-us = <5880>;
};
primitive_6 {
/* QUICK_FALL */
qcom,wf-vmax-mv = <1800>;
qcom,wf-pattern-period-us = <5880>;
};
primitive_7 {
/* LIGHT_TICK */
qcom,wf-vmax-mv = <1800>;
qcom,wf-pattern-period-us = <5880>;
};
primitive_8 {
/* LOW_TICK */
qcom,wf-vmax-mv = <1800>;
qcom,wf-pattern-period-us = <5880>;
};
};
&battery_charger {
qcom,wireless-fw-name = "idt9418.bin";
qcom,thermal-mitigation-step = <500000>;
#cooling-cells = <2>;
};
&eusb2_phy0 {
dummy-supply = <&pm8550b_eusb2_repeater>;
usb-repeater = <&pm8550b_eusb2_repeater>;
};
&pm8550b_eusb2_repeater {
qcom,param-override-seq =
/* <value reg_offset> */
/* Adjust HS trasmit amplitude */
<0xd 0x51
/* Squelch detection threshold */
0x3 0x54
/* Tx pre-emphasis tuning */
0x7 0x57
/* HS disconnect threshold */
0x6 0x53
/* slew rate */
0x00 0x59>;
};
&usb0 {
qcom,wcd_usbss = <&wcd_usbss>;
usb-role-switch;
port {
usb_port0: endpoint {
remote-endpoint = <&usb_port0_connector>;
};
};
};
&ucsi {
connector {
port {
usb_port0_connector: endpoint {
remote-endpoint = <&usb_port0>;
};
};
};
};
&qupv3_se6_i2c {
status = "ok";
#address-cells = <1>;
#size-cells = <0>;
redriver: redriver@1c {
compatible = "onnn,redriver";
reg = <0x1c>;
vdd-supply = <&L15B>;
lane-channel-swap;
eq = /bits/ 8 <
/* Parameters for USB */
0x4 0x4 0x4 0x4
/* Parameters for DP */
0x4 0x6 0x6 0x4>;
flat-gain = /bits/ 8 <
/* Parameters for USB */
0x3 0x1 0x1 0x3
/* Parameters for DP */
0x0 0x3 0x3 0x0>;
output-comp = /bits/ 8 <
/* Parameters for USB */
0x3 0x3 0x3 0x3
/* Parameters for DP */
0x3 0x3 0x3 0x3>;
loss-match = /bits/ 8 <
/* Parameters for USB */
0x1 0x3 0x3 0x1
/* Parameters for DP */
0x3 0x3 0x3 0x3>;
};
};
&usb_qmp_dp_phy {
pinctrl-names = "unused";
};
&usb0 {
pinctrl-names = "default";
pinctrl-0 = <&usb3phy_portselect_gpio>;
gpios = <&tlmm 29 0>;
ssusb_redriver = <&redriver>;
};
&regulator_ocp_notifier {
periph-1c1-supply = <&L1B>;
periph-1c2-supply = <&L2B>;
periph-1c5-supply = <&L5B>;
periph-1c6-supply = <&L6B>;
periph-1c7-supply = <&L7B>;
periph-1c8-supply = <&L8B>;
periph-1c9-supply = <&L9B>;
periph-1ca-supply = <&L10B>;
periph-1cb-supply = <&L11B>;
periph-1cc-supply = <&L12B>;
periph-1cd-supply = <&L13B>;
periph-1ce-supply = <&L14B>;
periph-1cf-supply = <&L15B>;
periph-1d0-supply = <&L16B>;
periph-1d1-supply = <&L17B>;
periph-1e4-supply = <&BOB1>;
periph-1e6-supply = <&BOB2>;
periph-29b-supply = <&S1C>;
periph-29e-supply = <&S2C>;
periph-2a1-supply = <&S3C>;
periph-2a4-supply = <&S4C>;
periph-2a7-supply = <&S5C>;
periph-2aa-supply = <&S6C>;
periph-2c1-supply = <&L1C>;
periph-2c2-supply = <&L2C>;
periph-2c3-supply = <&L3C>;
periph-3a1-supply = <&S3D_LEVEL>;
periph-3a4-supply = <&S4D_LEVEL>;
periph-3a7-supply = <&S5D_LEVEL>;
periph-3c1-supply = <&L1D>;
periph-3c2-supply = <&L2D_LEVEL>;
periph-3c3-supply = <&L3D>;
periph-4c2-supply = <&L2E>;
periph-4c3-supply = <&L3E>;
periph-69b-supply = <&S1G_LEVEL>;
periph-6a1-supply = <&S3G>;
periph-6a4-supply = <&S4G_LEVEL>;
periph-6a7-supply = <&S5G_LEVEL>;
periph-6c1-supply = <&L1G>;
periph-6c2-supply = <&L2G>;
periph-6c3-supply = <&L3G>;
periph-89b-supply = <&S1I_LEVEL>;
periph-8a1-supply = <&S3I_LEVEL>;
periph-8a4-supply = <&S4I>;
periph-8a7-supply = <&S5I>;
periph-8aa-supply = <&S6I_LEVEL>;
periph-8b0-supply = <&S8I_LEVEL>;
periph-8c1-supply = <&L1I>;
periph-8c2-supply = <&L2I>;
periph-8c3-supply = <&L3I>;
periph-ac1-supply = <&L1K>;
periph-ac2-supply = <&L2K>;
periph-ac3-supply = <&L3K>;
periph-ac4-supply = <&L4K>;
periph-ac5-supply = <&L5K>;
periph-ac6-supply = <&L6K>;
periph-ac7-supply = <&L7K>;
periph-c40-supply = <&L1M>;
periph-c41-supply = <&L2M>;
periph-c42-supply = <&L3M>;
periph-c43-supply = <&L4M>;
periph-c44-supply = <&L5M>;
periph-c45-supply = <&L6M>;
periph-c46-supply = <&L7M>;
periph-d40-supply = <&L1N>;
periph-d41-supply = <&L2N>;
periph-d42-supply = <&L3N>;
periph-d43-supply = <&L4N>;
periph-d44-supply = <&L5N>;
periph-d45-supply = <&L6N>;
periph-d46-supply = <&L7N>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "pineapple-rcm.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Pineapple RCM";
compatible = "qcom,pineapple-rcm", "qcom,pineapple", "qcom,pineapplep-rcm", "qcom,pineapplep", "qcom,rcm";
qcom,msm-id = <557 0x10000>, <557 0x20000>, <577 0x10000>, <577 0x20000>;
qcom,board-id = <0x15 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "pineapple-cdp.dtsi"
&qupv3_se4_spi {
status = "disabled";
};
&qupv3_se4_i2c {
#address-cells = <1>;
#size-cells = <0>;
status = "ok";
qcom,i2c-touch-active = "atmel,maxtouch";
qcom,la-vm;
atmel_mxt_ts@4a {
compatible = "atmel,maxtouch";
reg = <0x4a>;
interrupt-parent = <&tlmm>;
interrupts = <162 0x2008>;
avdd-supply = <&L14B>;
vdd-supply = <&L12B>;
pinctrl-names = "pmx_ts_active", "pmx_ts_suspend";
pinctrl-0 = <&ts_active>;
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
atmel,xy_switch;
atmel,inverty;
atmel,invertx;
reset-gpios = <&tlmm 161 0x00>;
irq-gpios = <&tlmm 162 0x2008>;
atmel,panel-coords = <0 0 479 799>;
atmel,display-coords = <0 0 339 729>;
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "pineapple-rumi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Pineapple RUMI";
compatible = "qcom,pineapple-rumi", "qcom,pineapple", "qcom,rumi";
qcom,msm-id = <557 0x10000>, <557 0x20000>;
qcom,board-id = <15 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/qcom,gcc-pineapple.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include "pineapple-pmic-overlay.dtsi"
&chosen {
};
&reserved_memory {
spintable: spintable_region@e3940000 {
no-map;
reg = <0x0 0xe3940000 0x0 0x100000>;
};
};
&arch_timer {
clock-frequency = <192000>;
};
&memtimer {
clock-frequency = <192000>;
};
&qupv3_se15_2uart {
qcom,rumi_platform;
};
&sdhc_2 {
status = "ok";
vdd-supply = <&pm_humu_l9>;
qcom,vdd-voltage-level = <2950000 2960000>;
qcom,vdd-current-level = <0 800000>;
vdd-io-supply = <&pm_humu_l8>;
qcom,vdd-io-voltage-level = <1800000 2960000>;
qcom,vdd-io-current-level = <0 10000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>;
pinctrl-1 = <&sdc2_off>;
resets = <&gcc GCC_SDCC2_BCR>;
reset-names = "core_reset";
qcom,iommu-dma = "fastmap";
};
&ufsphy_mem {
compatible = "qcom,ufs-phy-qrbtc-sdm845";
vdda-phy-max-microamp = <150000>;
vdda-pll-max-microamp = <19200>;
status = "ok";
};
&ufshc_mem {
limit-tx-hs-gear = <1>;
limit-rx-hs-gear = <1>;
limit-rate = <2>; /* HS Rate-B */
vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
vcc-supply = <&pm_humu_l17>;
vcc-max-microamp = <1300000>;
vccq-supply = <&pm_v6c_l1>;
vccq-max-microamp = <1200000>;
qcom,vddp-ref-clk-supply = <&pm_v6c_l3>;
qcom,vddp-ref-clk-max-microamp = <100>;
qcom,vccq-parent-supply = <&pm_v6c_s1>;
qcom,vccq-parent-max-microamp = <210000>;
qcom,disable-lpm;
rpm-level = <0>;
spm-level = <0>;
qcom,iommu-dma = "bypass";
clock-names =
"core_clk",
"bus_aggr_clk",
"iface_clk",
"core_clk_unipro",
"core_clk_ice",
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
"rx_lane1_sync_clk";
clocks =
<&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_UFS_PHY_AHB_CLK>,
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
freq-table-hz =
<100000000 403000000>,
<0 0>,
<0 0>,
<100000000 403000000>,
<100000000 403000000>,
<0 0>,
<0 0>,
<0 0>,
<0 0>;
status = "ok";
};
&SILVER_OFF_CL0 {
status = "nok";
};
&GOLD_OFF_CL1 {
status = "nok";
};
&GOLD_OFF_CL2 {
status = "nok";
};
&GOLD_OFF_CL3 {
status = "nok";
};
&CLUSTER_PWR_DN {
status = "nok";
};
&APSS_OFF {
status = "nok";
};
&tsens0 {
status = "disabled";
};
&tsens1 {
status = "disabled";
};
&tsens2 {
status = "disabled";
};
&soc {
usb_nop_phy: usb_nop_phy {
compatible = "usb-nop-xceiv";
};
usb_emuphy: phy@a784000 {
compatible = "qcom,usb-emu-phy";
reg = <0x0a784000 0x9500>;
qcom,emu-init-seq = <0xfffff 0x4
0xffff0 0x4
0x100000 0x20
0x0 0x20
0x000101F0 0x20
0x00100000 0x3c
0x0 0x3c
0x0 0x4>;
};
pcie0: qcom,pcie@1c00000 {
reg = <0x01c00000 0x3000>,
<0x01c06000 0x2000>,
<0x60000000 0xf1d>,
<0x60000f20 0xa8>,
<0x60001000 0x1000>,
<0x60100000 0x100000>,
<0x01c05000 0x1000>,
<0x01D07000 0x7000>;
reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf",
"rumi", "pcie_sm";
linux,pci-domain = <0>;
qcom,target-link-speed = <0x1>;
qcom,link-check-max-count = <200>; /* 1 sec */
qcom,no-l0s-supported;
qcom,no-l1-supported;
qcom,no-l1ss-supported;
qcom,no-aux-clk-sync;
/*
* Comment out ICC and SMMU properties in main PCIe node
* if any issue in PCIe probe in RUMI
*/
status = "ok";
};
};
&usb0 {
dwc3@a600000 {
usb-phy = <&usb_emuphy>, <&usb_nop_phy>;
dr_mode = "peripheral";
maximum-speed = "high-speed";
};
};
&bwmon_ddr {
qcom,hw-timer-hz = <192000>;
};
&bwmon_llcc {
qcom,hw-timer-hz = <192000>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/thermal/thermal_qti.h>
&soc {
qmi-tmd-devices {
compatible = "qcom,qmi-cooling-devices";
modem {
qcom,instance-id = <QMI_MODEM_INST_ID>;
modem_lte_dsc: modem_lte_dsc {
qcom,qmi-dev-name = "modem_lte_dsc";
#cooling-cells = <2>;
};
modem_nr_dsc: modem_nr_dsc {
qcom,qmi-dev-name = "modem_nr_dsc";
#cooling-cells = <2>;
};
modem_nr_scg_dsc: modem_nr_scg_dsc {
qcom,qmi-dev-name = "modem_nr_scg_dsc";
#cooling-cells = <2>;
};
sdr0_lte_dsc: sdr0_lte_dsc {
qcom,qmi-dev-name = "sdr0_lte_dsc";
#cooling-cells = <2>;
};
sdr0_nr_dsc: sdr0_nr_dsc {
qcom,qmi-dev-name = "sdr0_nr_dsc";
#cooling-cells = <2>;
};
pa_lte_sdr0_dsc: pa_lte_sdr0_dsc {
qcom,qmi-dev-name = "pa_lte_sdr0_dsc";
#cooling-cells = <2>;
};
pa_nr_sdr0_dsc: pa_nr_sdr0_dsc {
qcom,qmi-dev-name = "pa_nr_sdr0_dsc";
#cooling-cells = <2>;
};
pa_nr_sdr0_scg_dsc: pa_nr_sdr0_scg_dsc {
qcom,qmi-dev-name = "pa_nr_sdr0_scg_dsc";
#cooling-cells = <2>;
};
mmw0_dsc: mmw0_dsc {
qcom,qmi-dev-name = "mmw0_dsc";
#cooling-cells = <2>;
};
mmw1_dsc: mmw1_dsc {
qcom,qmi-dev-name = "mmw1_dsc";
#cooling-cells = <2>;
};
mmw2_dsc: mmw2_dsc {
qcom,qmi-dev-name = "mmw2_dsc";
#cooling-cells = <2>;
};
mmw3_dsc: mmw3_dsc {
qcom,qmi-dev-name = "mmw3_dsc";
#cooling-cells = <2>;
};
qmi_wlan: wlan {
qcom,qmi-dev-name = "wlan";
#cooling-cells = <2>;
};
modem_bw_backoff: modem_bw_backoff {
qcom,qmi-dev-name = "modem_bw_backoff";
#cooling-cells = <2>;
};
modem_vdd: modem_vdd {
qcom,qmi-dev-name = "cpuv_restriction_cold";
#cooling-cells = <2>;
};
};
};
qmi_sensor: qmi-ts-sensors {
compatible = "qcom,qmi-sensors";
#thermal-sensor-cells = <1>;
modem {
qcom,instance-id = <QMI_MODEM_INST_ID>;
qcom,qmi-sensor-names = "modem_tsens",
"modem_tsens1",
"pa",
"pa_1",
"modem_bcl_warn",
"sdr0_pa",
"sdr0",
"mmw0",
"mmw1",
"mmw2",
"mmw3",
"mmw_pa1",
"mmw_pa2",
"mmw_pa3",
"mmw_ific0",
"epm0",
"epm1",
"epm2",
"epm3",
"epm4",
"epm5",
"epm6",
"epm7",
"sys_therm1",
"sys_therm2",
"sys_therm3",
"sys_therm4",
"sys_therm5",
"sys_therm6",
"sub0_sdr0_pa",
"sdr_mmw_therm",
"sub1_modem_cfg",
"sub1_lte_cc",
"sub1_mcg_fr1_cc",
"sub1_mcg_fr2_cc",
"sub1_scg_fr1_cc",
"sub1_scg_fr2_cc";
};
};
};
&thermal_zones {
pa {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_PA)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
pa1 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_PA_1)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
bcl_warn {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_BCL_WARN)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sdr0_pa {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_SDR0_PA)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sdr0 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_SDR0)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
mmw0 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_MMW0)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
mmw1 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_MMW1)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
mmw2 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_MMW2)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
mmw3 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_MMW3)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
mmw_pa1 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_MMW_PA1)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
mmw_pa2 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_MMW_PA2)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
mmw_pa3 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_MMW_PA3)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
mmw_ific0 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_MMW_IFIC0)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
epm0 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_EPM0)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
epm1 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_EPM1)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
epm2 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_EPM2)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
epm3 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_EPM3)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
epm4 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_EPM4)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
epm5 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_EPM5)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
epm6 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_EPM6)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
epm7 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_EPM7)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sdr_mmw_therm {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_SDR_MMW)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sub1_modem_cfg {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_SUB1_MODEM_CFG)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sub1_lte_cc {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_SUB1_LTE_CC)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sub1_mcg_fr1_cc {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_SUB1_MCG_FR1_CC)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sub1_mcg_fr2_cc {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_SUB1_MCG_FR2_CC)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sub1_scg_fr1_cc {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_SUB1_SCG_FR1_CC)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sub1_scg_fr2_cc {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_SUB1_SCG_FR2_CC)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
pa-therm2-sys3 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_SYS_THERM_3)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/thermal/thermal_qti.h>
&thermal_zones {
socd {
cooling-maps {
socd_apc1 {
trip = <&socd_trip>;
cooling-device = <&APC1_pause 1 1>;
};
socd_apc2 {
trip = <&socd_trip>;
cooling-device = <&APC2_pause 1 1>;
};
socd_cdsp1 {
trip = <&socd_trip>;
cooling-device = <&cdsp_sw 4 4>;
};
socd_gpu0 {
trip = <&socd_trip>;
cooling-device = <&msm_gpu 4 4>;
};
};
};
pm8550b-bcl-lvl0 {
cooling-maps {
lbat_0_mdm_lte {
trip = <&b_bcl_lvl0>;
cooling-device = <&modem_lte_dsc 8 8>;
};
lbat_0_nr_scg {
trip = <&b_bcl_lvl0>;
cooling-device = <&modem_nr_scg_dsc 3 3>;
};
lbat_0_nr {
trip = <&b_bcl_lvl0>;
cooling-device = <&modem_nr_dsc 8 8>;
};
lbat_cpu_5_6_7 {
trip = <&b_bcl_lvl0>;
cooling-device = <&cpu_5_6_7_pause 1 1>;
};
lbat_cdsp0 {
trip = <&b_bcl_lvl0>;
cooling-device = <&cdsp_sw 2 2>;
};
lbat_gpu0 {
trip = <&b_bcl_lvl0>;
cooling-device = <&msm_gpu 2 2>;
};
};
};
pm8550b-bcl-lvl1 {
cooling-maps {
lbat_1_mdm_lte {
trip = <&b_bcl_lvl1>;
cooling-device = <&modem_lte_dsc 10 10>;
};
lbat_1_nr_scg {
trip = <&b_bcl_lvl1>;
cooling-device = <&modem_nr_scg_dsc 12 12>;
};
lbat_1_nr {
trip = <&b_bcl_lvl1>;
cooling-device = <&modem_nr_dsc 11 11>;
};
lbat_cpu_2_3_4 {
trip = <&b_bcl_lvl1>;
cooling-device = <&cpu_2_3_4_pause 1 1>;
};
lbat_cdsp1 {
trip = <&b_bcl_lvl1>;
cooling-device = <&cdsp_sw 4 4>;
};
lbat_gpu1 {
trip = <&b_bcl_lvl1>;
cooling-device = <&msm_gpu 4 4>;
};
};
};
pm8550b-bcl-lvl2 {
cooling-maps {
lbat_cdsp2 {
trip = <&b_bcl_lvl2>;
cooling-device = <&cdsp_sw 5 THERMAL_NO_LIMIT>;
};
lbat_gpu2 {
trip = <&b_bcl_lvl2>;
cooling-device = <&msm_gpu 5 THERMAL_NO_LIMIT>;
};
};
};
pm8550-bcl-lvl0 {
cooling-maps {
vph_lte0 {
trip = <&bcl_lvl0>;
cooling-device = <&modem_lte_dsc 8 8>;
};
vph_nr0_scg {
trip = <&bcl_lvl0>;
cooling-device = <&modem_nr_scg_dsc 3 3>;
};
vph_nr0 {
trip = <&bcl_lvl0>;
cooling-device = <&modem_nr_dsc 8 8>;
};
vph_cpu_5_6_7 {
trip = <&bcl_lvl0>;
cooling-device = <&cpu_5_6_7_pause 1 1>;
};
vph_cdsp0 {
trip = <&bcl_lvl0>;
cooling-device = <&cdsp_sw 2 2>;
};
vph_gpu0 {
trip = <&bcl_lvl0>;
cooling-device = <&msm_gpu 2 2>;
};
};
};
pm8550-bcl-lvl1 {
cooling-maps {
vph_lte1 {
trip = <&bcl_lvl1>;
cooling-device = <&modem_lte_dsc 10 10>;
};
vph_nr1_scg {
trip = <&bcl_lvl1>;
cooling-device = <&modem_nr_scg_dsc 12 12>;
};
vph_nr1 {
trip = <&bcl_lvl1>;
cooling-device = <&modem_nr_dsc 11 11>;
};
vph_cpu_2_3_4 {
trip = <&bcl_lvl1>;
cooling-device = <&cpu_2_3_4_pause 1 1>;
};
vph_cdsp1 {
trip = <&bcl_lvl1>;
cooling-device = <&cdsp_sw 4 4>;
};
vph_gpu1 {
trip = <&bcl_lvl1>;
cooling-device = <&msm_gpu 4 4>;
};
};
};
pm8550-bcl-lvl2 {
cooling-maps {
vph_cdsp2 {
trip = <&bcl_lvl2>;
cooling-device = <&cdsp_sw 5 THERMAL_NO_LIMIT>;
};
vph_gpu2 {
trip = <&bcl_lvl2>;
cooling-device = <&msm_gpu 5 THERMAL_NO_LIMIT>;
};
};
};
pm8550vs_e_tz {
cooling-maps {
pm8550vs_e_apc1 {
trip = <&pm8550vs_e_trip0>;
cooling-device = <&APC1_pause 1 1>;
};
pm8550vs_e_apc2 {
trip = <&pm8550vs_e_trip0>;
cooling-device = <&APC2_pause 1 1>;
};
};
};
pm8550vs_d_tz {
cooling-maps {
pm8550vs_d_gpu {
trip = <&pm8550vs_d_trip0>;
cooling-device = <&msm_gpu 5 THERMAL_NO_LIMIT>;
};
};
};
pm8550vs_g_tz {
cooling-maps {
pm8550vs_g_nsp {
trip = <&pm8550vs_g_trip0>;
cooling-device = <&cdsp_sw_hmx 5 THERMAL_NO_LIMIT>;
};
};
};
pm8550ve_tz {
cooling-maps {
pm8550ve_nsp {
trip = <&pm8550ve_trip0>;
cooling-device = <&cdsp_sw_hvx 5 THERMAL_NO_LIMIT>;
};
};
};
xo-therm {
cooling-maps {
apc1_cdev {
trip = <&xo_config0>;
cooling-device = <&APC1_pause 1 1>;
};
cdsp_cdev {
trip = <&xo_config0>;
cooling-device = <&cdsp_sw 5 THERMAL_NO_LIMIT>;
};
gpu_cdev {
trip = <&xo_config0>;
cooling-device = <&msm_gpu 5 THERMAL_NO_LIMIT>;
};
cpu3_hot_cdev {
trip = <&xo_config1>;
cooling-device = <&cpu3_hotplug 1 1>;
};
cpu4_hot_cdev {
trip = <&xo_config1>;
cooling-device = <&cpu4_hotplug 1 1>;
};
cpu5_hot_cdev {
trip = <&xo_config1>;
cooling-device = <&cpu5_hotplug 1 1>;
};
cpu6_hot_cdev {
trip = <&xo_config1>;
cooling-device = <&cpu6_hotplug 1 1>;
};
cpu7_hot_cdev {
trip = <&xo_config1>;
cooling-device = <&cpu7_hotplug 1 1>;
};
lte_cdev {
trip = <&xo_config1>;
cooling-device = <&modem_lte_dsc 255 255>;
};
nr_cdev {
trip = <&xo_config1>;
cooling-device = <&modem_nr_scg_dsc 255 255>;
};
display_cdev1 {
trip = <&display_test_config1>;
cooling-device = <&display_fps 1 1>;
};
display_cdev2 {
trip = <&display_test_config2>;
cooling-device = <&display_fps 2 2>;
};
display_cdev3 {
trip = <&display_test_config3>;
cooling-device = <&display_fps 3 3>;
};
display_cdev4 {
trip = <&display_test_config4>;
cooling-device = <&display_fps 4 4>;
};
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/clock/qcom,gcc-pineapple.h>
#include <dt-bindings/phy/qcom,usb3-4nm-qmp-combo.h>
&soc {
usb0: ssusb@a600000 {
compatible = "qcom,dwc-usb3-msm";
reg = <0xa600000 0x100000>,
<0x1fc6000 0x4>;
reg-names = "core_base",
"tcsr_dyn_en_dis";
#address-cells = <1>;
#size-cells = <1>;
ranges;
USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>;
clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
<&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_PRIM_SLEEP_CLK>;
clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
"utmi_clk", "sleep_clk";
resets = <&gcc GCC_USB30_PRIM_BCR>;
reset-names = "core_reset";
interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 14 IRQ_TYPE_EDGE_RISING>,
<&pdc 15 IRQ_TYPE_EDGE_RISING>,
<&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event_irq", "dp_hs_phy_irq",
"dm_hs_phy_irq", "ss_phy_irq";
qcom,use-pdc-interrupts;
qcom,use-eusb2-phy;
qcom,dis-sending-cm-l1-quirk;
qcom,core-clk-rate = <200000000>;
qcom,core-clk-rate-hs = <66666667>;
qcom,core-clk-rate-disconnected = <133333333>;
extcon = <&eud>;
qcom,num-gsi-evt-buffs = <0x3>;
qcom,gsi-reg-offset =
<0x0fc /* GSI_GENERAL_CFG */
0x110 /* GSI_DBL_ADDR_L */
0x120 /* GSI_DBL_ADDR_H */
0x130 /* GSI_RING_BASE_ADDR_L */
0x144 /* GSI_RING_BASE_ADDR_H */
0x1a4>; /* GSI_IF_STS */
interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb";
interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>,
<&aggre1_noc MASTER_USB3_0 &config_noc SLAVE_IPA_CFG>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>;
dwc3@a600000 {
compatible = "snps,dwc3";
reg = <0xa600000 0xd93c>;
iommus = <&apps_smmu 0x40 0x0>;
qcom,iommu-dma = "atomic";
qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
dma-coherent;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
usb-phy = <&eusb2_phy0>, <&usb_qmp_dp_phy>;
snps,disable-clk-gating;
snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x0>;
snps,is-utmi-l1-suspend;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
snps,dis_u2_susphy_quirk;
snps,ssp-u3-u0-quirk;
tx-fifo-resize;
dr_mode = "otg";
maximum-speed = "super-speed-plus";
usb-role-switch;
};
};
/* USB port related High Speed PHY */
eusb2_phy0: hsphy@88e3000 {
compatible = "qcom,usb-snps-eusb2-phy";
reg = <0x88e3000 0x154>,
<0x088e2000 0x4>,
<0x0c278000 0x4>;
reg-names = "eusb2_phy_base",
"eud_enable_reg",
"eud_detect_reg";
vdd-supply = <&pm_v8_l1>;
qcom,vdd-voltage-level = <0 880000 880000>;
vdda12-supply = <&pm_v8_l3>;
clocks = <&rpmhcc RPMH_CXO_PAD_CLK>,
<&tcsrcc TCSR_USB2_CLKREF_EN>;
clock-names = "ref_clk_src", "ref_clk";
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
reset-names = "phy_reset";
};
/* USB port related QMP USB DP Combo PHY */
usb_qmp_dp_phy: ssphy@88e8000 {
compatible = "qcom,usb-ssphy-qmp-dp-combo";
reg = <0x88e8000 0x3000>;
reg-names = "qmp_phy_base";
vdd-supply = <&pm_v6g_l3>;
qcom,vdd-voltage-level = <0 912000 912000>;
qcom,vdd-max-load-uA = <47000>;
core-supply = <&pm_v8_l3>;
usb3_dp_phy_gdsc-supply = <&gcc_usb3_phy_gdsc>;
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>,
<&usb3_phy_wrapper_gcc_usb30_pipe_clk>,
<&rpmhcc RPMH_CXO_PAD_CLK>,
<&tcsrcc TCSR_USB3_CLKREF_EN>,
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux",
"pipe_clk_ext_src", "ref_clk_src",
"ref_clk", "com_aux_clk";
resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
<&gcc GCC_USB3_PHY_PRIM_BCR>;
reset-names = "global_phy_reset", "phy_reset";
pinctrl-names = "default";
pinctrl-0 = <&usb3phy_portselect_default>;
qcom,qmp-phy-reg-offset =
<USB3_DP_PCS_PCS_STATUS1
USB3_DP_PCS_USB3_AUTONOMOUS_MODE_CTRL
USB3_DP_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
USB3_DP_PCS_POWER_DOWN_CONTROL
USB3_DP_PCS_SW_RESET
USB3_DP_PCS_START_CONTROL
0xffff /* USB3_PHY_PCS_MISC_TYPEC_CTRL */
USB3_DP_COM_POWER_DOWN_CTRL
USB3_DP_COM_SW_RESET
USB3_DP_COM_RESET_OVRD_CTRL
USB3_DP_COM_PHY_MODE_CTRL
USB3_DP_COM_TYPEC_CTRL
USB3_DP_PCS_AON_CLAMP_ENABLE>;
qcom,qmp-phy-init-seq =
/* <reg_offset, value> */
<USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xC0
USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x01
USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x02
USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1 0x16
USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1 0x36
USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1 0x04
USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1 0x16
USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1 0x41
USB3_DP_QSERDES_COM_DEC_START_MODE1 0x41
USB3_DP_QSERDES_COM_DEC_START_MSB_MODE1 0x00
USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1 0x55
USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1 0x75
USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1 0x01
USB3_DP_QSERDES_COM_HSCLK_SEL_1 0x01
USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1 0x25
USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1 0x02
USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x5C
USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x0F
USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x5C
USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x0F
USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xC0
USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x01
USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x02
USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x16
USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0 0x36
USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0 0x08
USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0 0x1A
USB3_DP_QSERDES_COM_DEC_START_MODE0 0x41
USB3_DP_QSERDES_COM_DEC_START_MSB_MODE0 0x00
USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0 0x55
USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0 0x75
USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0 0x01
USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0x25
USB3_DP_QSERDES_COM_VCO_TUNE2_MODE0 0x02
USB3_DP_QSERDES_COM_BG_TIMER 0x0A
USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x01
USB3_DP_QSERDES_COM_SSC_PER1 0x62
USB3_DP_QSERDES_COM_SSC_PER2 0x02
USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0C
USB3_DP_QSERDES_COM_SYSCLK_EN_SEL 0x1A
USB3_DP_QSERDES_COM_LOCK_CMP_CFG 0x14
USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x04
USB3_DP_QSERDES_COM_CORE_CLK_EN 0x20
USB3_DP_QSERDES_COM_CMN_CONFIG_1 0x16
USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_1 0xB6
USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_2 0x4B
USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_3 0x37
USB3_DP_QSERDES_COM_ADDITIONAL_MISC 0x0C
USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x00
USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x00
USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x1F
USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x09
USB3_DP_QSERDES_TXA_LANE_MODE_1 0xF5
USB3_DP_QSERDES_TXA_LANE_MODE_3 0x3F
USB3_DP_QSERDES_TXA_LANE_MODE_4 0x3F
USB3_DP_QSERDES_TXA_LANE_MODE_5 0x5F
USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12
USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x21
USB3_DP_QSERDES_RXA_UCDR_FO_GAIN 0x0A
USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x06
USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x2F
USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x7F
USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0xFF
USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x0F
USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x99
USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1 0x08
USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2 0x08
USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x00
USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x0A
USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0xA0
USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x54
USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x0F
USB3_DP_QSERDES_RXA_GM_CAL 0x13
USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0F
USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4A
USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x0A
USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0x07
USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x00
USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47
USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x04
USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E
USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0x3F
USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0xBF
USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0xFF
USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0xDF
USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0xED
USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0xDC
USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0x5C
USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0x9C
USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x1D
USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0x09
USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x04
USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x38
USB3_DP_QSERDES_RXA_DCC_CTRL1 0x0C
USB3_DP_QSERDES_RXA_VTH_CODE 0x10
USB3_DP_QSERDES_RXA_SIGDET_CAL_CTRL1 0x14
USB3_DP_QSERDES_RXA_SIGDET_CAL_TRIM 0x08
USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x00
USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x00
USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x1F
USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x09
USB3_DP_QSERDES_TXB_LANE_MODE_1 0xF5
USB3_DP_QSERDES_TXB_LANE_MODE_3 0x3F
USB3_DP_QSERDES_TXB_LANE_MODE_4 0x3F
USB3_DP_QSERDES_TXB_LANE_MODE_5 0x5F
USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12
USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x05
USB3_DP_QSERDES_RXB_UCDR_FO_GAIN 0x0A
USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x06
USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x2F
USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x7F
USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0xFF
USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x0F
USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x99
USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1 0x08
USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2 0x08
USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x00
USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x0A
USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0xA0
USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x54
USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x0F
USB3_DP_QSERDES_RXB_GM_CAL 0x13
USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0F
USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4A
USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x0A
USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0x07
USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x00
USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47
USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x04
USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E
USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0xBF
USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0xBF
USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0xBF
USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0xDF
USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0xFD
USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0xDC
USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0x5C
USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0x9C
USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x1D
USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0x09
USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x04
USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x38
USB3_DP_QSERDES_RXB_DCC_CTRL1 0x0C
USB3_DP_QSERDES_RXB_VTH_CODE 0x10
USB3_DP_QSERDES_RXB_SIGDET_CAL_CTRL1 0x14
USB3_DP_QSERDES_RXB_SIGDET_CAL_TRIM 0x08
USB3_DP_PCS_LOCK_DETECT_CONFIG1 0xC4
USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x89
USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x20
USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x13
USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x21
USB3_DP_PCS_RX_SIGDET_LVL 0x99
USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7
USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_H 0x03
USB3_DP_PCS_CDR_RESET_TIME 0x0A
USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x88
USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x13
USB3_DP_PCS_PCS_TX_RX_CONFIG 0x0C
USB3_DP_PCS_EQ_CONFIG1 0x4B
USB3_DP_PCS_EQ_CONFIG5 0x10
USB3_DP_PCS_USB3_POWER_STATE_CONFIG1 0x68
USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8
USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07
USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40
USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x00>;
};
usb_audio_qmi_dev {
compatible = "qcom,usb-audio-qmi-dev";
iommus = <&apps_smmu 0x100b 0x0>;
qcom,iommu-dma = "disabled";
qcom,usb-audio-stream-id = <0xb>;
qcom,usb-audio-intr-num = <2>;
};
};

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@@ -0,0 +1,14 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "pineapple-v2.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Pineapple v2 SoC";
compatible = "qcom,pineapple";
qcom,board-id = <0 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "pineapple.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Pineapple v2 SoC";
compatible = "qcom,pineapple";
qcom,msm-id = <557 0x20000>;
};
&camcc {
compatible = "qcom,pineapple-camcc-v2", "syscon";
};
&videocc {
compatible = "qcom,pineapple-videocc-v2", "syscon";
};
&qcom_memlat {
ddr {
silver {
qcom,cpufreq-memfreq-tbl =
< 1132800 547000 >,
< 1574400 768000 >,
< 2265600 1555000 >;
};
gold {
qcom,cpufreq-memfreq-tbl =
< 614400 547000 >,
< 960000 768000 >,
< 1190400 1555000 >,
< 1401600 2092000 >,
< 1920000 2736000 >,
< 2764800 3686000 >,
< 3187200 4224000 >;
};
prime {
qcom,cpufreq-memfreq-tbl =
< 614400 547000 >,
< 960000 768000 >,
< 1190400 1555000 >,
< 1401600 2092000 >,
< 1920000 2736000 >,
< 2764800 3686000 >,
< 3187200 4224000 >;
};
gold-compute {
qcom,cpufreq-memfreq-tbl =
< 2131200 547000 >,
< 3187200 2092000 >;
};
prime-latfloor {
qcom,cpufreq-memfreq-tbl =
< 2764800 547000 >,
< 3187200 4224000 >;
};
};
llcc {
silver {
qcom,cpufreq-memfreq-tbl =
< 902400 300000 >,
< 1574400 466000 >,
< 2265600 600000 >;
};
gold {
qcom,cpufreq-memfreq-tbl =
< 614400 300000 >,
< 1190400 466000 >,
< 1401600 600000 >,
< 1920000 806000 >,
< 2764800 933000 >,
< 3187200 1066000 >;
};
gold-compute {
qcom,cpufreq-memfreq-tbl =
< 2131200 300000 >,
< 3187200 600000 >;
};
};
l3 {
silver {
qcom,cpufreq-memfreq-tbl =
< 307200 307200 >,
< 460800 384000 >,
< 556800 499200 >,
< 787200 729600 >,
< 902400 844800 >,
< 1017600 940800 >,
< 1132800 1036800 >,
< 1248000 1132800 >,
< 1344000 1248000 >,
< 1574400 1440000 >,
< 1804800 1555200 >,
< 1920000 1651200 >,
< 2035200 1843200 >,
< 2265600 2035200 >;
};
gold {
qcom,cpufreq-memfreq-tbl =
< 499200 307200 >,
< 614400 499200 >,
< 960000 844800 >,
< 1190400 1036800 >,
< 1401600 1248000 >,
< 1920000 1440000 >,
< 2572800 1651200 >,
< 2764800 1843200 >,
< 3187200 2035200 >;
};
prime {
qcom,cpufreq-memfreq-tbl =
< 499200 307200 >,
< 614400 499200 >,
< 960000 844800 >,
< 1190400 1036800 >,
< 1401600 1248000 >,
< 1920000 1440000 >,
< 2572800 1651200 >,
< 2764800 1843200 >,
< 3187200 2035200 >;
};
prime-compute {
qcom,cpufreq-memfreq-tbl =
< 2131200 307200 >,
< 3187200 2035200 >;
};
};
ddrqos {
gold {
qcom,cpufreq-memfreq-tbl =
< 1920000 0 >,
< 3187200 1 >;
};
prime {
qcom,cpufreq-memfreq-tbl =
< 1401600 0 >,
< 3187200 1 >;
};
prime-latfloor {
qcom,cpufreq-memfreq-tbl =
< 2131200 0 >,
< 3187200 1 >;
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "pineapple.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Pineapple SoC";
compatible = "qcom,pineapple";
qcom,board-id = <0 0>;
};

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/dts-v1/;
#include "pineapplep-v2.dtsi"
/ {
model = "Qualcomm Technologies, Inc. PineappleP v2 SoC";
compatible = "qcom,pineapplep";
qcom,board-id = <0 0>;
};

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#include "pineapple-v2.dtsi"
/ {
model = "Qualcomm Technologies, Inc. PineappleP v2 SoC";
compatible = "qcom,pineapplep";
qcom,msm-id = <577 0x20000>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "pineapplep.dtsi"
/ {
model = "Qualcomm Technologies, Inc. PineappleP SoC";
compatible = "qcom,pineapplep";
qcom,board-id = <0 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "pineapple.dtsi"
/ {
model = "Qualcomm Technologies, Inc. PineappleP SoC";
compatible = "qcom,pineapplep";
qcom,msm-id = <577 0x10000>;
};

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@@ -12,6 +12,33 @@ _platform_map = {
{"name": "sun-rumi-overlay.dtbo"}, {"name": "sun-rumi-overlay.dtbo"},
], ],
}, },
"pineapple": {
"dtb_list": [
{"name": "pineapple.dtb"},
{"name": "pineapple-v2.dtb"},
{
"name": "pineapplep.dtb",
"apq": True,
},
{
"name": "pineapplep-v2.dtb",
"apq": True,
},
],
"dtbo_list": [
{"name": "pineapple-atp-overlay.dtbo"},
{"name": "pineapple-cdp-nfc-overlay.dtbo"},
{"name": "pineapple-cdp-overlay.dtbo"},
{"name": "pineapple-mtp-nfc-overlay.dtbo"},
{"name": "pineapple-mtp-overlay.dtbo"},
{"name": "pineapple-qrd-overlay.dtbo"},
{"name": "pineapple-rcm-overlay.dtbo"},
{
"name": "pineapple-rumi-overlay.dtbo",
"apq": False,
},
],
},
} }
def _get_dtb_lists(target, dt_overlay_supported): def _get_dtb_lists(target, dt_overlay_supported):

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
&spmi_bus {
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
pm8010_m: qcom,pm8010@c {
compatible = "qcom,spmi-pmic";
reg = <0xc SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm8010m_tz: pm8010m-temp-alarm@2400 {
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400>;
interrupts = <0xc 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
};
pm8010_n: qcom,pm8010@d {
compatible = "qcom,spmi-pmic";
reg = <0xd SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm8010n_tz: pm8010n-temp-alarm@2400 {
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400>;
interrupts = <0xd 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
};
};
&thermal_zones {
pm8010m_tz {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-governor = "step_wise";
thermal-sensors = <&pm8010m_tz>;
trips {
trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
pm8010n_tz {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-governor = "step_wise";
thermal-sensors = <&pm8010n_tz>;
trips {
trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
&spmi_bus {
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
qcom,pm8550@1 {
compatible = "qcom,spmi-pmic";
reg = <0x1 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm8550_tz: pm8550-temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pm8550_gpios: pinctrl@8800 {
compatible = "qcom,pm8550-gpio";
reg = <0x8800>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pm8550_pwm_1: pwms@e800 {
compatible = "qcom,pwm-lpg";
reg = <0xe800>;
reg-names = "lpg-base";
#pwm-cells = <2>;
qcom,num-lpg-channels = <3>;
nvmem = <&pmk8550_sdam_21 &pmk8550_sdam_22>;
nvmem-names = "lpg_chan_sdam", "lut_sdam";
qcom,lut-sdam-base = <0x45>;
qcom,lut-patterns = <0 10 20 30 40 50 60 70 80 90 100
90 80 70 60 50 40 30 20 10 0>;
qcom,tick-duration-us = <7800>;
lpg@1 {
qcom,lpg-chan-id = <1>;
qcom,ramp-step-ms = <100>;
qcom,ramp-low-index = <0>;
qcom,ramp-high-index = <19>;
qcom,ramp-pattern-repeat;
qcom,lpg-sdam-base = <0x48>;
};
lpg@2 {
qcom,lpg-chan-id = <2>;
qcom,ramp-step-ms = <100>;
qcom,ramp-low-index = <0>;
qcom,ramp-high-index = <19>;
qcom,ramp-pattern-repeat;
qcom,lpg-sdam-base = <0x56>;
};
lpg@3 {
qcom,lpg-chan-id = <3>;
qcom,ramp-step-ms = <100>;
qcom,ramp-low-index = <0>;
qcom,ramp-high-index = <19>;
qcom,ramp-pattern-repeat;
qcom,lpg-sdam-base = <0x64>;
};
};
pm8550_pwm_2: pwms@eb00 {
compatible = "qcom,pwm-lpg";
reg = <0xeb00>;
reg-names = "lpg-base";
pwm-cells = <2>;
qcom,num-lpg-channels = <1>;
};
pm8550_rgb: qcom,leds@ef00 {
compatible = "qcom,tri-led";
reg = <0xef00>;
red {
label = "red";
pwms = <&pm8550_pwm_1 0 1000000>;
led-sources = <0>;
linux,default-trigger = "timer";
};
green {
label = "green";
pwms = <&pm8550_pwm_1 1 1000000>;
led-sources = <1>;
linux,default-trigger = "timer";
};
blue {
label = "blue";
pwms = <&pm8550_pwm_1 2 1000000>;
led-sources = <2>;
linux,default-trigger = "timer";
};
};
pm8550_bcl: bcl@4700 {
compatible = "qcom,bcl-v5";
reg = <0x4700 0x100>;
interrupts = <0x1 0x47 0x0 IRQ_TYPE_NONE>,
<0x1 0x47 0x1 IRQ_TYPE_NONE>,
<0x1 0x47 0x2 IRQ_TYPE_NONE>;
interrupt-names = "bcl-lvl0",
"bcl-lvl1",
"bcl-lvl2";
qcom,pmic7-threshold;
#thermal-sensor-cells = <1>;
};
pm8550_flash: qcom,flash_led@ee00 {
compatible = "qcom,pm8350c-flash-led";
reg = <0xee00>;
interrupts = <0x1 0xee 0x0 IRQ_TYPE_EDGE_RISING>,
<0x1 0xee 0x3 IRQ_TYPE_EDGE_RISING>,
<0x1 0xee 0x4 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "led-fault-irq",
"all-ramp-down-done-irq",
"all-ramp-up-done-irq";
qcom,thermal-derate-current = <200 500>;
status = "disabled";
pm8550_flash0: qcom,flash_0 {
label = "flash";
qcom,led-name = "led:flash_0";
qcom,max-current-ma = <1500>;
qcom,default-led-trigger = "flash0_trigger";
qcom,id = <0>;
qcom,duration-ms = <1280>;
qcom,ires-ua = <12500>;
};
pm8550_flash1: qcom,flash_1 {
label = "flash";
qcom,led-name = "led:flash_1";
qcom,max-current-ma = <1500>;
qcom,default-led-trigger = "flash1_trigger";
qcom,id = <1>;
qcom,duration-ms = <1280>;
qcom,ires-ua = <12500>;
};
pm8550_flash2: qcom,flash_2 {
label = "flash";
qcom,led-name = "led:flash_2";
qcom,max-current-ma = <1500>;
qcom,default-led-trigger = "flash2_trigger";
qcom,id = <2>;
qcom,duration-ms = <1280>;
qcom,ires-ua = <12500>;
};
pm8550_flash3: qcom,flash_3 {
label = "flash";
qcom,led-name = "led:flash_3";
qcom,max-current-ma = <1500>;
qcom,default-led-trigger = "flash3_trigger";
qcom,id = <3>;
qcom,duration-ms = <1280>;
qcom,ires-ua = <12500>;
};
pm8550_torch0: qcom,torch_0 {
label = "torch";
qcom,led-name = "led:torch_0";
qcom,max-current-ma = <500>;
qcom,default-led-trigger = "torch0_trigger";
qcom,id = <0>;
qcom,ires-ua = <12500>;
};
pm8550_torch1: qcom,torch_1 {
label = "torch";
qcom,led-name = "led:torch_1";
qcom,max-current-ma = <500>;
qcom,default-led-trigger = "torch1_trigger";
qcom,id = <1>;
qcom,ires-ua = <12500>;
};
pm8550_torch2: qcom,torch_2 {
label = "torch";
qcom,led-name = "led:torch_2";
qcom,max-current-ma = <500>;
qcom,default-led-trigger = "torch2_trigger";
qcom,id = <2>;
qcom,ires-ua = <12500>;
};
pm8550_torch3: qcom,torch_3 {
label = "torch";
qcom,led-name = "led:torch_3";
qcom,max-current-ma = <500>;
qcom,default-led-trigger = "torch3_trigger";
qcom,id = <3>;
qcom,ires-ua = <12500>;
};
pm8550_switch0: qcom,led_switch_0 {
label = "switch";
qcom,led-name = "led:switch_0";
qcom,default-led-trigger = "switch0_trigger";
};
pm8550_switch1: qcom,led_switch_1 {
label = "switch";
qcom,led-name = "led:switch_1";
qcom,default-led-trigger = "switch1_trigger";
};
pm8550_switch2: qcom,led_switch_2 {
label = "switch";
qcom,led-name = "led:switch_2";
qcom,default-led-trigger = "switch2_trigger";
};
};
};
};
&thermal_zones {
pm8550_temp_alarm: pm8550_tz {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-governor = "step_wise";
thermal-sensors = <&pm8550_tz>;
trips {
pm8550_trip0: trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
pm8550_trip1: trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "passive";
};
pm8550_trip2: trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
pm8550-bcl-lvl0 {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-governor = "step_wise";
thermal-sensors = <&pm8550_bcl 5>;
trips {
bcl_lvl0: bcl-lvl0 {
temperature = <1>;
hysteresis = <1>;
type = "passive";
};
};
};
pm8550-bcl-lvl1 {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-governor = "step_wise";
thermal-sensors = <&pm8550_bcl 6>;
trips {
bcl_lvl1: bcl-lvl1 {
temperature = <1>;
hysteresis = <1>;
type = "passive";
};
};
};
pm8550-bcl-lvl2 {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-governor = "step_wise";
thermal-sensors = <&pm8550_bcl 7>;
trips {
bcl_lvl2: bcl-lvl2 {
temperature = <1>;
hysteresis = <1>;
type = "passive";
};
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/input/qcom,hv-haptics.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
&spmi_bus {
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
qcom,pm8550b@7 {
compatible = "qcom,spmi-pmic";
reg = <0x7 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm8550b_tz: pm8550b-temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pm8550b_lite_tz: pm8550b-temp-alarm-lite@c00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xc00>;
interrupts = <0x7 0xc 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pm8550b_gpios: pinctrl@8800 {
compatible = "qcom,pm8550b-gpio";
reg = <0x8800>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pm8550b_haptics: qcom,hv-haptics@f000 {
compatible = "qcom,hv-haptics";
reg = <0xf000>, <0xf100>, <0xf200>;
interrupts = <0x7 0xf0 0x1 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "fifo-empty";
qcom,vmax-mv = <3600>;
qcom,brake-mode = <BRAKE_CLOSE_LOOP>;
qcom,brake-pattern = /bits/ 8 <0xff 0x3f 0x1f>;
qcom,lra-period-us = <6667>;
qcom,drv-sig-shape = <WF_SINE>;
qcom,brake-sig-shape = <WF_SINE>;
hap_swr_slave_reg: qcom,hap-swr-slave-reg {
regulator-name = "hap-swr-slave-reg";
};
effect_0 {
/* CLICK */
qcom,effect-id = <0>;
qcom,wf-vmax-mv = <3600>;
qcom,wf-pattern-data = <0x01f S_PERIOD_T_LRA 0>,
<0x03f S_PERIOD_T_LRA 0>,
<0x05f S_PERIOD_T_LRA 0>,
<0x07f S_PERIOD_T_LRA 0>,
<0x17f S_PERIOD_T_LRA 0>,
<0x15f S_PERIOD_T_LRA 0>,
<0x13f S_PERIOD_T_LRA 0>,
<0x11f S_PERIOD_T_LRA 0>;
qcom,wf-pattern-period-us = <6667>;
qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
qcom,wf-pattern-preload;
qcom,wf-auto-res-disable;
};
effect_1 {
/* DOUBLE_CLICK */
qcom,effect-id = <1>;
qcom,wf-vmax-mv = <3600>;
qcom,wf-pattern-data = <0x01f S_PERIOD_T_LRA 0>,
<0x03f S_PERIOD_T_LRA 0>,
<0x05f S_PERIOD_T_LRA 0>,
<0x07f S_PERIOD_T_LRA 0>,
<0x17f S_PERIOD_T_LRA 0>,
<0x15f S_PERIOD_T_LRA 0>,
<0x13f S_PERIOD_T_LRA 0>,
<0x11f S_PERIOD_T_LRA 0>;
qcom,wf-pattern-period-us = <6667>;
qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
qcom,wf-auto-res-disable;
};
effect_2 {
/* TICK */
qcom,effect-id = <2>;
qcom,wf-vmax-mv = <3600>;
qcom,wf-pattern-data = <0x01f S_PERIOD_T_LRA 0>,
<0x03f S_PERIOD_T_LRA 0>,
<0x05f S_PERIOD_T_LRA 0>,
<0x07f S_PERIOD_T_LRA 0>,
<0x17f S_PERIOD_T_LRA 0>,
<0x15f S_PERIOD_T_LRA 0>,
<0x13f S_PERIOD_T_LRA 0>,
<0x11f S_PERIOD_T_LRA 0>;
qcom,wf-pattern-period-us = <6667>;
qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
qcom,wf-auto-res-disable;
};
effect_3 {
/* THUD */
qcom,effect-id = <3>;
qcom,wf-vmax-mv = <3600>;
qcom,wf-pattern-data = <0x01f S_PERIOD_T_LRA 0>,
<0x03f S_PERIOD_T_LRA 0>,
<0x05f S_PERIOD_T_LRA 0>,
<0x07f S_PERIOD_T_LRA 0>,
<0x17f S_PERIOD_T_LRA 0>,
<0x15f S_PERIOD_T_LRA 0>,
<0x13f S_PERIOD_T_LRA 0>,
<0x11f S_PERIOD_T_LRA 0>;
qcom,wf-pattern-period-us = <6667>;
qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
qcom,wf-auto-res-disable;
};
effect_4 {
/* POP */
qcom,effect-id = <4>;
qcom,wf-vmax-mv = <3600>;
qcom,wf-pattern-data = <0x01f S_PERIOD_T_LRA 0>,
<0x03f S_PERIOD_T_LRA 0>,
<0x05f S_PERIOD_T_LRA 0>,
<0x07f S_PERIOD_T_LRA 0>,
<0x17f S_PERIOD_T_LRA 0>,
<0x15f S_PERIOD_T_LRA 0>,
<0x13f S_PERIOD_T_LRA 0>,
<0x11f S_PERIOD_T_LRA 0>;
qcom,wf-pattern-period-us = <6667>;
qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
qcom,wf-auto-res-disable;
};
effect_5 {
/* HEAVY CLICK */
qcom,effect-id = <5>;
qcom,wf-vmax-mv = <3600>;
qcom,wf-pattern-data = <0x01f S_PERIOD_T_LRA 0>,
<0x03f S_PERIOD_T_LRA 0>,
<0x05f S_PERIOD_T_LRA 0>,
<0x07f S_PERIOD_T_LRA 0>,
<0x17f S_PERIOD_T_LRA 0>,
<0x15f S_PERIOD_T_LRA 0>,
<0x13f S_PERIOD_T_LRA 0>,
<0x11f S_PERIOD_T_LRA 0>;
qcom,wf-pattern-period-us = <6667>;
qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
qcom,wf-auto-res-disable;
};
primitive_0 {
/* NOOP */
qcom,primitive-id = <0>;
qcom,wf-vmax-mv = <3600>;
qcom,wf-pattern-data = <0 S_PERIOD_T_LRA 0>,
<0 S_PERIOD_T_LRA 0>;
qcom,wf-pattern-period-us = <6667>;
qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
qcom,wf-auto-res-disable;
};
primitive_1 {
/* CLICK */
qcom,primitive-id = <1>;
qcom,wf-vmax-mv = <3600>;
qcom,wf-pattern-data = <0x0ff S_PERIOD_T_LRA 0>,
<0x07f S_PERIOD_T_LRA 0>;
qcom,wf-pattern-period-us = <6667>;
qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
qcom,wf-auto-res-disable;
};
primitive_2 {
/* THUD */
qcom,primitive-id = <2>;
qcom,wf-vmax-mv = <3600>;
qcom,wf-pattern-data = <0x0ff S_PERIOD_T_LRA 0>,
<0x07f S_PERIOD_T_LRA 0>;
qcom,wf-pattern-period-us = <6667>;
qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
qcom,wf-auto-res-disable;
};
primitive_3 {
/* SPIN */
qcom,primitive-id = <3>;
qcom,wf-vmax-mv = <3600>;
qcom,wf-pattern-data = <0x0ff S_PERIOD_T_LRA 0>,
<0x07f S_PERIOD_T_LRA 0>;
qcom,wf-pattern-period-us = <6667>;
qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
qcom,wf-auto-res-disable;
};
primitive_4 {
/* QUICK_RISE */
qcom,primitive-id = <4>;
qcom,wf-vmax-mv = <3600>;
qcom,wf-pattern-data = <0x0ff S_PERIOD_T_LRA 0>,
<0x07f S_PERIOD_T_LRA 0>;
qcom,wf-pattern-period-us = <6667>;
qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
qcom,wf-auto-res-disable;
};
primitive_5 {
/* SLOW_RISE */
qcom,primitive-id = <5>;
qcom,wf-vmax-mv = <3600>;
qcom,wf-pattern-data = <0x0ff S_PERIOD_T_LRA 0>,
<0x07f S_PERIOD_T_LRA 0>;
qcom,wf-pattern-period-us = <6667>;
qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
qcom,wf-auto-res-disable;
};
primitive_6 {
/* QUICK_FALL */
qcom,primitive-id = <6>;
qcom,wf-vmax-mv = <3600>;
qcom,wf-pattern-data = <0x0ff S_PERIOD_T_LRA 0>,
<0x07f S_PERIOD_T_LRA 0>;
qcom,wf-pattern-period-us = <6667>;
qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
qcom,wf-auto-res-disable;
};
primitive_7 {
/* LIGHT_TICK */
qcom,primitive-id = <7>;
qcom,wf-vmax-mv = <3600>;
qcom,wf-pattern-data = <0x0ff S_PERIOD_T_LRA 0>,
<0x07f S_PERIOD_T_LRA 0>;
qcom,wf-pattern-period-us = <6667>;
qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
qcom,wf-auto-res-disable;
};
primitive_8 {
/* LOW_TICK */
qcom,primitive-id = <8>;
qcom,wf-vmax-mv = <3600>;
qcom,wf-pattern-data = <0x0ff S_PERIOD_T_LRA 0>,
<0x07f S_PERIOD_T_LRA 0>;
qcom,wf-pattern-period-us = <6667>;
qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
qcom,wf-auto-res-disable;
};
};
pm8550b_bcl: bcl@4700 {
compatible = "qcom,bcl-v5";
reg = <0x4700 0x100>;
interrupts = <0x7 0x47 0x0 IRQ_TYPE_NONE>,
<0x7 0x47 0x1 IRQ_TYPE_NONE>,
<0x7 0x47 0x2 IRQ_TYPE_NONE>;
interrupt-names = "bcl-lvl0",
"bcl-lvl1",
"bcl-lvl2";
qcom,pmic7-threshold;
#thermal-sensor-cells = <1>;
};
bcl_soc: bcl-soc {
compatible = "qcom,msm-bcl-soc";
#thermal-sensor-cells = <0>;
};
pm8550b_eusb2_repeater: qcom,eusb2-repeater@fd00 {
compatible = "qcom,pmic-eusb2-repeater";
reg = <0xfd00>;
};
};
};
&thermal_zones {
pm8550b_temp_alarm: pm8550b_tz {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-governor = "step_wise";
thermal-sensors = <&pm8550b_tz>;
trips {
pm8550b_trip0: trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
pm8550b_trip1: trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "passive";
};
pm8550b_trip2: trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
pm8550b_lite_temp_alarm: pm8550b_lite_tz {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-governor = "step_wise";
thermal-sensors = <&pm8550b_lite_tz>;
trips {
trip0 {
temperature = <125000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <135000>;
hysteresis = <0>;
type = "passive";
};
trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
pm8550b-ibat-lvl0 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pm8550b_bcl 0>;
trips {
ibat_lvl0:ibat-lvl0 {
temperature = <10000>;
hysteresis = <200>;
type = "passive";
};
};
};
pm8550b-ibat-lvl1 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pm8550b_bcl 1>;
trips {
ibat_lvl1:ibat-lvl1 {
temperature = <11500>;
hysteresis = <200>;
type = "passive";
};
};
};
pm8550b-bcl-lvl0 {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pm8550b_bcl 5>;
trips {
thermal-engine-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
thermal-hal-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
b_bcl_lvl0: b-bcl-lvl0 {
temperature = <1>;
hysteresis = <1>;
type = "passive";
};
};
};
pm8550b-bcl-lvl1 {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pm8550b_bcl 6>;
trips {
thermal-engine-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
thermal-hal-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
b_bcl_lvl1: b-bcl-lvl1 {
temperature = <1>;
hysteresis = <1>;
type = "passive";
};
};
};
pm8550b-bcl-lvl2 {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pm8550b_bcl 7>;
trips {
thermal-engine-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
thermal-hal-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
b_bcl_lvl2: b-bcl-lvl2 {
temperature = <1>;
hysteresis = <1>;
type = "passive";
};
};
};
socd {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&bcl_soc>;
trips {
thermal-engine-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
thermal-hal-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
socd_trip: socd-trip {
temperature = <90>;
hysteresis = <0>;
type = "passive";
};
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
&spmi_bus {
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
qcom,pm8550ve@8 {
compatible = "qcom,spmi-pmic";
reg = <0x8 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm8550ve_tz: pm8550ve-temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x8 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pm8550ve_gpios: pinctrl@8800 {
compatible = "qcom,pm8550ve-gpio";
reg = <0x8800>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};
&thermal_zones {
pm8550ve_temp_alarm: pm8550ve_tz {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-governor = "step_wise";
thermal-sensors = <&pm8550ve_tz>;
trips {
pm8550ve_trip0: trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
pm8550ve_trip1: trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "passive";
};
pm8550ve_trip2: trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
&spmi_bus {
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
pm8550vs_c: qcom,pm8550vs@2 {
compatible = "qcom,spmi-pmic";
reg = <0x2 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm8550vs_c_tz: pm8550vs-c-temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pm8550vs_c_gpios: pinctrl@8800 {
compatible = "qcom,pm8550vs-gpio";
reg = <0x8800>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
pm8550vs_d: qcom,pm8550vs@3 {
compatible = "qcom,spmi-pmic";
reg = <0x3 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm8550vs_d_tz: pm8550vs-d-temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pm8550vs_d_gpios: pinctrl@8800 {
compatible = "qcom,pm8550vs-gpio";
reg = <0x8800>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
pm8550vs_e: qcom,pm8550vs@4 {
compatible = "qcom,spmi-pmic";
reg = <0x4 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm8550vs_e_tz: pm8550vs-e-temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pm8550vs_e_gpios: pinctrl@8800 {
compatible = "qcom,pm8550vs-gpio";
reg = <0x8800>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
pm8550vs_g: qcom,pm8550vs@6 {
compatible = "qcom,spmi-pmic";
reg = <0x6 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm8550vs_g_tz: pm8550vs-g-temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pm8550vs_g_gpios: pinctrl@8800 {
compatible = "qcom,pm8550vs-gpio";
reg = <0x8800>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};
&thermal_zones {
pm8550vs_c_temp_alarm: pm8550vs_c_tz {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-governor = "step_wise";
thermal-sensors = <&pm8550vs_c_tz>;
trips {
pm8550vs_c_trip0: trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
pm8550vs_c_trip1: trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "passive";
};
pm8550vs_c_trip2: trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
pm8550vs_d_temp_alarm: pm8550vs_d_tz {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-governor = "step_wise";
thermal-sensors = <&pm8550vs_d_tz>;
trips {
pm8550vs_d_trip0: trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
pm8550vs_d_trip1: trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "passive";
};
pm8550vs_d_trip2: trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
pm8550vs_e_temp_alarm: pm8550vs_e_tz {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-governor = "step_wise";
thermal-sensors = <&pm8550vs_e_tz>;
trips {
pm8550vs_e_trip0: trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
pm8550vs_e_trip1: trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "passive";
};
pm8550vs_e_trip2: trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
pm8550vs_g_temp_alarm: pm8550vs_g_tz {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-governor = "step_wise";
thermal-sensors = <&pm8550vs_g_tz>;
trips {
pm8550vs_g_trip0: trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
pm8550vs_g_trip1: trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "passive";
};
pm8550vs_g_trip2: trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/iio/qcom,spmi-adc5-gen3-pmk8550.h>
#include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h>
#include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550b.h>
#define PM8550VE_SID 8
#include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550vx.h>
&spmi_bus {
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
qcom,pmk8550@0 {
compatible = "qcom,spmi-pmic";
reg = <0x0 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmk8550_sdam_1: sdam@7000 {
compatible = "qcom,spmi-sdam";
reg = <0x7000>;
#address-cells = <1>;
#size-cells = <1>;
ocp_log: ocp-log@76 {
reg = <0x76 0x6>;
};
};
pmk8550_sdam_2: sdam@7100 {
compatible = "qcom,spmi-sdam";
reg = <0x7100>;
#address-cells = <1>;
#size-cells = <1>;
restart_reason: restart@48 {
reg = <0x48 0x1>;
bits = <1 7>;
};
alarm_log: alarm-log@76 {
reg = <0x76 0x6>;
};
};
pmk8550_sdam_5: sdam@7400 {
compatible = "qcom,spmi-sdam";
reg = <0x7400>;
};
pmk8550_sdam_6: sdam@7500 {
compatible = "qcom,spmi-sdam";
reg = <0x7500>;
};
pmk8550_sdam_21: sdam@8400 {
compatible = "qcom,spmi-sdam";
reg = <0x8400>;
};
pmk8550_sdam_22: sdam@8500 {
compatible = "qcom,spmi-sdam";
reg = <0x8500>;
};
pon_hlos@1300 {
compatible = "qcom,pm8998-pon";
reg = <0x1300>, <0x800>;
reg-names = "pon_hlos", "pon_pbs";
pwrkey {
compatible = "qcom,pmk8350-pwrkey";
interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>;
linux,code = <KEY_POWER>;
};
resin {
compatible = "qcom,pmk8350-resin";
interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>;
linux,code = <KEY_VOLUMEDOWN>;
};
};
pmk8550_gpios: pinctrl@b800 {
compatible = "qcom,pmk8550-gpio";
reg = <0xb800>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pmk8550_rtc: rtc@6100 {
compatible = "qcom,pmk8350-rtc";
reg = <0x6100>, <0x6200>;
reg-names = "rtc", "alarm";
interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>;
};
pmk8550_vadc: vadc@9000 {
compatible = "qcom,spmi-adc5-gen3";
reg = <0x9000>, <0x9100>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-names = "adc-sdam0", "adc-sdam1";
interrupts = <0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>,
<0x0 0x91 0x1 IRQ_TYPE_EDGE_RISING>;
#thermal-sensor-cells = <1>;
#io-channel-cells = <1>;
io-channel-ranges;
/* PMK8550 Channel nodes */
pmk8550_offset_ref {
reg = <PMK8550_ADC5_GEN3_OFFSET_REF>;
label = "pmk8550_offset_ref";
qcom,pre-scaling = <1 1>;
};
pmk8550_vref_1p25 {
reg = <PMK8550_ADC5_GEN3_1P25VREF>;
label = "pmk8550_vref_1p25";
qcom,pre-scaling = <1 1>;
};
pmk8550_die_temp {
reg = <PMK8550_ADC5_GEN3_DIE_TEMP>;
label = "pmk8550_die_temp";
qcom,pre-scaling = <1 1>;
};
/* PM8550 Channel nodes */
pm8550_offset_ref {
reg = <PM8550_ADC5_GEN3_OFFSET_REF>;
label = "pm8550_offset_ref";
qcom,pre-scaling = <1 1>;
};
pm8550_vref_1p25 {
reg = <PM8550_ADC5_GEN3_1P25VREF>;
label = "pm8550_vref_1p25";
qcom,pre-scaling = <1 1>;
};
pm8550_die_temp {
reg = <PM8550_ADC5_GEN3_DIE_TEMP>;
label = "pm8550_die_temp";
qcom,pre-scaling = <1 1>;
};
pm8550_vph_pwr {
reg = <PM8550_ADC5_GEN3_VPH_PWR>;
label = "pm8550_vph_pwr";
qcom,pre-scaling = <1 3>;
};
/* PM8550B Channel nodes */
pm8550b_offset_ref {
reg = <PM8550B_ADC5_GEN3_OFFSET_REF>;
label = "pm8550b_offset_ref";
qcom,pre-scaling = <1 1>;
};
pm8550b_vref_1p25 {
reg = <PM8550B_ADC5_GEN3_1P25VREF>;
label = "pm8550b_vref_1p25";
qcom,pre-scaling = <1 1>;
};
pm8550b_die_temp {
reg = <PM8550B_ADC5_GEN3_DIE_TEMP>;
label = "pm8550b_die_temp";
qcom,pre-scaling = <1 1>;
};
pm8550b_lite_die_temp {
reg = <PM8550B_ADC5_GEN3_TEMP_ALARM_LITE>;
label = "pm8550b_lite_die_temp";
qcom,pre-scaling = <1 1>;
};
pm8550b_vph_pwr {
reg = <PM8550B_ADC5_GEN3_VPH_PWR>;
label = "pm8550b_vph_pwr";
qcom,pre-scaling = <1 3>;
};
pm8550b_vbat_sns_qbg {
reg = <PM8550B_ADC5_GEN3_VBAT_SNS_QBG>;
label = "pm8550b_vbat_sns_qbg";
qcom,pre-scaling = <1 3>;
};
/* PM8550VS_C Channel nodes */
pm8550vs_c_die_temp {
reg = <PM8550VS_C_ADC5_GEN3_DIE_TEMP>;
label = "pm8550vs_c_die_temp";
qcom,pre-scaling = <1 1>;
};
/* PM8550VS_D Channel nodes */
pm8550vs_d_die_temp {
reg = <PM8550VS_D_ADC5_GEN3_DIE_TEMP>;
label = "pm8550vs_d_die_temp";
qcom,pre-scaling = <1 1>;
};
/* PM8550VS_E Channel nodes */
pm8550vs_e_die_temp {
reg = <PM8550VS_E_ADC5_GEN3_DIE_TEMP>;
label = "pm8550vs_e_die_temp";
qcom,pre-scaling = <1 1>;
};
/* PM8550VS_G Channel nodes */
pm8550vs_g_die_temp {
reg = <PM8550VS_G_ADC5_GEN3_DIE_TEMP>;
label = "pm8550vs_g_die_temp";
qcom,pre-scaling = <1 1>;
};
/* PM8550VE Channel nodes */
pm8550ve_die_temp {
reg = <PM8550VE_ADC5_GEN3_DIE_TEMP>;
label = "pm8550ve_die_temp";
qcom,pre-scaling = <1 1>;
};
};
};
};

66
qcom/pmr735d.dtsi Normal file
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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
&spmi_bus {
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
qcom,pmr735d@a {
compatible = "qcom,spmi-pmic";
reg = <0xa SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmr735d_tz: pmr735d-temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0xa 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pmr735d_gpios: pinctrl@8800 {
compatible = "qcom,pmr735d-gpio";
reg = <0x8800>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};
&thermal_zones {
pmr735d_temp_alarm: pmr735d_tz {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-governor = "step_wise";
thermal-sensors = <&pmr735d_tz>;
trips {
pmr735d_trip0: trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
pmr735d_trip1: trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "passive";
};
pmr735d_trip2: trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
};