diff --git a/qcom/kera-qupv3.dtsi b/qcom/kera-qupv3.dtsi index 80f481be..643c8d7e 100644 --- a/qcom/kera-qupv3.dtsi +++ b/qcom/kera-qupv3.dtsi @@ -47,7 +47,8 @@ , , ; - qcom,gpii-mask = <0x1f>; + qcom,static-gpii-mask = <0x1>; + qcom,gpii-mask = <0x1e>; qcom,ev-factor = <1>; memory-region = <&qup1_gpi_iommu_region>; qcom,gpi-ee-offset = <0x10000>; @@ -92,8 +93,8 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se0_i2c_sda_active>, <&qupv3_se0_i2c_scl_active>; pinctrl-1 = <&qupv3_se0_i2c_sleep>; - dmas = <&gpi_dma1 0 0 3 64 0>, - <&gpi_dma1 1 0 3 64 0>; + dmas = <&gpi_dma1 0 0 3 64 2>, + <&gpi_dma1 1 0 3 64 2>; dma-names = "tx", "rx"; status = "disabled"; }; @@ -116,8 +117,8 @@ pinctrl-0 = <&qupv3_se0_spi_mosi_active>, <&qupv3_se0_spi_miso_active>, <&qupv3_se0_spi_clk_active>, <&qupv3_se0_spi_cs_active>; pinctrl-1 = <&qupv3_se0_spi_sleep>; - dmas = <&gpi_dma1 0 0 1 64 0>, - <&gpi_dma1 1 0 1 64 0>; + dmas = <&gpi_dma1 0 0 1 64 2>, + <&gpi_dma1 1 0 1 64 2>; dma-names = "tx", "rx"; spi-max-frequency = <50000000>; status = "disabled"; @@ -434,7 +435,8 @@ , , ; - qcom,gpii-mask = <0x1f>; + qcom,static-gpii-mask = <0x1>; + qcom,gpii-mask = <0x1e>; qcom,ev-factor = <1>; memory-region = <&qup2_gpi_iommu_region>; qcom,gpi-ee-offset = <0x10000>; @@ -480,8 +482,8 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se8_i2c_sda_active>, <&qupv3_se8_i2c_scl_active>; pinctrl-1 = <&qupv3_se8_i2c_sleep>; - dmas = <&gpi_dma2 0 0 3 64 0>, - <&gpi_dma2 1 0 3 64 0>; + dmas = <&gpi_dma2 0 0 3 64 2>, + <&gpi_dma2 1 0 3 64 2>; dma-names = "tx", "rx"; status = "disabled"; }; @@ -504,8 +506,8 @@ pinctrl-0 = <&qupv3_se8_spi_mosi_active>, <&qupv3_se8_spi_miso_active>, <&qupv3_se8_spi_clk_active>, <&qupv3_se8_spi_cs_active>; pinctrl-1 = <&qupv3_se8_spi_sleep>; - dmas = <&gpi_dma2 0 0 1 64 0>, - <&gpi_dma2 1 0 1 64 0>; + dmas = <&gpi_dma2 0 0 1 64 2>, + <&gpi_dma2 1 0 1 64 2>; dma-names = "tx", "rx"; spi-max-frequency = <50000000>; status = "disabled"; diff --git a/qcom/kera-vm.dtsi b/qcom/kera-vm.dtsi index 5ae595f2..a4836d26 100644 --- a/qcom/kera-vm.dtsi +++ b/qcom/kera-vm.dtsi @@ -71,6 +71,9 @@ vm-attrs = "context-dump", "crash-restart"; + iomemory-ranges = <0x0 0xa24000 0x0 0xa24000 0x0 0x4000 0x0 + 0x0 0x824000 0x0 0x824000 0x0 0x4000 0x0>; + /* For LEVM por usecases is QUP1_SE4 and QUP2_SE7. * QUP1_SE4: GPII5 : IRQ_316 * QUP2_SE7: GPII5 : IRQ_625 @@ -250,6 +253,165 @@ qcom,custom-bridge-size = <64>; qcom,support-hypervisor; }; + + /* + * QUP1 : SE0 - Secondary touch + * QUP2 : SE0 - Primary touch + */ + qup_iommu_group: qup_common_iommu_group { + iommu-addresses = <&gpi_dma1 0x00000000 0x00020000>, + <&qupv3_1 0x00000000 0x00020000>, + <&gpi_dma2 0x00000000 0x00020000>, + <&qupv3_2 0x00000000 0x00020000>; + }; + + /* GPI Instance */ + gpi_dma1: qcom,gpi-dma@a00000 { + compatible = "qcom,gpi-dma"; + reg = <0xa00000 0x60000>; + #dma-cells = <5>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0xb8 0x0>; + qcom,iommu-group = <&qup_iommu_group>; + dma-coherent; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,max-num-gpii = <12>; + qcom,static-gpii-mask = <0x20>; + qcom,gpii-mask = <0x0>; + qcom,ev-factor = <1>; + qcom,gpi-ee-offset = <0x10000>; + qcom,le-vm; + status = "ok"; + }; + + /* QUPv3_1 wrapper instance */ + qupv3_1: qcom,qupv3_1_geni_se@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0xac0000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus = <&apps_smmu 0xb8 0x0>; + qcom,iommu-group = <&qup_iommu_group>; + dma-coherent; + ranges; + status = "ok"; + + /* Secondary Tounch */ + qupv3_se0_i2c: i2c@a80000 { + compatible = "qcom,i2c-geni"; + reg = <0xa80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&gpi_dma1 0 0 3 64 0xc>, + <&gpi_dma1 1 0 3 64 0xc>; + dma-names = "tx", "rx"; + qcom,le-vm; + status = "disabled"; + }; + + /* Secondary Touch */ + qupv3_se0_spi: spi@a80000 { + compatible = "qcom,spi-geni"; + reg = <0xa80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + dmas = <&gpi_dma1 0 0 1 64 0xc>, + <&gpi_dma1 1 0 1 64 0xc>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,le-vm; + status = "disabled"; + }; + }; + + /* GPI Instance */ + gpi_dma2: qcom,gpi-dma@800000 { + compatible = "qcom,gpi-dma"; + reg = <0x800000 0x60000>; + #dma-cells = <5>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0x438 0x0>; + qcom,iommu-group = <&qup_iommu_group>; + dma-coherent; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,max-num-gpii = <12>; + qcom,static-gpii-mask = <0x20>; + qcom,gpii-mask = <0x0>; + qcom,ev-factor = <1>; + qcom,gpi-ee-offset = <0x10000>; + qcom,le-vm; + status = "ok"; + }; + + /* QUPv3_2 wrapper instance */ + qupv3_2: qcom,qupv3_2_geni_se@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x8c0000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + iommus = <&apps_smmu 0x438 0x0>; + qcom,iommu-group = <&qup_iommu_group>; + dma-coherent; + ranges; + status = "ok"; + + /* Touchscreen I2C Instance */ + qupv3_se8_i2c: i2c@880000 { + compatible = "qcom,i2c-geni"; + reg = <0x880000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&gpi_dma2 0 0 3 64 0xc>, + <&gpi_dma2 1 0 3 64 0xc>; + dma-names = "tx", "rx"; + qcom,le-vm; + status = "disabled"; + }; + + /* Touchscreen SPI Instance */ + qupv3_se8_spi: spi@880000 { + compatible = "qcom,spi-geni"; + reg = <0x880000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + dmas = <&gpi_dma2 0 0 1 64 0xc>, + <&gpi_dma2 1 0 1 64 0xc>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,le-vm; + status = "disabled"; + }; + }; }; #include "msm-arm-smmu-kera-vm.dtsi"