From 3744a8982504573399c7a9fa5b9387fb32b38e3f Mon Sep 17 00:00:00 2001
From: Anaadi Mishra <quic_anaadim@quicinc.com>
Date: Mon, 23 Sep 2024 16:36:06 +0530
Subject: [PATCH 1/2] ARM: dts: msm: Add support for RPMHCC and DEBUGCC on Kera
 platform

Add support for rpmh and debug clock controller nodes on Kera platform.
While at it, keep rpmhcc node as dummy for KERA rumi platform.

Change-Id: Ic11513d45bbc9b3f172a411f854a2348af4bfb94
Signed-off-by: Anaadi Mishra <quic_anaadim@quicinc.com>
---
 qcom/kera-rumi.dtsi |  6 ++++++
 qcom/kera.dtsi      | 52 +++++++++++++++++++++++++++++++++++++++------
 2 files changed, 51 insertions(+), 7 deletions(-)

diff --git a/qcom/kera-rumi.dtsi b/qcom/kera-rumi.dtsi
index 2b8a1e8c..8e1cfa60 100644
--- a/qcom/kera-rumi.dtsi
+++ b/qcom/kera-rumi.dtsi
@@ -158,3 +158,9 @@
 &APSS_OFF {
 	status = "disabled";
 };
+
+&rpmhcc {
+	compatible = "fixed-clock";
+	clock-output-names = "rpmh_clocks";
+	clock-frequency = <19200000>;
+};
diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi
index e81631e2..62afb64e 100644
--- a/qcom/kera.dtsi
+++ b/qcom/kera.dtsi
@@ -636,6 +636,11 @@
 				qcom,llcc-bcm-name = "SH5";
 
 			};
+
+			rpmhcc: clock-controller {
+				compatible = "qcom,tuna-rpmh-clk";
+				#clock-cells = <1>;
+			};
 		};
 	};
 
@@ -1732,13 +1737,6 @@
 		};
 	};
 
-	rpmhcc: clock-controller {
-		compatible = "fixed-clock";
-		clock-output-names = "rpmh_clocks";
-		clock-frequency = <19200000>;
-		#clock-cells = <1>;
-	};
-
 	cambistmclkcc: clock-controller@1760000 {
 		compatible = "qcom,tuna-cambistmclkcc", "syscon";
 		reg = <0x1760000 0x6000>;
@@ -3082,6 +3080,46 @@
 		qcom,count-unit = <0x10000>;
 		qcom,target-dev = <&qcom_ddr_dcvs_hw>;
 	};
+
+	apsscc: syscon@17a80000 {
+		compatible = "syscon";
+		reg = <0x17a80000 0x21000>;
+	};
+
+	mccc: syscon@240ba000 {
+		compatible = "syscon";
+		reg = <0x240ba000 0x800>;
+	};
+
+	debugcc: clock-controller@0 {
+		compatible = "qcom,kera-debugcc";
+		qcom,apsscc = <&apsscc>;
+		qcom,cambistmclkcc = <&cambistmclkcc>;
+		qcom,camcc = <&camcc>;
+		qcom,dispcc = <&dispcc>;
+		qcom,gcc = <&gcc>;
+		qcom,gpucc = <&gpucc>;
+		qcom,tcsrcc = <&tcsrcc>;
+		qcom,videocc = <&videocc>;
+		qcom,mccc = <&mccc>;
+		clocks = <&rpmhcc RPMH_CXO_CLK>,
+			 <&cambistmclkcc 0>,
+			 <&camcc 0>,
+			 <&dispcc 0>,
+			 <&gcc 0>,
+			 <&gpucc 0>,
+			 <&tcsrcc 0>,
+			 <&videocc 0>;
+		clock-names = "xo_clk_src",
+			      "cambistmclkcc",
+			      "camcc",
+			      "dispcc",
+			      "gcc",
+			      "gpucc",
+			      "tcsrcc",
+			      "videocc";
+		#clock-cells = <1>;
+	};
 };
 
 #include "tuna-gdsc.dtsi"

From 6fc3e14b6a2a3576e4090d4dbf8dbf176433d189 Mon Sep 17 00:00:00 2001
From: Anaadi Mishra <quic_anaadim@quicinc.com>
Date: Wed, 25 Sep 2024 12:26:45 +0530
Subject: [PATCH 2/2] ARM: dts: msm: Update videocc clock node as GenPD
 provider on Kera

Mark videocc clock node as GenPD provider and disable the video GDSC
regulator nodes for kera platform.
While at it, keep the gdsc's as it is on kera-rumi platform.

Change-Id: I4a41aacbaa7d144f72db48b9af3a336a92ef95aa
Signed-off-by: Anaadi Mishra <quic_anaadim@quicinc.com>
---
 qcom/kera-rumi.dtsi | 8 ++++++++
 qcom/kera.dtsi      | 4 ++--
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/qcom/kera-rumi.dtsi b/qcom/kera-rumi.dtsi
index 8e1cfa60..76d7f98c 100644
--- a/qcom/kera-rumi.dtsi
+++ b/qcom/kera-rumi.dtsi
@@ -164,3 +164,11 @@
 	clock-output-names = "rpmh_clocks";
 	clock-frequency = <19200000>;
 };
+
+&video_cc_mvs0_gdsc {
+	status = "ok";
+};
+
+&video_cc_mvs0c_gdsc {
+	status = "ok";
+};
diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi
index 62afb64e..ac2ac1de 100644
--- a/qcom/kera.dtsi
+++ b/qcom/kera.dtsi
@@ -1872,6 +1872,7 @@
 		reg-name = "cc_base";
 		vdd_mm-supply = <&VDD_CX_LEVEL>;
 		vdd_mxc-supply = <&VDD_MX_LEVEL>;
+		vdd_mm_mxc_voter-supply = <&VDD_CX_LEVEL>;
 		clocks = <&rpmhcc RPMH_CXO_CLK>,
 			 <&rpmhcc RPMH_CXO_CLK_A>,
 			 <&sleep_clk>,
@@ -1882,6 +1883,7 @@
 			      "iface";
 		#clock-cells = <1>;
 		#reset-cells = <1>;
+		#power-domain-cells = <1>;
 	};
 
 	qti,smmu-proxy {
@@ -3232,14 +3234,12 @@
 &video_cc_mvs0_gdsc {
 	clocks = <&gcc GCC_VIDEO_AHB_CLK>;
 	clock-names = "ahb_clk";
-	status = "ok";
 };
 
 &video_cc_mvs0c_gdsc {
 	clocks = <&gcc GCC_VIDEO_AHB_CLK>;
 	clock-names = "ahb_clk";
 	parent-supply = <&VDD_CX_LEVEL>;
-	status = "ok";
 };
 
 &reserved_memory {