ARM: dts: msm: Use correct UFS ref_clk on RUMI for Sun
Add RPMH_CXO_CLK as ref_clk to UFS for Sun on pre-sil. On Rumi ref_clk is to UFS PHY is 19.2MHz and actual device it is 38.4MHz. Also update correct gcc header file for sun. Change-Id: I78ed60095e5229405e7962f4676bfab7b7556676 Signed-off-by: Vivek Aknurwar <quic_viveka@quicinc.com>
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@@ -4,7 +4,8 @@
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/qcom,gcc-pineapple.h>
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#include <dt-bindings/clock/qcom,gcc-sun.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
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#include "sun-pmic-overlay.dtsi"
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@@ -141,6 +142,27 @@
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vdda-qref-supply = <&pm_v8i_l3>;
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vdda-qref-max-microamp = <30000>;
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clock-names =
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"core_clk",
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"bus_aggr_clk",
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"iface_clk",
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"core_clk_unipro",
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"core_clk_ice",
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"ref_clk",
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"tx_lane0_sync_clk",
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"rx_lane0_sync_clk",
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"rx_lane1_sync_clk";
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clocks =
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<&gcc GCC_UFS_PHY_AXI_CLK>,
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<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
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<&gcc GCC_UFS_PHY_AHB_CLK>,
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<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
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<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
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<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
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<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
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qcom,disable-lpm;
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status = "ok";
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