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ARM: dts: msm: Use correct UFS ref_clk on RUMI for Sun

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Add RPMH_CXO_CLK as ref_clk to UFS for Sun on pre-sil.
On Rumi ref_clk is to UFS PHY is 19.2MHz and actual device
it is 38.4MHz.
Also update correct gcc header file for sun.

Change-Id: I78ed60095e5229405e7962f4676bfab7b7556676
Signed-off-by: Vivek Aknurwar <quic_viveka@quicinc.com>
This commit is contained in:
Vivek Aknurwar
2023-10-17 17:16:55 -07:00
parent 234066ce47
commit e4710386ff
1 changed files with 23 additions and 1 deletions
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24
qcom/sun-rumi.dtsi
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@@ -4,7 +4,8 @@
*/ */
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/qcom,gcc-pineapple.h> #include <dt-bindings/clock/qcom,gcc-sun.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h> #include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
#include "sun-pmic-overlay.dtsi" #include "sun-pmic-overlay.dtsi"
@@ -141,6 +142,27 @@
vdda-qref-supply = <&pm_v8i_l3>; vdda-qref-supply = <&pm_v8i_l3>;
vdda-qref-max-microamp = <30000>; vdda-qref-max-microamp = <30000>;
clock-names =
"core_clk",
"bus_aggr_clk",
"iface_clk",
"core_clk_unipro",
"core_clk_ice",
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
"rx_lane1_sync_clk";
clocks =
<&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_UFS_PHY_AHB_CLK>,
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
qcom,disable-lpm; qcom,disable-lpm;
status = "ok"; status = "ok";