ARM: dts: msm: dsi: enable sun platforms
Adds initial dts nodes for CDP, MTP, RCM platforms. Also adds the common, display common, and pinctrl configurations. Change-Id: I473dbca3b60bd32c7d54bef600c8398ef6d35a59 Signed-off-by: Kirill Shpin <quic_kshpin@quicinc.com> Signed-off-by: Rohith Iyer <quic_rohiiyer@quicinc.com>
This commit is contained in:
Kirill Shpin
committed by
Rohith Iyer
Rohith Iyer
parent
d25f73950b
commit
e3b7d16634
2
Kbuild
2
Kbuild
@@ -1,4 +1,6 @@
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dtbo-$(CONFIG_ARCH_SUN) += display/sun-sde.dtbo \
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display/sun-sde-display-cdp-overlay.dtbo \
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display/sun-sde-display-mtp-overlay.dtbo \
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display/sun-sde-display-rumi-overlay.dtbo
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always-y := $(dtb-y) $(dtbo-y)
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@@ -331,5 +331,141 @@
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qcom,sde-dspp-dither = <0x82c 0x00010007>;
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};
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};
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};
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mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 {
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compatible = "qcom,dsi-ctrl-hw-v2.9";
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label = "dsi-ctrl-0";
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cell-index = <0>;
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frame-threshold-time-us = <800>;
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reg = <0xae94000 0x1000>,
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<0xaf0f000 0x4>,
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<0x0ae36000 0x300>;
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reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base";
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interrupt-parent = <&mdss_mdp>;
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interrupts = <4 0>;
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qcom,ctrl-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,ctrl-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "vdda-1p2";
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qcom,supply-min-voltage = <1200000>;
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qcom,supply-max-voltage = <1200000>;
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qcom,supply-enable-load = <16600>;
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qcom,supply-disable-load = <0>;
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};
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};
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};
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mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 {
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compatible = "qcom,dsi-ctrl-hw-v2.9";
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label = "dsi-ctrl-1";
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cell-index = <1>;
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frame-threshold-time-us = <800>;
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reg = <0xae96000 0x1000>,
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<0xaf0f000 0x4>,
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<0x0ae37000 0x300>;
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reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base";
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interrupt-parent = <&mdss_mdp>;
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interrupts = <5 0>;
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qcom,ctrl-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,ctrl-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "vdda-1p2";
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qcom,supply-min-voltage = <1200000>;
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qcom,supply-max-voltage = <1200000>;
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qcom,supply-enable-load = <16600>;
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qcom,supply-disable-load = <0>;
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};
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};
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};
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mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae95500 {
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compatible = "qcom,dsi-phy-v7.2";
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label = "dsi-phy-0";
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cell-index = <0>;
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#clock-cells = <1>;
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reg = <0xae95000 0xa00>,
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<0xae95500 0x400>,
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<0xae94200 0xa0>;
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reg-names = "dsi_phy", "pll_base", "dyn_refresh_base";
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pll-label = "dsi_pll_3nm";
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qcom,platform-strength-ctrl = [55 03
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55 03
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55 03
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55 03
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55 00];
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qcom,platform-lane-config = [00 00 0a 0a
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00 00 0a 0a
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00 00 0a 0a
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00 00 0a 0a
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00 00 8a 8a];
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qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
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qcom,phy-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,phy-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "vdda-0p9";
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qcom,supply-min-voltage = <880000>;
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qcom,supply-max-voltage = <880000>;
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qcom,supply-enable-load = <98000>;
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qcom,supply-disable-load = <96>;
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};
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};
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};
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mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae97500 {
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compatible = "qcom,dsi-phy-v7.2";
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label = "dsi-phy-1";
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cell-index = <1>;
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#clock-cells = <1>;
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reg = <0xae97000 0xa00>,
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<0xae97500 0x400>,
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<0xae96200 0xa0>;
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reg-names = "dsi_phy", "pll_base", "dyn_refresh_base";
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pll-label = "dsi_pll_3nm";
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qcom,platform-strength-ctrl = [55 03
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55 03
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55 03
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55 03
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55 00];
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qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
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qcom,platform-lane-config = [00 00 0a 0a
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00 00 0a 0a
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00 00 0a 0a
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00 00 0a 0a
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00 00 8a 8a];
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qcom,phy-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,phy-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "vdda-0p9";
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qcom,supply-min-voltage = <880000>;
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qcom,supply-max-voltage = <880000>;
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qcom,supply-enable-load = <98000>;
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qcom,supply-disable-load = <96>;
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};
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};
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};
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dsi_pll_codes_data:dsi_pll_codes {
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reg = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
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0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
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0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
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0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
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0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
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0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
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0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
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0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
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label = "dsi_pll_codes";
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};
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};
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@@ -14,4 +14,3 @@
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qcom,msm-id = <618 0x10000>, <618 0x20000>;
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qcom,board-id = <1 0>;
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};
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@@ -5,3 +5,179 @@
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#include "sun-sde-display.dtsi"
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&dsi_vtdr6130_amoled_cmd {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
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qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <10>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,mdss-brightness-max-level = <8191>;
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qcom,mdss-dsi-bl-inverted-dbv;
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qcom,platform-reset-gpio = <&tlmm 98 0>;
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qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
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};
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&dsi_vtdr6130_amoled_video {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
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qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <10>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,mdss-brightness-max-level = <8191>;
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qcom,mdss-dsi-bl-inverted-dbv;
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qcom,platform-reset-gpio = <&tlmm 98 0>;
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qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
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};
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&dsi_vtdr6130_amoled_120hz_cmd {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <10>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,mdss-brightness-max-level = <8191>;
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qcom,mdss-dsi-bl-inverted-dbv;
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qcom,platform-reset-gpio = <&tlmm 98 0>;
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};
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&dsi_nt37801_amoled_cmd {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <10>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,mdss-brightness-max-level = <8191>;
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qcom,mdss-dsi-bl-inverted-dbv;
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qcom,platform-reset-gpio = <&tlmm 98 0>;
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};
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&dsi_nt37801_amoled_video {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <10>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,mdss-brightness-max-level = <8191>;
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qcom,mdss-dsi-bl-inverted-dbv;
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qcom,platform-reset-gpio = <&tlmm 98 0>;
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};
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&dsi_vtdr6130_amoled_120hz_video {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <10>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,mdss-brightness-max-level = <8191>;
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qcom,mdss-dsi-bl-inverted-dbv;
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qcom,platform-reset-gpio = <&tlmm 98 0>;
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};
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&dsi_sim_panel_au {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <10>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,mdss-brightness-max-level = <8191>;
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qcom,mdss-dsi-bl-inverted-dbv;
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qcom,platform-reset-gpio = <&tlmm 98 0>;
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};
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&dsi_vtdr6130_amoled_qsync_144hz_cmd {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <10>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,mdss-brightness-max-level = <8191>;
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qcom,mdss-dsi-bl-inverted-dbv;
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qcom,platform-reset-gpio = <&tlmm 98 0>;
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};
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&dsi_vtdr6130_amoled_qsync_144hz_video {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <10>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,mdss-brightness-max-level = <8191>;
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qcom,mdss-dsi-bl-inverted-dbv;
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qcom,platform-reset-gpio = <&tlmm 98 0>;
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};
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&dsi_sharp_4k_dsc_cmd {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
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qcom,mdss-dsi-bl-min-level = <1>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,platform-reset-gpio = <&tlmm 98 0>;
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qcom,platform-bklight-en-gpio = <&tlmm 100 0>;
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};
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&dsi_sharp_4k_dsc_video {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
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qcom,mdss-dsi-bl-min-level = <1>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,platform-reset-gpio = <&tlmm 98 0>;
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qcom,platform-bklight-en-gpio = <&tlmm 100 0>;
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};
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&dsi_sim_cmd {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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};
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&dsi_sim_vid {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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};
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&dsi_sim_dsc_375_cmd {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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};
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&dsi_sim_dsc_10b_cmd {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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};
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&dsi_dual_sim_cmd {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,bl-dsc-cmd-state = "dsi_lp_mode";
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};
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&dsi_dual_sim_dsc_375_cmd {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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};
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&dsi_sim_sec_hd_cmd {
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qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
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qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_sim>;
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <1>;
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qcom,mdss-dsi-bl-max-level = <1023>;
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};
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&sde_dsi {
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avdd-supply = <&display_panel_avdd>;
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qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>;
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};
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&qupv3_se4_i2c {
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st_fts@49 {
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panel = <&dsi_nt37801_amoled_cmd
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&dsi_nt37801_amoled_cmd_cphy
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&dsi_nt37801_amoled_video
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&dsi_nt37801_amoled_video_cphy>;
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};
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};
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&qupv3_se15_i2c {
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st_fts@49 {
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panel = <&dsi_nt37801_amoled_cmd
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&dsi_nt37801_amoled_cmd_cphy
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&dsi_nt37801_amoled_video
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&dsi_nt37801_amoled_video_cphy>;
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};
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};
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914
display/sun-sde-display-common.dtsi
Normal file
914
display/sun-sde-display-common.dtsi
Normal file
@@ -0,0 +1,914 @@
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/*
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include "dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi"
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#include "dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi"
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#include "dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi"
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#include "dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi"
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#include "dsi-panel-sharp-dsc-4k-cmd.dtsi"
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#include "dsi-panel-sharp-dsc-4k-video.dtsi"
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#include "dsi-panel-sim-cmd-au.dtsi"
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#include "dsi-panel-sim-cmd.dtsi"
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#include "dsi-panel-sim-dsc-10bit-cmd.dtsi"
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#include "dsi-panel-sim-dsc375-cmd.dtsi"
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#include "dsi-panel-sim-dualmipi-cmd.dtsi"
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#include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi"
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#include "dsi-panel-sim-dualmipi-video.dtsi"
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#include "dsi-panel-sim-sec-hd-cmd.dtsi"
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#include "dsi-panel-sim-video.dtsi"
|
||||
#include "dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi"
|
||||
#include "dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi"
|
||||
#include "dsi-panel-vtdr6130-dsc-fhd-plus-cmd.dtsi"
|
||||
#include "dsi-panel-vtdr6130-dsc-fhd-plus-video.dtsi"
|
||||
#include "dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-cmd.dtsi"
|
||||
#include "dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-video.dtsi"
|
||||
|
||||
#include "sun-sde-display-pinctrl.dtsi"
|
||||
|
||||
&soc {
|
||||
dsi_panel_pwr_supply_sim: dsi_panel_pwr_supply_sim {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,panel-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "dummy";
|
||||
qcom,supply-min-voltage = <1800000>;
|
||||
qcom,supply-max-voltage = <1800000>;
|
||||
qcom,supply-enable-load = <220000>;
|
||||
qcom,supply-disable-load = <8000>;
|
||||
qcom,supply-post-on-sleep = <20>;
|
||||
};
|
||||
};
|
||||
|
||||
dsi_panel_pwr_supply: dsi_panel_pwr_supply {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,panel-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "vddio";
|
||||
qcom,supply-min-voltage = <1800000>;
|
||||
qcom,supply-max-voltage = <1800000>;
|
||||
qcom,supply-enable-load = <154000>;
|
||||
qcom,supply-disable-load = <45000>;
|
||||
qcom,supply-post-on-sleep = <20>;
|
||||
};
|
||||
|
||||
qcom,panel-supply-entry@1 {
|
||||
reg = <1>;
|
||||
qcom,supply-name = "vdd";
|
||||
qcom,supply-min-voltage = <1000000>;
|
||||
qcom,supply-max-voltage = <1100000>;
|
||||
qcom,supply-enable-load = <220000>;
|
||||
qcom,supply-disable-load = <471>;
|
||||
qcom,supply-post-on-sleep = <0>;
|
||||
};
|
||||
|
||||
qcom,panel-supply-entry@2 {
|
||||
reg = <2>;
|
||||
qcom,supply-name = "vci";
|
||||
qcom,supply-min-voltage = <3000000>;
|
||||
qcom,supply-max-voltage = <3000000>;
|
||||
qcom,supply-enable-load = <1000>;
|
||||
qcom,supply-disable-load = <300>;
|
||||
qcom,supply-post-on-sleep = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
dsi_panel_pwr_supply_avdd: dsi_panel_pwr_supply_avdd {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,panel-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "vddio";
|
||||
qcom,supply-min-voltage = <1800000>;
|
||||
qcom,supply-max-voltage = <1800000>;
|
||||
qcom,supply-enable-load = <220000>;
|
||||
qcom,supply-disable-load = <8000>;
|
||||
qcom,supply-post-on-sleep = <20>;
|
||||
};
|
||||
|
||||
qcom,panel-supply-entry@1 {
|
||||
reg = <1>;
|
||||
qcom,supply-name = "avdd";
|
||||
qcom,supply-min-voltage = <4600000>;
|
||||
qcom,supply-max-voltage = <6000000>;
|
||||
qcom,supply-enable-load = <260000>;
|
||||
qcom,supply-disable-load = <100>;
|
||||
};
|
||||
};
|
||||
|
||||
sde_dsi: qcom,dsi-display-primary {
|
||||
compatible = "qcom,dsi-display";
|
||||
label = "primary";
|
||||
|
||||
qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
|
||||
qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
|
||||
|
||||
pinctrl-names = "panel_active", "panel_suspend";
|
||||
pinctrl-0 = <&sde_dsi_active &sde_te_active>;
|
||||
pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
|
||||
|
||||
qcom,platform-te-gpio = <&tlmm 86 0>;
|
||||
qcom,panel-te-source = <0>;
|
||||
|
||||
qcom,mdp = <&mdss_mdp>;
|
||||
qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>;
|
||||
qcom,demura-panel-id = <0x0122e700 0x00000471>;
|
||||
};
|
||||
|
||||
sde_dsi1: qcom,dsi-display-secondary {
|
||||
compatible = "qcom,dsi-display";
|
||||
label = "secondary";
|
||||
|
||||
qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
|
||||
qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
|
||||
|
||||
pinctrl-names = "panel_active", "panel_suspend";
|
||||
pinctrl-0 = <&sde_dsi1_active &sde_te1_active>;
|
||||
pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>;
|
||||
|
||||
qcom,platform-te-gpio = <&tlmm 87 0>;
|
||||
qcom,panel-te-source = <1>;
|
||||
|
||||
qcom,mdp = <&mdss_mdp>;
|
||||
qcom,demura-panel-id = <0x0 0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
/* PHY TIMINGS REVISION YL with reduced margins */
|
||||
&dsi_vtdr6130_amoled_cmd {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1";
|
||||
|
||||
qcom,dsi-dyn-clk-enable;
|
||||
|
||||
qcom,esd-check-enabled;
|
||||
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
||||
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
|
||||
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-panel-status-value = <0x9c>;
|
||||
qcom,mdss-dsi-panel-status-read-length = <1>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07
|
||||
07 08 02 04 00 19 0c];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>;
|
||||
};
|
||||
|
||||
timing@1 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07
|
||||
07 08 02 04 00 19 0c];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>;
|
||||
};
|
||||
|
||||
timing@2 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07
|
||||
07 08 02 04 00 19 0c];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>;
|
||||
};
|
||||
|
||||
timing@3 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07
|
||||
07 08 02 04 00 19 0c];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sim_panel_au {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07
|
||||
07 08 02 04 00 19 0c];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_video {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1";
|
||||
qcom,dsi-supported-dfps-list = <144 120 90 60>;
|
||||
qcom,mdss-dsi-pan-enable-dynamic-fps;
|
||||
qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
|
||||
|
||||
qcom,dsi-dyn-clk-enable;
|
||||
qcom,dsi-dyn-clk-type = "constant-fps-adjust-hfp";
|
||||
|
||||
qcom,esd-check-enabled;
|
||||
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
||||
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
|
||||
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-panel-status-value = <0x9c>;
|
||||
qcom,mdss-dsi-panel-status-read-length = <1>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07
|
||||
07 08 02 04 00 19 0c];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,dsi-dyn-clk-list = <847480320 844537680 841595040>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_120hz_cmd {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
|
||||
qcom,esd-check-enabled;
|
||||
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
||||
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
|
||||
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-panel-status-value = <0x9c>;
|
||||
qcom,mdss-dsi-panel-status-read-length = <1>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07
|
||||
06 07 02 04 00 16 0b];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@1 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07
|
||||
06 07 02 04 00 16 0b];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@2 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07
|
||||
06 07 02 04 00 16 0b];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_120hz_video {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,dsi-supported-dfps-list = <120 90 60>;
|
||||
qcom,mdss-dsi-pan-enable-dynamic-fps;
|
||||
qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
|
||||
|
||||
qcom,esd-check-enabled;
|
||||
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
||||
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
|
||||
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-panel-status-value = <0x9c>;
|
||||
qcom,mdss-dsi-panel-status-read-length = <1>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07
|
||||
06 07 02 04 00 16 0b];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_cmd {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,esd-check-enabled;
|
||||
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
||||
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
|
||||
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-panel-status-value = <0x9c>;
|
||||
qcom,mdss-dsi-panel-status-read-length = <1>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07
|
||||
07 08 02 04 00 19 0c];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_video {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,esd-check-enabled;
|
||||
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
||||
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
|
||||
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-panel-status-value = <0x9c>;
|
||||
qcom,mdss-dsi-panel-status-read-length = <1>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07
|
||||
07 08 02 04 00 19 0c];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_cmd {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a
|
||||
0b 0a 02 04 00 21 0f];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_video {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a
|
||||
0b 0a 02 04 00 21 0f];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sharp_4k_dsc_cmd {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
|
||||
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
||||
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c];
|
||||
qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-panel-status-value = <0x77>;
|
||||
qcom,mdss-dsi-panel-on-check-value = <0x77>;
|
||||
qcom,mdss-dsi-panel-status-read-length = <1>;
|
||||
qcom,esd-check-enabled;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05
|
||||
05 06 02 04 00 12 0a];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sharp_4k_dsc_video {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
|
||||
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
||||
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c];
|
||||
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-panel-status-value = <0x77>;
|
||||
qcom,mdss-dsi-panel-on-check-value = <0x77>;
|
||||
qcom,mdss-dsi-panel-status-read-length = <1>;
|
||||
qcom,esd-check-enabled;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06
|
||||
06 07 02 04 00 15 0b];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sim_cmd {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,poms-align-panel-vsync;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 { /* WQHD 60FPS cmd-vid mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07
|
||||
07 07 02 04 00 16 0c];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,qsync-mode-min-refresh-rate = <50>;
|
||||
};
|
||||
|
||||
timing@1 { /* WQHD 60FPS vid mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07
|
||||
07 07 02 04 00 16 0c];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,qsync-mode-min-refresh-rate = <50>;
|
||||
};
|
||||
|
||||
timing@2 { /* FHD+ 60FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 25 0a 0a 1b 24 0a
|
||||
0a 0a 02 04 00 1f 0f];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,qsync-mode-min-refresh-rate = <10>;
|
||||
};
|
||||
|
||||
timing@3 { /* HD 60FPS cmd mode */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 29 0a 0b 1b 26 0a
|
||||
0b 0a 02 04 00 21 10];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,qsync-mode-min-refresh-rate = <48>;
|
||||
};
|
||||
|
||||
timing@4 { /* FHD+ 90FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 39 0f 0e 21 2a 0e
|
||||
0f 0d 02 04 00 2d 13];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,qsync-mode-min-refresh-rate = <30>;
|
||||
};
|
||||
|
||||
timing@5 { /* FHD+ 180 FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 69 1d 1d 35 2f 1b
|
||||
1d 18 02 04 00 51 21];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,qsync-mode-min-refresh-rate = <96>;
|
||||
};
|
||||
|
||||
timing@6 { /* FHD+ 240 FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 89 26 27 42 39 25
|
||||
27 1f 02 04 00 69 2a];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,qsync-mode-min-refresh-rate = <110>;
|
||||
};
|
||||
|
||||
timing@7 { /* FHD+ 120FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 4a 13 14 28 24 12
|
||||
14 11 02 04 00 39 18];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,qsync-mode-min-refresh-rate = <40>;
|
||||
};
|
||||
|
||||
timing@8 { /* FHD+ 144FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07
|
||||
06 07 02 04 00 16 0b];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,qsync-mode-min-refresh-rate = <60>;
|
||||
};
|
||||
|
||||
timing@9 { /* WQHD 1FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06
|
||||
06 07 02 04 00 15 0b];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,qsync-mode-min-refresh-rate = <1>;
|
||||
};
|
||||
|
||||
timing@10 { /* WQHD 5FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06
|
||||
06 07 02 04 00 15 0b];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,qsync-mode-min-refresh-rate = <1>;
|
||||
};
|
||||
|
||||
timing@11 { /* WQHD 10FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06
|
||||
06 07 02 04 00 15 0b];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,qsync-mode-min-refresh-rate = <5>;
|
||||
};
|
||||
|
||||
timing@12 { /* WQHD 24FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06
|
||||
06 07 02 04 00 15 0b];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,qsync-mode-min-refresh-rate = <15>;
|
||||
};
|
||||
|
||||
timing@13 { /* WQHD 30FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06
|
||||
06 07 02 04 00 15 0b];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,qsync-mode-min-refresh-rate = <22>;
|
||||
};
|
||||
|
||||
timing@14 { /* WQHD 60FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06
|
||||
06 07 02 04 00 15 0b];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,qsync-mode-min-refresh-rate = <30>;
|
||||
};
|
||||
|
||||
timing@15 { /* WQHD 90FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 19 23 09
|
||||
09 09 02 04 00 1d 0e];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
qcom,qsync-mode-min-refresh-rate = <10>;
|
||||
};
|
||||
|
||||
timing@16 { /* WQHD 120FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 2c 0c 0c 1d 27 0c
|
||||
0c 0b 02 04 00 24 11];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,qsync-mode-min-refresh-rate = <1>;
|
||||
};
|
||||
|
||||
timing@17 { /* WQHD 144FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 38 0e 0e 17 14 0e
|
||||
0e 0d 02 04 00 2b 12];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,qsync-mode-min-refresh-rate = <5>;
|
||||
};
|
||||
|
||||
timing@18 { /* WQHD 180FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 3d 0f 0f 19 15 0f
|
||||
10 0e 02 04 00 2f 13];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,qsync-mode-min-refresh-rate = <30>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sim_vid {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,dsi-supported-dfps-list = <144 120 90 60 30 10 1>;
|
||||
qcom,mdss-dsi-pan-enable-dynamic-fps;
|
||||
qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
|
||||
|
||||
qcom,qsync-enable;
|
||||
qcom,dsi-supported-qsync-min-fps-list = <1 1 1 1 1 1 1>;
|
||||
qcom,dsi-qsync-avr-step-list = <288 240 180 120 60 20 0>;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 24 0a 0a 1a 24 0a
|
||||
0a 09 02 04 00 1e 0f];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_375_cmd {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 { /* 1080p */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 14 1f 05
|
||||
05 06 02 04 00 13 0a];
|
||||
qcom,display-topology = <1 1 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@1 { /* qhd */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0c 02 02 10 1c 03
|
||||
03 02 02 04 00 0b 08];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>, /* dsc merge */
|
||||
<2 1 1>; /* 3d mux */
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_10b_cmd {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 { /* QHD 60fps */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 14 1f 05
|
||||
05 06 02 04 00 13 0a];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>, /* dsc merge */
|
||||
<2 1 1>; /* 3d mux */
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
|
||||
timing@1 { /* FHD+ 60fps cmd mode */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 10 1d 03
|
||||
03 02 02 04 00 0c 08];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>, /* dsc merge */
|
||||
<2 1 1>; /* 3d mux */
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
|
||||
timing@2 { /* QHD 90fps */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1d 08 07 17 22 08
|
||||
08 08 02 04 00 19 0d];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>, /* dsc merge */
|
||||
<2 1 1>; /* 3d mux */
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
|
||||
timing@3 { /* FHD+ 180FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1f 08 07 18 16 08
|
||||
08 08 02 04 00 1a 0d];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@4 { /* FHD+ 240FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a
|
||||
0b 0a 02 04 00 21 0f];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@5 { /* FHD+ 120FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 13 06
|
||||
06 06 02 04 00 13 0b];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@6 { /* FHD+ 1FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [03 04 00 00 0d 18 01
|
||||
00 01 02 04 00 05 05];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
|
||||
timing@7 { /* FHD+ 10FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 0d 1a 01
|
||||
01 01 02 04 00 07 06];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
|
||||
timing@8 { /* FHD+ 24FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 09 01 01 0e 1b 02
|
||||
01 01 02 04 00 08 06];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
|
||||
timing@9 { /* FHD+ 30FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0a 01 02 0e 1b 02
|
||||
02 01 02 04 00 09 07];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
|
||||
timing@10 { /* FHD+ 90FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 39 0f 0e 21 2a 0e
|
||||
0f 0d 02 04 00 2d 13];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@11 { /* FHD+ 144FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07
|
||||
06 07 02 04 00 16 0b];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_dual_sim_cmd {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 { /* 5K 60FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 44 11 12 25 2d 11
|
||||
12 0f 02 04 00 35 16];
|
||||
qcom,display-topology = <2 0 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@1 { /* FHD 120FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 17 15 07
|
||||
07 08 02 04 00 18 0c];
|
||||
qcom,display-topology = <2 0 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@2 { /* WQHD 60FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 21 07
|
||||
07 07 02 04 00 17 0c];
|
||||
qcom,display-topology = <2 0 2>,
|
||||
<1 0 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@3 { /* 4K 40FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 25 0a 0a 1b 24 0a
|
||||
0a 0a 02 04 00 1f 0f];
|
||||
qcom,display-topology = <2 0 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@4 { /* 5K 80FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 57 17 17 2e 33 17
|
||||
18 14 02 04 00 43 1c];
|
||||
qcom,display-topology = <2 0 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@5 { /* FHD 60FPS 24bpp cmd mode */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05
|
||||
05 06 02 04 00 12 0a];
|
||||
qcom,display-topology = <2 0 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@6 { /* FHD 60FPS 30bpp cmd mode */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 17 06 05 15 20 06
|
||||
06 07 02 04 00 15 0b];
|
||||
qcom,display-topology = <2 0 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_dual_sim_dsc_375_cmd {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 { /* 4k 30 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 11 1d 04
|
||||
04 03 02 04 00 0d 09];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@1 { /* 4k 60 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06
|
||||
06 07 02 04 00 15 0b];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@2 { /* 4k 90 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 19 23 09
|
||||
09 09 02 04 00 1d 0e];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@3 { /* 1080 30 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 0e 1b 01
|
||||
01 02 02 04 00 08 06];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@4 { /* 1080 60 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 0f 1c 03
|
||||
02 02 02 04 00 0a 07];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@5 { /* 1080 90 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 11 1d 04
|
||||
03 03 02 04 00 0d 08];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@6 { /* 1080 120 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 11 04 04 12 12 04
|
||||
04 03 02 04 00 0f 09];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@7 { /* qhd 30 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 0f 1c 02
|
||||
02 02 02 04 00 0a 07];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@8 { /* qhd 60 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 11 1d 04
|
||||
04 03 02 04 00 0d 09];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@9 { /* qhd 90 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 1f 05
|
||||
05 06 02 04 00 12 0a];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@10 { /* qhd 120 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07
|
||||
06 07 02 04 00 16 0b];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@11 { /* 5k */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 21 07
|
||||
07 07 02 04 00 17 0c];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@12 { /* 720p 30 FPS */
|
||||
qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 0d 1a 01
|
||||
01 01 02 04 00 07 06];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@13 { /* 720p 60 FPS */
|
||||
qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 0e 1b 01
|
||||
01 02 02 04 00 08 06];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@14 { /* 720p 90 FPS */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 0f 1c 02
|
||||
02 02 02 04 00 0a 07];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@15 { /* 720 120 FPS */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 0f 0f 03
|
||||
03 02 02 04 00 0a 08];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@16 { /* 1080 144FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 12 05
|
||||
05 06 02 04 00 12 0a];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@17 { /* WQHD 144 FPS*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1d 07 07 17 16 07
|
||||
07 08 02 04 00 19 0c];
|
||||
qcom,display-topology = <2 2 2>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sim_sec_hd_cmd {
|
||||
qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e
|
||||
04 04 03 02 04 00 0e 09];
|
||||
qcom,display-topology = <1 0 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -14,4 +14,3 @@
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>;
|
||||
qcom,board-id = <8 0>;
|
||||
};
|
||||
|
||||
|
||||
@@ -5,3 +5,92 @@
|
||||
|
||||
#include "sun-sde-display.dtsi"
|
||||
|
||||
&dsi_nt37801_amoled_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_sim_panel_au {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_sim_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_vid {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_375_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_10b_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,bl-dsc-cmd-state = "dsi_lp_mode";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_dsc_375_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_sec_hd_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <1023>;
|
||||
};
|
||||
|
||||
&sde_dsi {
|
||||
qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>;
|
||||
};
|
||||
|
||||
&qupv3_se4_i2c {
|
||||
st_fts@49 {
|
||||
panel = <&dsi_nt37801_amoled_cmd
|
||||
&dsi_nt37801_amoled_cmd_cphy
|
||||
&dsi_nt37801_amoled_video
|
||||
&dsi_nt37801_amoled_video_cphy>;
|
||||
};
|
||||
};
|
||||
|
||||
&battery_charger {
|
||||
qcom,display-panels = <&dsi_nt37801_amoled_cmd
|
||||
&dsi_nt37801_amoled_cmd_cphy
|
||||
&dsi_nt37801_amoled_video
|
||||
&dsi_nt37801_amoled_video_cphy>;
|
||||
};
|
||||
|
||||
113
display/sun-sde-display-pinctrl.dtsi
Normal file
113
display/sun-sde-display-pinctrl.dtsi
Normal file
@@ -0,0 +1,113 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&tlmm {
|
||||
pmx_sde: pmx_sde {
|
||||
sde_dsi_active: sde_dsi_active {
|
||||
mux {
|
||||
pins = "gpio98";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio98";
|
||||
drive-strength = <8>; /* 8 mA */
|
||||
bias-disable = <0>; /* no pull */
|
||||
};
|
||||
};
|
||||
|
||||
sde_dsi_suspend: sde_dsi_suspend {
|
||||
mux {
|
||||
pins = "gpio98";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio98";
|
||||
drive-strength = <2>; /* 2 mA */
|
||||
bias-pull-down; /* PULL DOWN */
|
||||
};
|
||||
};
|
||||
|
||||
sde_dsi1_active: sde_dsi1_active {
|
||||
mux {
|
||||
pins = "gpio97";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio97";
|
||||
drive-strength = <8>; /* 8 mA */
|
||||
bias-disable = <0>; /* no pull */
|
||||
};
|
||||
};
|
||||
|
||||
sde_dsi1_suspend: sde_dsi1_suspend {
|
||||
mux {
|
||||
pins = "gpio97";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio97";
|
||||
drive-strength = <2>; /* 2 mA */
|
||||
bias-pull-down; /* PULL DOWN */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pmx_sde_te: pmx_sde_te {
|
||||
sde_te_active: sde_te_active {
|
||||
mux {
|
||||
pins = "gpio86";
|
||||
function = "mdp_vsync";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio86";
|
||||
drive-strength = <2>; /* 2 mA */
|
||||
bias-pull-down; /* PULL DOWN */
|
||||
};
|
||||
};
|
||||
|
||||
sde_te_suspend: sde_te_suspend {
|
||||
mux {
|
||||
pins = "gpio86";
|
||||
function = "mdp_vsync";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio86";
|
||||
drive-strength = <2>; /* 2 mA */
|
||||
bias-pull-down; /* PULL DOWN */
|
||||
};
|
||||
};
|
||||
|
||||
sde_te1_active: sde_te1_active {
|
||||
mux {
|
||||
pins = "gpio87";
|
||||
function = "mdp_vsync";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio87";
|
||||
drive-strength = <2>; /* 2 mA */
|
||||
bias-pull-down; /* PULL DOWN */
|
||||
};
|
||||
};
|
||||
|
||||
sde_te1_suspend: sde_te1_suspend {
|
||||
mux {
|
||||
pins = "gpio87";
|
||||
function = "mdp_vsync";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio87";
|
||||
drive-strength = <2>; /* 2 mA */
|
||||
bias-pull-down; /* PULL DOWN */
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -4,6 +4,7 @@
|
||||
*/
|
||||
|
||||
#include "sun-sde.dtsi"
|
||||
#include "sun-sde-display-common.dtsi"
|
||||
#include <dt-bindings/clock/qcom,dispcc-sun.h>
|
||||
|
||||
&soc {
|
||||
@@ -18,9 +19,157 @@
|
||||
cell-index = <1>;
|
||||
label = "wb_display2";
|
||||
};
|
||||
|
||||
|
||||
display_panel_avdd: display_gpio_regulator@1 {
|
||||
compatible = "qti-regulator-fixed";
|
||||
regulator-name = "display_panel_avdd";
|
||||
regulator-min-microvolt = <5500000>;
|
||||
regulator-max-microvolt = <5500000>;
|
||||
regulator-enable-ramp-delay = <233>;
|
||||
enable-active-high;
|
||||
regulator-boot-on;
|
||||
proxy-supply = <&display_panel_avdd>;
|
||||
qcom,proxy-consumer-enable;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
};
|
||||
|
||||
&sde_dsi {
|
||||
clocks = <&mdss_dsi_phy0 0>,
|
||||
<&mdss_dsi_phy0 1>,
|
||||
<&mdss_dsi_phy1 2>,
|
||||
<&mdss_dsi_phy1 3>,
|
||||
/*
|
||||
* Currently the dsi clock handles are under the dsi
|
||||
* controller DT node. As soon as the controller probe
|
||||
* finishes, the dispcc sync state can get called before
|
||||
* the dsi_display probe potentially disturbing the clock
|
||||
* votes for cont_splash use case. Hence we are no longer
|
||||
* protected by the component model in this case against the
|
||||
* disp cc sync state getting triggered after the dsi_ctrl
|
||||
* probe. To protect against this incorrect sync state trigger
|
||||
* add this dummy MDP clk vote handle to the dsi_display
|
||||
* DT node. Since the dsi_display driver does not parse
|
||||
* MDP clock nodes, no actual vote shall be added and this
|
||||
* change is done just to satisfy sync state requirements.
|
||||
*/
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>;
|
||||
clock-names = "pll_byte_clk0", "pll_dsi_clk0",
|
||||
"pll_byte_clk1", "pll_dsi_clk1",
|
||||
"mdp_core_clk";
|
||||
vddio-supply = <&L12B>;
|
||||
vci-supply = <&L13B>;
|
||||
vdd-supply = <&L11B>;
|
||||
};
|
||||
|
||||
&sde_dsi1 {
|
||||
clocks = <&mdss_dsi_phy0 0>,
|
||||
<&mdss_dsi_phy0 1>,
|
||||
<&mdss_dsi_phy1 2>,
|
||||
<&mdss_dsi_phy1 3>,
|
||||
/*
|
||||
* Currently the dsi clock handles are under the dsi
|
||||
* controller DT node. As soon as the controller probe
|
||||
* finishes, the dispcc sync state can get called before
|
||||
* the dsi_display probe potentially disturbing the clock
|
||||
* votes for cont_splash use case. Hence we are no longer
|
||||
* protected by the component model in this case against the
|
||||
* disp cc sync state getting triggered after the dsi_ctrl
|
||||
* probe. To protect against this incorrect sync state trigger
|
||||
* add this dummy MDP clk vote handle to the dsi_display
|
||||
* DT node. Since the dsi_display driver does not parse
|
||||
* MDP clock nodes, no actual vote shall be added and this
|
||||
* change is done just to satisfy sync state requirements.
|
||||
*/
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>;
|
||||
clock-names = "pll_byte_clk0", "pll_dsi_clk0",
|
||||
"pll_byte_clk1", "pll_dsi_clk1",
|
||||
"mdp_core_clk";
|
||||
vddio-supply = <&L12B>;
|
||||
vci-supply = <&L13B>;
|
||||
vdd-supply = <&L11B>;
|
||||
};
|
||||
|
||||
&mdss_mdp {
|
||||
connectors = <&smmu_sde_unsec &sde_wb1 &sde_wb2>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_cmd {
|
||||
qcom,ulps-enabled;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <540 40 40 40 1080 40>;
|
||||
};
|
||||
|
||||
timing@1 {
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <540 40 40 40 1080 40>;
|
||||
};
|
||||
|
||||
timing@2 {
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <540 40 40 40 1080 40>;
|
||||
};
|
||||
|
||||
timing@3 {
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <540 40 40 40 1080 40>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_cmd {
|
||||
qcom,ulps-enabled;
|
||||
};
|
||||
|
||||
&dsi_sharp_4k_dsc_cmd {
|
||||
qcom,ulps-enabled;
|
||||
};
|
||||
|
||||
&dsi_sim_cmd {
|
||||
qcom,ulps-enabled;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 { /* WQHD 60FPS cmd vid mode*/
|
||||
qcom,panel-roi-alignment = <720 40 720 40 720 40>;
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
};
|
||||
|
||||
timing@2 { /* FHD 60FPS cmd mode*/
|
||||
qcom,panel-roi-alignment = <540 40 540 40 540 40>;
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
};
|
||||
|
||||
timing@3 { /* HD 60FPS cmd mode*/
|
||||
qcom,panel-roi-alignment = <360 20 360 20 360 20>;
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_375_cmd {
|
||||
qcom,ulps-enabled;
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_10b_cmd {
|
||||
qcom,ulps-enabled;
|
||||
};
|
||||
|
||||
&dsi_dual_sim_cmd {
|
||||
qcom,ulps-enabled;
|
||||
};
|
||||
|
||||
&dsi_dual_sim_dsc_375_cmd {
|
||||
qcom,ulps-enabled;
|
||||
};
|
||||
|
||||
&dsi_sim_sec_hd_cmd {
|
||||
qcom,ulps-enabled;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,panel-roi-alignment = <720 40 720 40 720 40>;
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -86,3 +86,46 @@
|
||||
};
|
||||
};
|
||||
|
||||
&mdss_dsi0 {
|
||||
vdda-1p2-supply = <&L3G>;
|
||||
qcom,split-link-supported;
|
||||
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
|
||||
"pixel_clk", "pixel_clk_rcg", "esc_clk", "xo";
|
||||
};
|
||||
|
||||
&mdss_dsi1 {
|
||||
vdda-1p2-supply = <&L3G>;
|
||||
qcom,split-link-supported;
|
||||
clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK1_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_ESC1_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
|
||||
"pixel_clk", "pixel_clk_rcg", "esc_clk", "xo";
|
||||
};
|
||||
|
||||
&mdss_dsi_phy0 {
|
||||
vdda-0p9-supply = <&L3I>;
|
||||
qcom,panel-allow-phy-poweroff;
|
||||
qcom,dsi-pll-ssc-en;
|
||||
qcom,dsi-pll-ssc-mode = "down-spread";
|
||||
pll_codes_region = <&dsi_pll_codes_data>;
|
||||
|
||||
};
|
||||
|
||||
&mdss_dsi_phy1 {
|
||||
vdda-0p9-supply = <&L3I>;
|
||||
qcom,panel-allow-phy-poweroff;
|
||||
qcom,dsi-pll-ssc-en;
|
||||
qcom,dsi-pll-ssc-mode = "down-spread";
|
||||
};
|
||||
|
||||
Reference in New Issue
Block a user