samsung_sm8750/android_kernel_samsung_sm8750-devicetrees
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ARM: dts: qcom: Add initial Thermal configuration for tuna

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Add thermal devicetree changes and thermal configuration
for tuna based on the recommendation.

Change-Id: I6904fca29794cc8f7615d5f540f613ef903b59aa
Signed-off-by: Nitesh Kumar <quic_nitekuma@quicinc.com>
This commit is contained in:
Nitesh Kumar
2024-09-23 10:29:06 +05:30
parent fc140de718
commit e30408130e
3 changed files with 1790 additions and 0 deletions
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16
qcom/tuna-rumi.dtsi
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@@ -174,3 +174,19 @@
&APSS_OFF { &APSS_OFF {
status = "disabled"; status = "disabled";
}; };
&tsens0 {
status = "disabled";
};
&tsens1 {
status = "disabled";
};
&tsens2 {
status = "disabled";
};
&tsens3 {
status = "disabled";
};

1765
qcom/tuna-thermal.dtsi Normal file
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File diff suppressed because it is too large Load Diff

9
qcom/tuna.dtsi
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@@ -91,6 +91,7 @@
cpu-idle-states = <&GOLD_OFF_CL0 &GOLD_RAIL_OFF_CL0>; cpu-idle-states = <&GOLD_OFF_CL0 &GOLD_RAIL_OFF_CL0>;
power-domains = <&CPU_PD0>; power-domains = <&CPU_PD0>;
power-domain-names = "psci"; power-domain-names = "psci";
#cooling-cells = <2>;
cpu-release-addr = <0x0 0xE3940000>; cpu-release-addr = <0x0 0xE3940000>;
next-level-cache = <&L2_0>; next-level-cache = <&L2_0>;
capacity-dmips-mhz = <1024>; capacity-dmips-mhz = <1024>;
@@ -115,6 +116,7 @@
cpu-idle-states = <&GOLD_OFF_CL0 &GOLD_RAIL_OFF_CL0>; cpu-idle-states = <&GOLD_OFF_CL0 &GOLD_RAIL_OFF_CL0>;
power-domains = <&CPU_PD1>; power-domains = <&CPU_PD1>;
power-domain-names = "psci"; power-domain-names = "psci";
#cooling-cells = <2>;
cpu-release-addr = <0x0 0xE3940000>; cpu-release-addr = <0x0 0xE3940000>;
next-level-cache = <&L2_1>; next-level-cache = <&L2_1>;
capacity-dmips-mhz = <1024>; capacity-dmips-mhz = <1024>;
@@ -135,6 +137,7 @@
cpu-idle-states = <&GOLD_OFF_CL1 &GOLD_RAIL_OFF_CL1>; cpu-idle-states = <&GOLD_OFF_CL1 &GOLD_RAIL_OFF_CL1>;
power-domains = <&CPU_PD2>; power-domains = <&CPU_PD2>;
power-domain-names = "psci"; power-domain-names = "psci";
#cooling-cells = <2>;
cpu-release-addr = <0x0 0xE3940000>; cpu-release-addr = <0x0 0xE3940000>;
next-level-cache = <&L2_2>; next-level-cache = <&L2_2>;
capacity-dmips-mhz = <1321>; capacity-dmips-mhz = <1321>;
@@ -154,6 +157,7 @@
cpu-idle-states = <&GOLD_OFF_CL1 &GOLD_RAIL_OFF_CL1>; cpu-idle-states = <&GOLD_OFF_CL1 &GOLD_RAIL_OFF_CL1>;
power-domains = <&CPU_PD3>; power-domains = <&CPU_PD3>;
power-domain-names = "psci"; power-domain-names = "psci";
#cooling-cells = <2>;
cpu-release-addr = <0x0 0xE3940000>; cpu-release-addr = <0x0 0xE3940000>;
next-level-cache = <&L2_3>; next-level-cache = <&L2_3>;
capacity-dmips-mhz = <1321>; capacity-dmips-mhz = <1321>;
@@ -173,6 +177,7 @@
cpu-idle-states = <&GOLD_OFF_CL1 &GOLD_RAIL_OFF_CL1>; cpu-idle-states = <&GOLD_OFF_CL1 &GOLD_RAIL_OFF_CL1>;
power-domains = <&CPU_PD4>; power-domains = <&CPU_PD4>;
power-domain-names = "psci"; power-domain-names = "psci";
#cooling-cells = <2>;
cpu-release-addr = <0x0 0xE3940000>; cpu-release-addr = <0x0 0xE3940000>;
next-level-cache = <&L2_4>; next-level-cache = <&L2_4>;
capacity-dmips-mhz = <1321>; capacity-dmips-mhz = <1321>;
@@ -192,6 +197,7 @@
cpu-idle-states = <&GOLD_OFF_CL2 &GOLD_RAIL_OFF_CL2>; cpu-idle-states = <&GOLD_OFF_CL2 &GOLD_RAIL_OFF_CL2>;
power-domains = <&CPU_PD5>; power-domains = <&CPU_PD5>;
power-domain-names = "psci"; power-domain-names = "psci";
#cooling-cells = <2>;
cpu-release-addr = <0x0 0xE3940000>; cpu-release-addr = <0x0 0xE3940000>;
next-level-cache = <&L2_5>; next-level-cache = <&L2_5>;
capacity-dmips-mhz = <1321>; capacity-dmips-mhz = <1321>;
@@ -211,6 +217,7 @@
cpu-idle-states = <&GOLD_OFF_CL2 &GOLD_RAIL_OFF_CL2>; cpu-idle-states = <&GOLD_OFF_CL2 &GOLD_RAIL_OFF_CL2>;
power-domains = <&CPU_PD6>; power-domains = <&CPU_PD6>;
power-domain-names = "psci"; power-domain-names = "psci";
#cooling-cells = <2>;
cpu-release-addr = <0x0 0xE3940000>; cpu-release-addr = <0x0 0xE3940000>;
next-level-cache = <&L2_6>; next-level-cache = <&L2_6>;
capacity-dmips-mhz = <1321>; capacity-dmips-mhz = <1321>;
@@ -230,6 +237,7 @@
cpu-idle-states = <&GOLD_PLUS_OFF &GOLD_PLUS_RAIL_OFF>; cpu-idle-states = <&GOLD_PLUS_OFF &GOLD_PLUS_RAIL_OFF>;
power-domains = <&CPU_PD7>; power-domains = <&CPU_PD7>;
power-domain-names = "psci"; power-domain-names = "psci";
#cooling-cells = <2>;
cpu-release-addr = <0x0 0xE3940000>; cpu-release-addr = <0x0 0xE3940000>;
next-level-cache = <&L2_7>; next-level-cache = <&L2_7>;
capacity-dmips-mhz = <1935>; capacity-dmips-mhz = <1935>;
@@ -2177,6 +2185,7 @@
#include "msm-rdbg.dtsi" #include "msm-rdbg.dtsi"
#include "tuna-pmic-overlay.dtsi" #include "tuna-pmic-overlay.dtsi"
#include "tuna-walt.dtsi" #include "tuna-walt.dtsi"
#include "tuna-thermal.dtsi"
&qupv3_se7_2uart { &qupv3_se7_2uart {
status = "ok"; status = "ok";