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Merge "ARM: dts: msm: Remove jtag_mm node on monaco"

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QCTECMDR Service
2024-06-27 10:30:27 -07:00
committed by Gerrit - the friendly Code Review server
parent 870190b56a 85c0e79e7b
commit e29742b7bc
1 changed files with 0 additions and 44 deletions
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44
qcom/monaco.dtsi
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@@ -1592,50 +1592,6 @@
};
jtag_mm0: jtagmm@9040000 {
/* compatible = "qcom,jtagv8-mm"; */
reg = <0x9040000 0x1000>;
reg-names = "etm-base";
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU0>;
};
jtag_mm1: jtagmm@9140000 {
/* compatible = "qcom,jtagv8-mm"; */
reg = <0x9140000 0x1000>;
reg-names = "etm-base";
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU1>;
};
jtag_mm2: jtagmm@9240000 {
/* compatible = "qcom,jtagv8-mm"; */
reg = <0x9240000 0x1000>;
reg-names = "etm-base";
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU2>;
};
jtag_mm3: jtagmm@9340000 {
/* compatible = "qcom,jtagv8-mm"; */
reg = <0x9340000 0x1000>;
reg-names = "etm-base";
clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU3>;
};
dcc: dcc_v2@16FF000 {
compatible = "qcom,dcc-v2";
reg = <0x16FF000 0x1000>,