From c0a6035e47a819e581763724033a65c635618249 Mon Sep 17 00:00:00 2001
From: Jagadeesh Kona <quic_jkona@quicinc.com>
Date: Thu, 1 Feb 2024 18:15:16 +0530
Subject: [PATCH] ARM: dts: msm: Mark GCC clock node as GenPD provider

Mark GCC clock node as GenPD provider and disable the
PCIE GDSC regulator nodes.

Change-Id: I98fc6709592c393259da77443d4b6e580e61a0b8
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
---
 qcom/sun.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi
index 348f9338..12870c75 100644
--- a/qcom/sun.dtsi
+++ b/qcom/sun.dtsi
@@ -1731,6 +1731,7 @@
 			      "ufs_phy_tx_symbol_0_clk",
 			      "usb3_phy_wrapper_gcc_usb30_pipe_clk";
 		#clock-cells = <1>;
+		#power-domain-cells = <1>;
 		#reset-cells = <1>;
 	};
 
@@ -1958,6 +1959,7 @@
 		qcom,no-status-check-on-disable;
 		qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 0>;
 		qcom,support-cfg-gdscr;
+		status = "disabled";
 	};
 
 	gcc_pcie_0_phy_gdsc: qcom,gdsc@16c000 {
@@ -1969,6 +1971,7 @@
 		qcom,no-status-check-on-disable;
 		qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 2>;
 		qcom,support-cfg-gdscr;
+		status = "disabled";
 	};
 
 	gcc_ufs_mem_phy_gdsc: qcom,gdsc@19e000 {