Merge "ARM: dts: msm: correct name of ext_cmb/turing/gcc tpdm on sun"

This commit is contained in:
qctecmdr
2023-12-14 05:36:13 -08:00
committed by Gerrit - the friendly Code Review server

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@@ -539,7 +539,7 @@
reg = <0x10980000 0x1000>; reg = <0x10980000 0x1000>;
reg-names = "tpdm-base"; reg-names = "tpdm-base";
coresight-name = "coresight-tpdm-turing_dsb"; coresight-name = "coresight-tpdm-turing";
clocks = <&aoss_qmp>; clocks = <&aoss_qmp>;
clock-names = "apb_pclk"; clock-names = "apb_pclk";
@@ -555,7 +555,7 @@
}; };
tpdm_turing_llm: tpdm@10981000 { tpdm_turing_llm: tpdm@10981000 {
compatible = "arm,coresight-dummy-source"; compatible = "qcom,coresight-static-tpdm";
coresight-name = "coresight-tpdm-turing-llm"; coresight-name = "coresight-tpdm-turing-llm";
out-ports { out-ports {
@@ -569,7 +569,7 @@
}; };
tpdm_turing_llm2: tpdm@10982000 { tpdm_turing_llm2: tpdm@10982000 {
compatible = "arm,coresight-dummy-source"; compatible = "qcom,coresight-static-tpdm";
coresight-name = "coresight-tpdm-turing-llm2"; coresight-name = "coresight-tpdm-turing-llm2";
out-ports { out-ports {
@@ -1143,7 +1143,7 @@
reg = <0x10cc0000 0x1000>; reg = <0x10cc0000 0x1000>;
reg-names = "tpdm-base"; reg-names = "tpdm-base";
coresight-name = "coresight-tpdm-tmess-rvss"; coresight-name = "coresight-tpdm-tmess-0";
clocks = <&aoss_qmp>; clocks = <&aoss_qmp>;
clock-names = "apb_pclk"; clock-names = "apb_pclk";
@@ -1167,7 +1167,7 @@
reg = <0x10cc1000 0x1000>; reg = <0x10cc1000 0x1000>;
reg-names = "tpdm-base"; reg-names = "tpdm-base";
coresight-name = "coresight-tpdm-tmess-dl"; coresight-name = "coresight-tpdm-tmess-1";
clocks = <&aoss_qmp>; clocks = <&aoss_qmp>;
clock-names = "apb_pclk"; clock-names = "apb_pclk";
@@ -1819,7 +1819,7 @@
reg = <0x12183000 0x1000>; reg = <0x12183000 0x1000>;
reg-names = "tpdm-base"; reg-names = "tpdm-base";
coresight-name = "coresight-tpdm-ext-cmb1"; coresight-name = "coresight-tpdm-ext_cmb1";
clocks = <&aoss_qmp>; clocks = <&aoss_qmp>;
clock-names = "apb_pclk"; clock-names = "apb_pclk";
@@ -1840,7 +1840,7 @@
reg = <0x12185000 0x1000>; reg = <0x12185000 0x1000>;
reg-names = "tpdm-base"; reg-names = "tpdm-base";
coresight-name = "coresight-tpdm-ext-cmb2"; coresight-name = "coresight-tpdm-ext_cmb2";
clocks = <&aoss_qmp>; clocks = <&aoss_qmp>;
clock-names = "apb_pclk"; clock-names = "apb_pclk";
@@ -1861,7 +1861,7 @@
reg = <0x12187000 0x1000>; reg = <0x12187000 0x1000>;
reg-names = "tpdm-base"; reg-names = "tpdm-base";
coresight-name = "coresight-tpdm-ext-cmb3"; coresight-name = "coresight-tpdm-ext_cmb3";
clocks = <&aoss_qmp>; clocks = <&aoss_qmp>;
clock-names = "apb_pclk"; clock-names = "apb_pclk";
@@ -2797,7 +2797,7 @@
}; };
}; };
replicator_uc0: replicator@134a0000 { replicator_uc0: replicator@1340a000 {
compatible = "arm,primecell"; compatible = "arm,primecell";
arm,primecell-periphid = <0x000bb909>; arm,primecell-periphid = <0x000bb909>;
reg = <0x1340a000 0x1000>; reg = <0x1340a000 0x1000>;
@@ -3218,7 +3218,6 @@
qcom,replicator-loses-context; qcom,replicator-loses-context;
clocks = <&aoss_qmp>; clocks = <&aoss_qmp>;
clock-names = "apb_pclk"; clock-names = "apb_pclk";
status = "disabled";
in-ports { in-ports {
port { port {
@@ -3414,9 +3413,9 @@
out-ports { out-ports {
port { port {
tpdm_ddr_shrm_out_tn_ddr: endpoint { tpdm_ddr_llcc0_out_tn_ddr: endpoint {
remote-endpoint = remote-endpoint =
<&tn_ddr_in_tpdm_ddr_shrm>; <&tn_ddr_in_tpdm_ddr_llcc0>;
}; };
}; };
}; };
@@ -3435,9 +3434,9 @@
out-ports { out-ports {
port { port {
tpdm_ddr_dpm_out_tn_ddr: endpoint { tpdm_ddr_llcc1_out_tn_ddr: endpoint {
remote-endpoint = remote-endpoint =
<&tn_ddr_in_tpdm_ddr_dpm>; <&tn_ddr_in_tpdm_ddr_llcc1>;
}; };
}; };
}; };
@@ -3485,6 +3484,48 @@
}; };
}; };
tpdm_ddr_dpm: tpdm@10d04000 {
compatible = "arm,primecell";
arm,primecell-periphid = <0x000bb968>;
reg = <0x10d04000 0x1000>;
reg-names = "tpdm-base";
coresight-name = "coresight-tpdm-ddr-dpm";
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
out-ports {
port {
tpdm_ddr_dpm_out_tn_ddr: endpoint {
remote-endpoint =
<&tn_ddr_in_tpdm_ddr_dpm>;
};
};
};
};
tpdm_ddr_shrm: tpdm@10d03000 {
compatible = "arm,primecell";
arm,primecell-periphid = <0x000bb968>;
reg = <0x10d03000 0x1000>;
reg-names = "tpdm-base";
coresight-name = "coresight-tpdm-ddr-shrm";
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
out-ports {
port {
tpdm_ddr_shrm_out_tn_ddr: endpoint {
remote-endpoint =
<&tn_ddr_in_tpdm_ddr_shrm>;
};
};
};
};
tpdm_ddr_ch02: tpdm@10d06000 { tpdm_ddr_ch02: tpdm@10d06000 {
compatible = "arm,primecell"; compatible = "arm,primecell";
arm,primecell-periphid = <0x000bb968>; arm,primecell-periphid = <0x000bb968>;
@@ -3574,17 +3615,17 @@
port@9 { port@9 {
reg = <9>; reg = <9>;
tn_ddr_in_tpdm_ddr_shrm: endpoint { tn_ddr_in_tpdm_ddr_llcc0: endpoint {
remote-endpoint = remote-endpoint =
<&tpdm_ddr_shrm_out_tn_ddr>; <&tpdm_ddr_llcc0_out_tn_ddr>;
}; };
}; };
port@a { port@a {
reg = <10>; reg = <10>;
tn_ddr_in_tpdm_ddr_dpm: endpoint { tn_ddr_in_tpdm_ddr_llcc1: endpoint {
remote-endpoint = remote-endpoint =
<&tpdm_ddr_dpm_out_tn_ddr>; <&tpdm_ddr_llcc1_out_tn_ddr>;
}; };
}; };
@@ -3604,6 +3645,22 @@
}; };
}; };
port@d {
reg = <13>;
tn_ddr_in_tpdm_ddr_dpm: endpoint {
remote-endpoint =
<&tpdm_ddr_dpm_out_tn_ddr>;
};
};
port@e {
reg = <14>;
tn_ddr_in_tpdm_ddr_shrm: endpoint {
remote-endpoint =
<&tpdm_ddr_shrm_out_tn_ddr>;
};
};
port@f { port@f {
reg = <15>; reg = <15>;
tn_ddr_in_tpdm_ddr_ch02: endpoint { tn_ddr_in_tpdm_ddr_ch02: endpoint {
@@ -4059,7 +4116,7 @@
reg = <0x1082c000 0x1000>; reg = <0x1082c000 0x1000>;
reg-names = "tpdm-base"; reg-names = "tpdm-base";
coresight-name = "coresight-tpdm-qdss"; coresight-name = "coresight-tpdm-gcc";
clocks = <&aoss_qmp>; clocks = <&aoss_qmp>;
clock-names = "apb_pclk"; clock-names = "apb_pclk";