samsung_sm8750/android_kernel_samsung_sm8750-devicetrees
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ARM: dts: msm: add display dt node for Tuna target

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This patch adds display device tree support for Tuna target.

Change-Id: Ife1ab80dcb78fc7654805ab5bedec76bdd33039d
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
This commit is contained in:
Akash Gajjar
2024-09-24 13:04:15 +05:30
committed by Abhinav Saurabh
parent a0472afd5f
commit e1e3bcbdde
3 changed files with 482 additions and 0 deletions
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81
display/tuna-sde.dtsi
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@@ -5,8 +5,10 @@
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
#include <dt-bindings/clock/qcom,dispcc-tuna.h>
#include <dt-bindings/clock/qcom,gcc-tuna.h>
#include <dt-bindings/interconnect/qcom,tuna.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,tcsrcc-sun.h>
#include <dt-bindings/arm/msm/qti-smmu-proxy-dt-ids.h>
#include "tuna-sde-common.dtsi"
&soc {
@@ -175,10 +177,89 @@
qcom,supply-disable-load = <0>;
};
};
};
smmu_sde_iommu_region_partition: smmu_sde_iommu_region_partition {
iommu-addresses = <&smmu_sde_unsec 0x0 0x00060000>,
<&smmu_sde_sec 0x0 0x00020000>;
};
smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
compatible = "qcom,smmu_sde_unsec";
iommus = <&apps_smmu 0x800 0x2>;
memory-region = <&smmu_sde_iommu_region_partition>;
qcom,iommu-faults = "non-fatal";
qcom,iommu-earlymap; /* for cont-splash */
dma-coherent;
clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
clock-names = "mdp_core_clk";
};
smmu_sde_sec: qcom,smmu_sde_sec_cb {
compatible = "qcom,smmu_sde_sec";
iommus = <&apps_smmu 0x801 0x0>;
memory-region = <&smmu_sde_iommu_region_partition>;
qcom,iommu-faults = "non-fatal";
qcom,iommu-vmid = <0xa>;
clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
clock-names = "mdp_core_clk";
};
};
&mdss_mdp {
clocks =
<&gcc GCC_DISP_HF_AXI_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK_SRC>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>,
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>;
clock-names = "gcc_bus",
"iface_clk", "branch_clk", "core_clk", "vsync_clk",
"lut_clk";
clock-rate = <0 0 660000000 660000000 19200000 660000000>;
clock-max-rate = <0 0 660000000 660000000 19200000 660000000>;
clock-mmrm = <0 0 0 DISP_CC_MDSS_MDP_CLK_SRC 0 0>;
qcom,hw-fence-sw-version = <0x1>;
power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
mmcx-supply = <&VDD_MMCX_LEVEL>;
qti,smmu-proxy-cb-id = <QTI_SMMU_PROXY_DISPLAY_CB>;
qcom,sde-vm-exclude-reg-names = "ipcc_reg";
/* data and reg bus scale settings */
interconnects = <&mmss_noc MASTER_MDP &gem_noc SLAVE_LLCC>,
<&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC
&config_noc SLAVE_DISPLAY_CFG>;
interconnect-names = "qcom,sde-data-bus0",
"qcom,sde-ebi-bus", "qcom,sde-reg-bus";
qcom,sde-has-idle-pc;
qcom,sde-ib-bw-vote = <2500000 0 800000>;
qcom,sde-dspp-ltm-version = <0x00010003>;
/* offsets are based off dspp 0, 1, 2, and 3 */
qcom,sde-dspp-ltm-off = <0x15300 0x14300 0x13300>;
qcom,platform-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,platform-supply-entry@0 {
reg = <0>;
qcom,supply-name = "mmcx";
qcom,supply-min-voltage = <0>;
qcom,supply-max-voltage = <0>;
qcom,supply-enable-load = <0>;
qcom,supply-disable-load = <0>;
};
};
};
&mdss_dsi0 {