Merge "ARM: dts: msm: Add PCIe Root port configuration for sun"
This commit is contained in:
qctecmdr
committed by
Gerrit - the friendly Code Review server
Gerrit - the friendly Code Review server
commit
e0e504a5cc
174
qcom/sun-pcie.dtsi
Normal file
174
qcom/sun-pcie.dtsi
Normal file
@@ -0,0 +1,174 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/qcom,gcc-sun.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
&soc {
|
||||
pcie0: qcom,pcie@1c00000 {
|
||||
compatible = "qcom,pci-msm";
|
||||
|
||||
reg = <0x01c00000 0x3000>,
|
||||
<0x01c06000 0x2000>,
|
||||
<0x40000000 0xf1d>,
|
||||
<0x40000f20 0xa8>,
|
||||
<0x40001000 0x1000>,
|
||||
<0x40100000 0x100000>;
|
||||
reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";
|
||||
|
||||
cell-index = <0>;
|
||||
linux,pci-domain = <0>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>,
|
||||
<0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>;
|
||||
|
||||
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
|
||||
"int_d";
|
||||
|
||||
msi-map = <0x0 &gic_its 0x1400 0x1>,
|
||||
<0x100 &gic_its 0x1401 0x1>; /* 32 event IDs */
|
||||
|
||||
perst-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>;
|
||||
wake-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&pcie0_perst_default
|
||||
&pcie0_clkreq_default
|
||||
&pcie0_wake_default>;
|
||||
pinctrl-1 = <&pcie0_perst_default
|
||||
&pcie0_clkreq_sleep
|
||||
&pcie0_wake_default>;
|
||||
|
||||
gdsc-core-vdd-supply = <&gcc_pcie_0_gdsc>;
|
||||
vreg-1p2-supply = <&pm_v8g_l3>;
|
||||
vreg-0p9-supply = <&pm_v6f_l1>;
|
||||
vreg-cx-supply = <&VDD_CX_LEVEL>;
|
||||
vreg-mx-supply = <&VDD_MXA_LEVEL>;
|
||||
qcom,vreg-1p2-voltage-level = <1200000 1200000 18200>;
|
||||
qcom,vreg-0p9-voltage-level = <912000 880000 80900>;
|
||||
qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
|
||||
RPMH_REGULATOR_LEVEL_NOM 0>;
|
||||
qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
|
||||
RPMH_REGULATOR_LEVEL_NOM 0>;
|
||||
qcom,bw-scale = /* Gen1 */
|
||||
<RPMH_REGULATOR_LEVEL_LOW_SVS
|
||||
RPMH_REGULATOR_LEVEL_LOW_SVS
|
||||
19200000
|
||||
/* Gen2 */
|
||||
RPMH_REGULATOR_LEVEL_LOW_SVS
|
||||
RPMH_REGULATOR_LEVEL_LOW_SVS
|
||||
19200000
|
||||
/* Gen3 */
|
||||
RPMH_REGULATOR_LEVEL_NOM
|
||||
RPMH_REGULATOR_LEVEL_NOM
|
||||
100000000>;
|
||||
|
||||
interconnect-names = "icc_path";
|
||||
interconnects = <&pcie_noc MASTER_PCIE_3 &mc_virt SLAVE_EBI1>;
|
||||
|
||||
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_PCIE_0_AUX_CLK>,
|
||||
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
|
||||
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
|
||||
<&tcsrcc TCSR_PCIE_0_CLKREF_EN>,
|
||||
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
|
||||
<&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
|
||||
<&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
|
||||
<&gcc GCC_CNOC_PCIE_SF_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
|
||||
<&pcie_0_pipe_clk>;
|
||||
clock-names = "pcie_pipe_clk", "pcie_ref_clk_src",
|
||||
"pcie_aux_clk", "pcie_cfg_ahb_clk",
|
||||
"pcie_mstr_axi_clk", "pcie_slv_axi_clk",
|
||||
"pcie_clkref_en", "pcie_slv_q2a_axi_clk",
|
||||
"pcie_rate_change_clk",
|
||||
"gcc_ddrss_pcie_sf_qtb_clk",
|
||||
"pcie_aggre_noc_axi_clk",
|
||||
"gcc_cnoc_pcie_sf_axi_clk", "pcie_pipe_clk_mux",
|
||||
"pcie_pipe_clk_ext_src";
|
||||
qcom,pcie-clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>, <0>, <0>,
|
||||
<100000000>, <0>, <0>, <0>, <0>, <0>;
|
||||
clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>,
|
||||
<0>, <0>, <0>, <1>, <0>, <0>;
|
||||
|
||||
resets = <&gcc GCC_PCIE_0_BCR>,
|
||||
<&gcc GCC_PCIE_0_PHY_BCR>;
|
||||
reset-names = "pcie_0_core_reset",
|
||||
"pcie_0_phy_reset";
|
||||
|
||||
dma-coherent;
|
||||
qcom,smmu-sid-base = <0x1400>;
|
||||
iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
|
||||
<0x100 &apps_smmu 0x1401 0x1>;
|
||||
|
||||
qcom,boot-option = <0x1>;
|
||||
qcom,aux-clk-freq = <20>; /* 19.2 MHz */
|
||||
qcom,drv-name = "lpass";
|
||||
qcom,drv-l1ss-timeout-us = <5000>;
|
||||
qcom,l1-2-th-scale = <2>;
|
||||
qcom,l1-2-th-value = <150>;
|
||||
qcom,slv-addr-space-size = <0x4000000>;
|
||||
qcom,ep-latency = <10>;
|
||||
qcom,num-parf-testbus-sel = <0xb9>;
|
||||
|
||||
qcom,phy-status-offset = <0x414>;
|
||||
qcom,phy-status-bit = <6>;
|
||||
qcom,phy-power-down-offset = <0x440>;
|
||||
|
||||
pcie0_rp: pcie0_rp {
|
||||
reg = <0 0 0 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie0_msi: qcom,pcie0_msi@16110040 {
|
||||
compatible = "qcom,pci-msi";
|
||||
msi-controller;
|
||||
reg = <0x17110040 0x0>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
@@ -281,6 +281,60 @@
|
||||
};
|
||||
};
|
||||
|
||||
pcie0 {
|
||||
pcie0_perst_default: pcie0_perst_default {
|
||||
mux {
|
||||
pins = "gpio102";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio102";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
pcie0_clkreq_default: pcie0_clkreq_default {
|
||||
mux {
|
||||
pins = "gpio103";
|
||||
function = "pcie0_clk_req_n";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio103";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pcie0_wake_default: pcie0_wake_default {
|
||||
mux {
|
||||
pins = "gpio104";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio104";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pcie0_clkreq_sleep: pcie0_clkreq_sleep {
|
||||
mux {
|
||||
pins = "gpio103";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio103";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sdc2_on: sdc2_on {
|
||||
clk {
|
||||
pins = "sdc2_clk";
|
||||
|
||||
@@ -62,6 +62,30 @@
|
||||
0x0 0x3c
|
||||
0x0 0x4>;
|
||||
};
|
||||
|
||||
pcie0: qcom,pcie@1c00000 {
|
||||
reg = <0x01c00000 0x3000>,
|
||||
<0x01c06000 0x2000>,
|
||||
<0x40000000 0xf1d>,
|
||||
<0x40000f20 0xa8>,
|
||||
<0x40001000 0x1000>,
|
||||
<0x40100000 0x100000>,
|
||||
<0x01c05000 0x1000>;
|
||||
reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf",
|
||||
"rumi";
|
||||
linux,pci-domain = <0>;
|
||||
qcom,target-link-speed = <0x1>;
|
||||
qcom,link-check-max-count = <200>; /* 1 sec */
|
||||
qcom,no-l0s-supported;
|
||||
qcom,no-l1-supported;
|
||||
qcom,no-l1ss-supported;
|
||||
qcom,no-aux-clk-sync;
|
||||
/*
|
||||
* Comment out ICC and SMMU properties in main PCIe node
|
||||
* if any issue in PCIe probe in RUMI
|
||||
*/
|
||||
status = "ok";
|
||||
};
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
|
||||
@@ -33,7 +33,7 @@
|
||||
|
||||
|
||||
chosen: chosen {
|
||||
bootargs = "nokaslr kpti=0 log_buf_len=256K swiotlb=0 loop.max_part=7";
|
||||
bootargs = "nokaslr kpti=0 log_buf_len=256K swiotlb=0 loop.max_part=7 pcie_ports=compat";
|
||||
stdout-path = "/soc/qcom,qupv3_1_geni_se@ac0000/qcom,qup_uart@a9c000:115200n8";
|
||||
};
|
||||
|
||||
@@ -377,11 +377,21 @@
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
ranges;
|
||||
#redistributor-regions = <1>;
|
||||
redistributor-stride = <0x0 0x40000>;
|
||||
reg = <0x16000000 0x10000>, /* GICD */
|
||||
<0x16080000 0x200000>; /* GICR * 8 */
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
gic_its: msi-controller@0x16040000 {
|
||||
compatible = "arm,gic-v3-its";
|
||||
msi-controller;
|
||||
#msi-cells = <1>;
|
||||
reg = <0x16040000 0x20000>;
|
||||
};
|
||||
};
|
||||
|
||||
memtimer: timer@16800000 {
|
||||
@@ -2022,6 +2032,7 @@
|
||||
#include "sun-qupv3.dtsi"
|
||||
#include "sun-usb.dtsi"
|
||||
#include "sun-thermal.dtsi"
|
||||
#include "sun-pcie.dtsi"
|
||||
|
||||
&qupv3_se7_2uart {
|
||||
status = "ok";
|
||||
|
||||
Reference in New Issue
Block a user