diff --git a/Kbuild b/Kbuild new file mode 100644 index 00000000..c6b9be42 --- /dev/null +++ b/Kbuild @@ -0,0 +1,18 @@ +# Use current $(MSM_ARCH) to set config/ makefile path +SYNX_TARGET_MKFILE_PATH := $(SYNX_DEVICETREE_ROOT)/config/$(MSM_ARCH).mk +# Check to see if current target makefile exists +SYNX_TARGET_EXISTS := $(or $(and $(wildcard $(SYNX_TARGET_MKFILE_PATH)),y),n) + +# Since Kernel SI can support multiple ARCH's this allows only the current selected target ARCH +# to compile. +ifeq ($(SYNX_TARGET_EXISTS), y) +include $(SYNX_TARGET_MKFILE_PATH) +else +# Print a warning but do not throw an error to allow bring-up of new targets! +$(warning [$(MODNAME)] $(MSM_ARCH) is not a valid target, make sure config\ folder contains a makefile named $(MSM_ARCH).mk) +$(warning [$(MODNAME)] driver is NOT being enabled!) +endif + +always-y := $(dtbo-y) $(dtb-y) +subdir-y := $(dts-dirs) +clean-files := *.dtb *.dtbo diff --git a/Makefile b/Makefile new file mode 100644 index 00000000..37f193f9 --- /dev/null +++ b/Makefile @@ -0,0 +1,20 @@ + +SYNX_DEVICETREE_ROOT=$(KERNEL_SRC)/$(M) +SYNX_KERNEL_ROOT=$(SYNX_DEVICETREE_ROOT)/../../opensource/synx-kernel + +KBUILD_OPTIONS += SYNX_DEVICETREE_ROOT=$(KERNEL_SRC)/$(M) +KBUILD_OPTIONS += KBUILD_DTC_INCLUDE=$(SYNX_KERNEL_ROOT) +KBUILD_OPTIONS += KBUILD_EXTMOD_DTS=. +KBUILD_OPTIONS += KERNEL_ROOT=$(ROOT_DIR)/$(KERNEL_DIR) +KBUILD_OPTIONS += MODNAME=synx-devicetree + +all: dtbs + +dtbs: + $(MAKE) -C $(KERNEL_SRC) M=$(M) dtbs $(KBUILD_OPTIONS) + +modules_install: + $(MAKE) M=$(M) -C $(KERNEL_SRC) modules_install + +clean: + $(MAKE) -C $(KERNEL_SRC) M=$(M) clean diff --git a/bindings/qcom,ipclite.txt b/bindings/qcom,ipclite.txt new file mode 100644 index 00000000..07d37f22 --- /dev/null +++ b/bindings/qcom,ipclite.txt @@ -0,0 +1,86 @@ +Qualcomm Technologies, Inc. IPCLite Framework + +This binding describes IPCLite protocol within the system. +IPCLite is a light weight mechanism for communication between +subsystem-pairs. This protocol will be primarily used to +support low-latency signalling for Global Synx framework. + +- compatible : + Usage: required + Value type: + Definition: must be "qcom,ipclite" + +- label: + Usage: optional + Value type: + Definition: should specify the subsystem name this edge corresponds to. + +- global_atomic: + Usage: required + Value type: + Definition: this property specifies if the core supports global atomic operations + 1 if cores supports, 0 if core doesn't support global atomic operations + +- interrupts: + Usage: required + Value type: + Definition: should specify the IRQ used by the remote processor to + signal this processor about communication related events + +- qcom,remote-pid: + Usage: required for ipcmem + Value type: + Definition: specifies the identifier of the remote endpoint of this edge + +- mboxes: + Usage: required + Value type: + Definition: reference to the "rpm_hlos" mailbox in APCS, as described + in mailbox/mailbox.txt + += EXAMPLE +The following example represents the IPCLite node along with cdsp sub-node. + +ipclite { + compatible = "qcom,ipclite"; + memory-region = <&global_sync_mem>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ipclite_cdsp: cdsp { + qcom,remote-pid = <5>; + label = "cdsp"; + global_atomic = <0>; + + ipclite_signal_0 { + index = <0>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_1 { + index = <1>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_2 { + index = <2>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + }; +}; diff --git a/config/pineapple.mk b/config/pineapple.mk new file mode 100644 index 00000000..8cfc7dec --- /dev/null +++ b/config/pineapple.mk @@ -0,0 +1,4 @@ +dtbo-y := synx/pineapple-synx.dtbo +dtbo-y += pineapple-synx-atp.dtbo +dtbo-y += pineapple-synx-mtp.dtbo + diff --git a/config/sun.mk b/config/sun.mk new file mode 100644 index 00000000..6b319c3d --- /dev/null +++ b/config/sun.mk @@ -0,0 +1,4 @@ +dtbo-y := synx/sun-synx.dtbo +#dtbo-y += sun-synx-cdp.dtbo +#dtbo-y += sun-synx-mtp.dtbo +#dtbo-y += sun-synx-qrd.dtbo diff --git a/pineapple-synx-atp.dts b/pineapple-synx-atp.dts new file mode 100644 index 00000000..c73d090a --- /dev/null +++ b/pineapple-synx-atp.dts @@ -0,0 +1,15 @@ +Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. +SPDX-License-Identifier: BSD-3-Clause +/dts-v1/; +/plugin/; + +#include +#include +#include "synx/pineapple-synx.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Pineapple"; + compatible = "qcom,pineapple"; + qcom,msm-id = <557 0x10000>; + qcom,board-id = <0 0>; +}; diff --git a/pineapple-synx-common.dtsi b/pineapple-synx-common.dtsi new file mode 100644 index 00000000..028eeb42 --- /dev/null +++ b/pineapple-synx-common.dtsi @@ -0,0 +1,11 @@ +Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. +SPDX-License-Identifier: BSD-3-Clause +//&soc { +// st54spi_gpio { +// status = "ok"; +// compatible = "st,st54spi_gpio"; +// /* gpio used as SE_nRESET */ +// gpio-power_nreset = <&tlmm 12 0x00>; +// }; +//}; + diff --git a/pineapple-synx-mtp.dts b/pineapple-synx-mtp.dts new file mode 100644 index 00000000..63207d43 --- /dev/null +++ b/pineapple-synx-mtp.dts @@ -0,0 +1,13 @@ +Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. +SPDX-License-Identifier: BSD-3-Clause +/dts-v1/; +/plugin/; + +#include "pineapple-synx-common.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lanai MTP"; + compatible = "qcom,lanai-mtp", "qcom,lanai", "qcom,mtp"; + qcom,msm-id = <519 0x10000>, <536 0x10000>; + qcom,board-id = <0x10008 0>; +}; diff --git a/sun-synx-cdp.dts b/sun-synx-cdp.dts new file mode 100644 index 00000000..5db529d2 --- /dev/null +++ b/sun-synx-cdp.dts @@ -0,0 +1,15 @@ +Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. +SPDX-License-Identifier: BSD-3-Clause +// /dts-v1/; +// /plugin/; +// +// #include +// #include +// #include "synx/sun-synx.dtsi" +// +// / { +// model = "Qualcomm Technologies, Inc. Sun CDP"; +// compatible = "qcom,sun-cdp", "qcom,sun", "qcom,cdp"; +// qcom,msm-id = <618 0x10000>; +// qcom,board-id = <1 0>; +// }; \ No newline at end of file diff --git a/sun-synx-common.dtsi b/sun-synx-common.dtsi new file mode 100644 index 00000000..028eeb42 --- /dev/null +++ b/sun-synx-common.dtsi @@ -0,0 +1,11 @@ +Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. +SPDX-License-Identifier: BSD-3-Clause +//&soc { +// st54spi_gpio { +// status = "ok"; +// compatible = "st,st54spi_gpio"; +// /* gpio used as SE_nRESET */ +// gpio-power_nreset = <&tlmm 12 0x00>; +// }; +//}; + diff --git a/sun-synx-mtp.dts b/sun-synx-mtp.dts new file mode 100644 index 00000000..1402f98f --- /dev/null +++ b/sun-synx-mtp.dts @@ -0,0 +1,15 @@ +Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. +SPDX-License-Identifier: BSD-3-Clause +// /dts-v1/; +// /plugin/; +// +// #include +// #include +// #include "sun-synx-common.dtsi" +// +// / { +// model = "Qualcomm Technologies, Inc. Sun MTP"; +// compatible = "qcom,sun-mtp", "qcom,sun", "qcom,mtp"; +// qcom,msm-id = <618 0x10000>; +// qcom,board-id = <8 0>; +// }; \ No newline at end of file diff --git a/sun-synx-qrd.dts b/sun-synx-qrd.dts new file mode 100644 index 00000000..3b53a08e --- /dev/null +++ b/sun-synx-qrd.dts @@ -0,0 +1,13 @@ +Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. +SPDX-License-Identifier: BSD-3-Clause +// /dts-v1/; +// /plugin/; +// +// #include "sun-synx-common.dtsi" +// +// / { +// model = "Qualcomm Technologies, Inc. Sun QRD"; +// compatible = "qcom,sun-qrd", "qcom,sun", "qcom,qrd"; +// qcom,msm-id = <618 0x10000>; +// qcom,board-id = <11 0>; +// }; \ No newline at end of file diff --git a/synx/pineapple-synx.dts b/synx/pineapple-synx.dts new file mode 100644 index 00000000..346aac34 --- /dev/null +++ b/synx/pineapple-synx.dts @@ -0,0 +1,15 @@ +Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. +SPDX-License-Identifier: BSD-3-Clause +/dts-v1/; +/plugin/; + +#include +#include +#include "pineapple-synx.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Pineapple"; + compatible = "qcom,pineapple"; + qcom,msm-id = <557 0x10000>, <557 0x20000>, <577 0x10000>, <577 0x20000>; + qcom,board-id = <0 0>; +}; diff --git a/synx/pineapple-synx.dtsi b/synx/pineapple-synx.dtsi new file mode 100644 index 00000000..c0aec61a --- /dev/null +++ b/synx/pineapple-synx.dtsi @@ -0,0 +1,291 @@ +Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. +SPDX-License-Identifier: BSD-3-Clause +#include + +&soc { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + ipcc_compute_l0: qcom,ipcc_compute_l0@443000 { + compatible = "qcom,ipcc"; + reg = <0x443000 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + ipclite { + compatible = "qcom,ipclite"; + memory-region = <&global_sync_mem>; + hwlocks = <&tcsr_mutex 11>; + #address-cells = <1>; + #size-cells = <1>; + major_version = <1>; + minor_version = <0>; + feature_mask_low = <0x0003>; + feature_mask_high = <0x0000>; + ranges; + + ipclite_apss: apss { + qcom,remote-pid = <0>; + label = "apss"; + + ipclite_signal_0 { + index = <0>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_APSS + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_1 { + index = <1>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_BROADCAST + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_2 { + index = <2>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_APSS + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_3 { + index = <3>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_APSS + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_4 { + index = <4>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_APSS + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_SSR>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_5 { + index = <5>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_APSS + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_DEBUG>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + }; + + ipclite_cdsp: cdsp { + qcom,remote-pid = <5>; + label = "cdsp"; + + ipclite_signal_0 { + index = <0>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_1 { + index = <1>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_2 { + index = <2>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_3 { + index = <3>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_4 { + index = <4>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_SSR>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_5 { + index = <5>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_DEBUG>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + }; + + ipclite_cvp: cvp { + qcom,remote-pid = <6>; + label = "cvp"; + + ipclite_signal_0 { + index = <0>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CVP + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_1 { + index = <1>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CVP + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_2 { + index = <2>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CVP + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_3 { + index = <3>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CVP + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_4 { + index = <4>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CVP + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_SSR>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_5 { + index = <5>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CVP + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_DEBUG>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + }; + + ipclite_cam: cam { + qcom,remote-pid = <7>; + label = "cam"; + + ipclite_signal_0 { + index = <0>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CAM + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_1 { + index = <1>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CAM + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_2 { + index = <2>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CAM + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_3 { + index = <3>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CAM + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_4 { + index = <4>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CAM + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_SSR>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_5 { + index = <5>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CAM + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_DEBUG>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + }; + }; + +}; diff --git a/synx/sun-synx.dts b/synx/sun-synx.dts new file mode 100644 index 00000000..2a93da13 --- /dev/null +++ b/synx/sun-synx.dts @@ -0,0 +1,15 @@ +Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. +SPDX-License-Identifier: BSD-3-Clause +/dts-v1/; +/plugin/; + +#include +#include +#include "sun-synx.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun SoC"; + compatible = "qcom,sun"; + qcom,msm-id = <618 0x10000>; + qcom,board-id = <0 0>; +}; \ No newline at end of file diff --git a/synx/sun-synx.dtsi b/synx/sun-synx.dtsi new file mode 100644 index 00000000..c0aec61a --- /dev/null +++ b/synx/sun-synx.dtsi @@ -0,0 +1,291 @@ +Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. +SPDX-License-Identifier: BSD-3-Clause +#include + +&soc { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + ipcc_compute_l0: qcom,ipcc_compute_l0@443000 { + compatible = "qcom,ipcc"; + reg = <0x443000 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + ipclite { + compatible = "qcom,ipclite"; + memory-region = <&global_sync_mem>; + hwlocks = <&tcsr_mutex 11>; + #address-cells = <1>; + #size-cells = <1>; + major_version = <1>; + minor_version = <0>; + feature_mask_low = <0x0003>; + feature_mask_high = <0x0000>; + ranges; + + ipclite_apss: apss { + qcom,remote-pid = <0>; + label = "apss"; + + ipclite_signal_0 { + index = <0>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_APSS + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_1 { + index = <1>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_BROADCAST + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_2 { + index = <2>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_APSS + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_3 { + index = <3>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_APSS + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_4 { + index = <4>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_APSS + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_SSR>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_5 { + index = <5>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_APSS + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_DEBUG>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + }; + + ipclite_cdsp: cdsp { + qcom,remote-pid = <5>; + label = "cdsp"; + + ipclite_signal_0 { + index = <0>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_1 { + index = <1>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_2 { + index = <2>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_3 { + index = <3>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_4 { + index = <4>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_SSR>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_5 { + index = <5>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_DEBUG>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + }; + + ipclite_cvp: cvp { + qcom,remote-pid = <6>; + label = "cvp"; + + ipclite_signal_0 { + index = <0>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CVP + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_1 { + index = <1>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CVP + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_2 { + index = <2>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CVP + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_3 { + index = <3>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CVP + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_4 { + index = <4>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CVP + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_SSR>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_5 { + index = <5>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CVP + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_DEBUG>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + }; + + ipclite_cam: cam { + qcom,remote-pid = <7>; + label = "cam"; + + ipclite_signal_0 { + index = <0>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CAM + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_1 { + index = <1>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CAM + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_2 { + index = <2>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CAM + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_3 { + index = <3>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CAM + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_4 { + index = <4>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CAM + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_SSR>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_5 { + index = <5>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CAM + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_DEBUG>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + }; + }; + +};