samsung_sm8750/android_kernel_samsung_sm8750-devicetrees
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

ARM: dts: msm: Add USB device nodes for sun

Browse Source 
Enable USB related properties for USB functionality on sun.

Change-Id: Ibb522859494c0e939b46a6b790448fc2e62bd37e
Signed-off-by: Ronak Vijay Raheja <quic_rraheja@quicinc.com>
This commit is contained in:
Ronak Vijay Raheja
2023-06-01 15:22:45 -07:00
parent 86f0caef7c
commit de8649c8e1
3 changed files with 88 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

28
qcom/sun-rumi.dtsi
View File

@@ -21,3 +21,31 @@
&qupv3_se7_2uart {
qcom,rumi_platform;
};
&soc {
usb_nop_phy: usb_nop_phy {
compatible = "usb-nop-xceiv";
};
usb_emuphy: phy@a784000 {
compatible = "qcom,usb-emu-phy";
reg = <0x0a784000 0x9500>;
qcom,emu-init-seq = <0xfffff 0x4
0xffff0 0x4
0x100000 0x20
0x0 0x20
0x000101F0 0x20
0x00100000 0x3c
0x0 0x3c
0x0 0x4>;
};
};
&usb0 {
dwc3@a600000 {
usb-phy = <&usb_emuphy>, <&usb_nop_phy>;
dr_mode = "peripheral";
maximum-speed = "high-speed";
};
};

59
qcom/sun-usb.dtsi Normal file
View File

@@ -0,0 +1,59 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&soc {
usb0: ssusb@a600000 {
compatible = "qcom,dwc-usb3-msm";
reg = <0xa600000 0x100000>;
reg-names = "core_base";
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
<&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_PRIM_SLEEP_CLK>;
clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
"utmi_clk", "sleep_clk";
resets = <&gcc GCC_USB30_PRIM_BCR>;
reset-names = "core_reset";
interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event_irq";
qcom,dis-sending-cm-l1-quirk;
qcom,core-clk-rate = <200000000>;
qcom,core-clk-rate-hs = <66666667>;
qcom,core-clk-rate-disconnected = <133333333>;
dwc3@a600000 {
compatible = "snps,dwc3";
reg = <0xa600000 0xd93c>;
iommus = <&apps_smmu 0x40 0x0>;
qcom,iommu-dma = "bypass";
qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
dma-coherent;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
snps,disable-clk-gating;
snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x0>;
snps,is-utmi-l1-suspend;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
snps,dis_u2_susphy_quirk;
snps,ssp-u3-u0-quirk;
tx-fifo-resize;
dr_mode = "otg";
maximum-speed = "super-speed-plus";
usb-role-switch;
};
};
};

1
qcom/sun.dtsi
View File

@@ -899,6 +899,7 @@
#include "sun-pinctrl.dtsi"
#include "sun-regulators.dtsi"
#include "sun-qupv3.dtsi"
#include "sun-usb.dtsi"
&qupv3_se7_2uart {
status = "ok";