From 8e4ec07539dc4a3349cbdc16fdebfd529a5d30e0 Mon Sep 17 00:00:00 2001 From: kamasali Satyanarayan Date: Wed, 17 Apr 2024 12:41:12 +0530 Subject: [PATCH] ARM: dts: msm: Remove coherent and voltage-level property in Ravelin Ravelin target doesn't support IO coherency. So, remove the coherent property from storage nodes. Don't vote for voltage for regulators shared between eMMC and UFS to be in consistent with UFS design where regulator-min-microvolt and regulator-max-microvolt properties are removed from regulator device tree files for UFS regulators and to avoid below regulator API failures. [3.198613] pm6450_l24: unsupportable voltage range: 2960000-0uV [4.236846] sdhci_msm_vreg_set_voltage: regulator_set_voltage(vdd)failed. min_uV=2960000,max_uV=2960000,ret=-22. Change-Id: I780218b0903887e36589704af3e790a710932dd7 Signed-off-by: kamasali Satyanarayan --- qcom/ravelin-atp.dtsi | 1 - qcom/ravelin-idp.dtsi | 1 - qcom/ravelin-qrd.dtsi | 1 - qcom/ravelin-rumi.dtsi | 1 - qcom/ravelin.dtsi | 23 ++++++++++------------- 5 files changed, 10 insertions(+), 17 deletions(-) diff --git a/qcom/ravelin-atp.dtsi b/qcom/ravelin-atp.dtsi index f1aa4a4f..67401de2 100644 --- a/qcom/ravelin-atp.dtsi +++ b/qcom/ravelin-atp.dtsi @@ -56,7 +56,6 @@ &sdhc_2 { status = "ok"; vdd-supply = <&L24B>; - qcom,vdd-voltage-level = <2960000 2960000>; qcom,vdd-current-level = <0 800000>; /* diff --git a/qcom/ravelin-idp.dtsi b/qcom/ravelin-idp.dtsi index 5de7dd7b..568b5aa0 100644 --- a/qcom/ravelin-idp.dtsi +++ b/qcom/ravelin-idp.dtsi @@ -105,7 +105,6 @@ &sdhc_2 { status = "ok"; vdd-supply = <&L24B>; - qcom,vdd-voltage-level = <2960000 2960000>; qcom,vdd-current-level = <0 800000>; /* diff --git a/qcom/ravelin-qrd.dtsi b/qcom/ravelin-qrd.dtsi index cf9f8ecd..bbb43de5 100644 --- a/qcom/ravelin-qrd.dtsi +++ b/qcom/ravelin-qrd.dtsi @@ -56,7 +56,6 @@ &sdhc_2 { status = "ok"; vdd-supply = <&L24B>; - qcom,vdd-voltage-level = <2960000 2960000>; qcom,vdd-current-level = <0 800000>; /* diff --git a/qcom/ravelin-rumi.dtsi b/qcom/ravelin-rumi.dtsi index 8b32a2fc..28cae426 100644 --- a/qcom/ravelin-rumi.dtsi +++ b/qcom/ravelin-rumi.dtsi @@ -156,7 +156,6 @@ &sdhc_2 { status = "ok"; vdd-supply = <&L24B>; - qcom,vdd-voltage-level = <2960000 2960000>; qcom,vdd-current-level = <0 800000>; vdd-io-supply = <&L28B>; diff --git a/qcom/ravelin.dtsi b/qcom/ravelin.dtsi index 03f7f28e..d5d8158b 100644 --- a/qcom/ravelin.dtsi +++ b/qcom/ravelin.dtsi @@ -1736,6 +1736,11 @@ reg = <0x007C4000 0x1000>, <0x007C5000 0x1000>, <0x007C8000 0x8000>, <0x007D0000 0x9000>; reg-names = "hc", "cqhci", "cqhci_ice", "cqhci_ice_hwkm"; + iommus = <&apps_smmu 0x560 0x0>; + qcom,iommu-dma = "fastmap"; + + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; interrupts = , ; @@ -1765,6 +1770,11 @@ qcom,ice-clk-rates = <300000000 100000000>; + interconnects = <&aggre2_noc MASTER_SDCC_1 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_SDC1>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + operating-points-v2 = <&sdhc1_opp_table>; + /* DLL HSR settings. Refer go/hsr - DLL settings */ qcom,dll-hsr-list = <0x000F642C 0x0 0x01 0x2C010800 0x80040868>; @@ -1773,18 +1783,6 @@ resets = <&gcc GCC_SDCC1_BCR>; reset-names = "core_reset"; - iommus = <&apps_smmu 0x560 0x0>; - dma-coherent; - qcom,iommu-dma = "fastmap"; - - qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; - qcom,iommu-geometry = <0x40000000 0x10000000>; - - interconnects = <&aggre2_noc MASTER_SDCC_1 &mc_virt SLAVE_EBI1>, - <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_SDC1>; - interconnect-names = "sdhc-ddr","cpu-sdhc"; - operating-points-v2 = <&sdhc1_opp_table>; - qos0 { mask = <0x03>; vote = <44>; @@ -1837,7 +1835,6 @@ 0x2C010800 0x80040868>; iommus = <&apps_smmu 0x140 0x0>; - dma-coherent; qcom,iommu-dma = "fastmap"; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;