From dcbf0b3a52f509902b88f1f4bc6143c004274b71 Mon Sep 17 00:00:00 2001
From: Sai Harshini Nimmala <quic_snimmala@quicinc.com>
Date: Sun, 12 Nov 2023 10:17:57 -0800
Subject: [PATCH] dt-bindings: Add bindings for cycle counter driver

Adding a new node to devicetree for cycle counter driver. Add related
bindings file.

Change-Id: I381c5c693d96a054de1b3db5f9cd7ad8e4aa382b
Signed-off-by: Sai Harshini Nimmala <quic_snimmala@quicinc.com>
---
 qcom/qcom,cycle-cntr.yaml | 44 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)
 create mode 100644 qcom/qcom,cycle-cntr.yaml

diff --git a/qcom/qcom,cycle-cntr.yaml b/qcom/qcom,cycle-cntr.yaml
new file mode 100644
index 00000000..3d77e892
--- /dev/null
+++ b/qcom/qcom,cycle-cntr.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/qcom/qcom,cycle-cntr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. (QTI) Cycle Counter Driver
+
+maintainers:
+  - Sai Harshini Nimmala <quic_snimmala@quicinc.com>
+
+description: |
+
+    The various cycle counter drivers are used to read the cycle counter registers of the appropriate HW used in the Qualcomm Technologies, Inc. SoC.
+
+properties:
+  compatible:
+    oneOf:
+      - description: OSM cpufreq HW
+        items:
+          - const: qcom,cycle-cntr-hw
+
+      - description: EPSS cpufreq HW
+        items:
+          - const: qcom,epss
+
+      - description: NCC GCLK HW
+        items:
+          - const: qcom,gclk
+  reg:
+    items:
+      - description: Frequency domain 0 register region
+      - description: Frequency domain 1 register region
+      - description: Frequency domain 2 register region
+      - description: Frequency domain 3 register region
+
+  reg-names:
+    items:
+      - const: freq-domain0
+      - const: freq-domain1
+      - const: freq-domain2
+      - const: freq-domain3
+
+additionalProperties: false