From db1d959604adb9bf96ac27d891d416f83da411ed Mon Sep 17 00:00:00 2001 From: Swetha Chikkaboraiah Date: Wed, 31 Jan 2024 16:09:27 +0530 Subject: [PATCH] ARM: dts: msm: Add initial device tree for parrot Add initial device tree support for parrot target. This is a snapshot of dtsi files as of KP.1.0 'commit <3a433cd2ffb4> ("ARM: dts: msm: Add ext-region prop of cpusysvm for parrot")'. Change-Id: I582a3d131b94551da5f6d819003ab1a15ecd36f1 Signed-off-by: Swetha Chikkaboraiah --- qcom/Makefile | 34 + qcom/diwali-gdsc.dtsi | 410 ++ qcom/ipcc-test-parrot.dtsi | 10 + qcom/msm-arm-smmu-parrot.dtsi | 402 ++ qcom/parrot-4gb.dts | 14 + qcom/parrot-4gb.dtsi | 52 + qcom/parrot-atp-overlay.dts | 18 + qcom/parrot-atp.dts | 16 + qcom/parrot-atp.dtsi | 173 + qcom/parrot-coresight.dtsi | 3877 +++++++++++++++++ qcom/parrot-debug.dtsi | 1745 ++++++++ qcom/parrot-dma-heaps.dtsi | 48 + qcom/parrot-idp-4gb-overlay.dts | 18 + qcom/parrot-idp-4gb.dts | 17 + qcom/parrot-idp-4gb.dtsi | 6 + qcom/parrot-idp-nopmi-overlay.dts | 20 + qcom/parrot-idp-nopmi.dts | 18 + qcom/parrot-idp-overlay.dts | 19 + qcom/parrot-idp-pm7250b.dtsi | 42 + qcom/parrot-idp-pm8350b-overlay.dts | 19 + qcom/parrot-idp-pm8350b.dts | 17 + qcom/parrot-idp-pm8350b.dtsi | 41 + qcom/parrot-idp-wcn3990-4gb-overlay.dts | 18 + qcom/parrot-idp-wcn3990-4gb.dts | 17 + qcom/parrot-idp-wcn3990-4gb.dtsi | 6 + ...rot-idp-wcn3990-amoled-rcm-4gb-overlay.dts | 18 + qcom/parrot-idp-wcn3990-amoled-rcm-4gb.dts | 17 + qcom/parrot-idp-wcn3990-amoled-rcm-4gb.dtsi | 6 + .../parrot-idp-wcn3990-amoled-rcm-overlay.dts | 19 + qcom/parrot-idp-wcn3990-amoled-rcm.dts | 17 + qcom/parrot-idp-wcn3990-amoled-rcm.dtsi | 47 + qcom/parrot-idp-wcn3990-overlay.dts | 18 + qcom/parrot-idp-wcn3990.dts | 17 + qcom/parrot-idp-wcn3990.dtsi | 9 + .../parrot-idp-wcn6750-amoled-4gb-overlay.dts | 18 + qcom/parrot-idp-wcn6750-amoled-4gb.dts | 17 + qcom/parrot-idp-wcn6750-amoled-4gb.dtsi | 6 + qcom/parrot-idp-wcn6750-amoled-overlay.dts | 19 + ...rot-idp-wcn6750-amoled-rcm-4gb-overlay.dts | 18 + qcom/parrot-idp-wcn6750-amoled-rcm-4gb.dts | 17 + qcom/parrot-idp-wcn6750-amoled-rcm-4gb.dtsi | 6 + .../parrot-idp-wcn6750-amoled-rcm-overlay.dts | 19 + qcom/parrot-idp-wcn6750-amoled-rcm.dts | 17 + qcom/parrot-idp-wcn6750-amoled-rcm.dtsi | 47 + qcom/parrot-idp-wcn6750-amoled.dts | 17 + qcom/parrot-idp-wcn6750-amoled.dtsi | 47 + qcom/parrot-idp.dts | 17 + qcom/parrot-idp.dtsi | 169 + qcom/parrot-pinctrl.dtsi | 1890 ++++++++ qcom/parrot-pm7250b.dtsi | 341 ++ qcom/parrot-pm8350b.dtsi | 376 ++ qcom/parrot-pmic-overlay.dtsi | 700 +++ qcom/parrot-qrd-4gb-overlay.dts | 18 + qcom/parrot-qrd-4gb.dts | 17 + qcom/parrot-qrd-4gb.dtsi | 6 + qcom/parrot-qrd-nopmi-overlay.dts | 20 + qcom/parrot-qrd-nopmi.dts | 18 + qcom/parrot-qrd-overlay.dts | 19 + qcom/parrot-qrd-pm7250b.dtsi | 45 + qcom/parrot-qrd-pm8350b-overlay.dts | 19 + qcom/parrot-qrd-pm8350b.dts | 17 + qcom/parrot-qrd-pm8350b.dtsi | 41 + qcom/parrot-qrd-wcn6750-4gb-overlay.dts | 18 + qcom/parrot-qrd-wcn6750-4gb.dts | 17 + qcom/parrot-qrd-wcn6750-4gb.dtsi | 6 + qcom/parrot-qrd-wcn6750-overlay.dts | 19 + qcom/parrot-qrd-wcn6750.dts | 17 + qcom/parrot-qrd-wcn6750.dtsi | 9 + qcom/parrot-qrd.dts | 17 + qcom/parrot-qrd.dtsi | 155 + qcom/parrot-qupv3.dtsi | 583 +++ qcom/parrot-regulators.dtsi | 992 +++++ qcom/parrot-reserved-memory.dtsi | 178 + qcom/parrot-rumi-overlay.dts | 17 + qcom/parrot-rumi.dts | 17 + qcom/parrot-rumi.dtsi | 132 + qcom/parrot-sg-atp.dts | 16 + qcom/parrot-sg-atp.dtsi | 6 + qcom/parrot-sg-idp-nopmi.dts | 18 + qcom/parrot-sg-idp-pm8350b.dts | 17 + qcom/parrot-sg-idp-wcn3990-amoled-rcm.dts | 17 + qcom/parrot-sg-idp-wcn3990-amoled-rcm.dtsi | 6 + qcom/parrot-sg-idp-wcn3990.dts | 17 + qcom/parrot-sg-idp-wcn3990.dtsi | 6 + qcom/parrot-sg-idp-wcn6750-amoled-rcm.dts | 17 + qcom/parrot-sg-idp-wcn6750-amoled-rcm.dtsi | 6 + qcom/parrot-sg-idp-wcn6750-amoled.dts | 17 + qcom/parrot-sg-idp-wcn6750-amoled.dtsi | 6 + qcom/parrot-sg-idp.dts | 17 + qcom/parrot-sg-idp.dtsi | 6 + qcom/parrot-sg-qrd-nopmi.dts | 18 + qcom/parrot-sg-qrd-pm8350b.dts | 17 + qcom/parrot-sg-qrd-wcn6750.dts | 17 + qcom/parrot-sg-qrd-wcn6750.dtsi | 6 + qcom/parrot-sg-qrd.dts | 17 + qcom/parrot-sg-qrd.dtsi | 6 + qcom/parrot-sg.dts | 14 + qcom/parrot-sg.dtsi | 18 + qcom/parrot-stub-regulator.dtsi | 499 +++ qcom/parrot-thermal-overlay.dtsi | 143 + qcom/parrot-thermal.dtsi | 1165 +++++ qcom/parrot-usb.dtsi | 315 ++ qcom/parrot-wcn3990.dtsi | 34 + qcom/parrot-wcn6750.dtsi | 152 + qcom/parrot.dts | 14 + qcom/parrot.dtsi | 2861 ++++++++++++ qcom/parrotp-atp.dts | 16 + qcom/parrotp-atp.dtsi | 6 + qcom/parrotp-idp-nopmi.dts | 18 + qcom/parrotp-idp-pm8350b.dts | 17 + qcom/parrotp-idp-wcn3990-amoled-rcm.dts | 17 + qcom/parrotp-idp-wcn3990-amoled-rcm.dtsi | 6 + qcom/parrotp-idp-wcn3990.dts | 17 + qcom/parrotp-idp-wcn3990.dtsi | 6 + qcom/parrotp-idp-wcn6750-amoled-rcm.dts | 17 + qcom/parrotp-idp-wcn6750-amoled-rcm.dtsi | 6 + qcom/parrotp-idp-wcn6750-amoled.dts | 17 + qcom/parrotp-idp-wcn6750-amoled.dtsi | 6 + qcom/parrotp-idp.dts | 17 + qcom/parrotp-idp.dtsi | 6 + qcom/parrotp-qrd-nopmi.dts | 18 + qcom/parrotp-qrd-pm8350b.dts | 17 + qcom/parrotp-qrd-wcn6750.dts | 17 + qcom/parrotp-qrd-wcn6750.dtsi | 6 + qcom/parrotp-qrd.dts | 17 + qcom/parrotp-qrd.dtsi | 6 + qcom/parrotp-sg-atp.dts | 16 + qcom/parrotp-sg-atp.dtsi | 6 + qcom/parrotp-sg-idp-nopmi.dts | 18 + qcom/parrotp-sg-idp-pm8350b.dts | 17 + qcom/parrotp-sg-idp-wcn3990-amoled-rcm.dts | 17 + qcom/parrotp-sg-idp-wcn3990-amoled-rcm.dtsi | 6 + qcom/parrotp-sg-idp-wcn3990.dts | 17 + qcom/parrotp-sg-idp-wcn3990.dtsi | 6 + qcom/parrotp-sg-idp-wcn6750-amoled-rcm.dts | 17 + qcom/parrotp-sg-idp-wcn6750-amoled-rcm.dtsi | 6 + qcom/parrotp-sg-idp-wcn6750-amoled.dts | 17 + qcom/parrotp-sg-idp-wcn6750-amoled.dtsi | 6 + qcom/parrotp-sg-idp.dts | 17 + qcom/parrotp-sg-idp.dtsi | 6 + qcom/parrotp-sg-qrd-nopmi.dts | 18 + qcom/parrotp-sg-qrd-pm8350b.dts | 17 + qcom/parrotp-sg-qrd-wcn6750.dts | 17 + qcom/parrotp-sg-qrd-wcn6750.dtsi | 6 + qcom/parrotp-sg-qrd.dts | 17 + qcom/parrotp-sg-qrd.dtsi | 6 + qcom/parrotp-sg.dts | 14 + qcom/parrotp-sg.dtsi | 18 + qcom/parrotp.dts | 14 + qcom/parrotp.dtsi | 13 + qcom/platform_map.bzl | 33 + qcom/pm6150l.dtsi | 482 ++ qcom/pm6450.dtsi | 74 + qcom/pm7250b.dtsi | 374 ++ qcom/pm8350b.dtsi | 389 ++ qcom/pmk8350.dtsi | 258 ++ qcom/pmr735a.dtsi | 66 + qcom/waipio-thermal-modem.dtsi | 669 +++ 158 files changed, 21741 insertions(+) create mode 100644 qcom/diwali-gdsc.dtsi create mode 100644 qcom/ipcc-test-parrot.dtsi create mode 100644 qcom/msm-arm-smmu-parrot.dtsi create mode 100644 qcom/parrot-4gb.dts create mode 100644 qcom/parrot-4gb.dtsi create mode 100644 qcom/parrot-atp-overlay.dts create mode 100644 qcom/parrot-atp.dts create mode 100644 qcom/parrot-atp.dtsi create mode 100644 qcom/parrot-coresight.dtsi create mode 100644 qcom/parrot-debug.dtsi create mode 100644 qcom/parrot-dma-heaps.dtsi create mode 100644 qcom/parrot-idp-4gb-overlay.dts create mode 100644 qcom/parrot-idp-4gb.dts create mode 100644 qcom/parrot-idp-4gb.dtsi create mode 100644 qcom/parrot-idp-nopmi-overlay.dts create mode 100644 qcom/parrot-idp-nopmi.dts create mode 100644 qcom/parrot-idp-overlay.dts create mode 100644 qcom/parrot-idp-pm7250b.dtsi create mode 100644 qcom/parrot-idp-pm8350b-overlay.dts create mode 100644 qcom/parrot-idp-pm8350b.dts create mode 100644 qcom/parrot-idp-pm8350b.dtsi create mode 100644 qcom/parrot-idp-wcn3990-4gb-overlay.dts create mode 100644 qcom/parrot-idp-wcn3990-4gb.dts create mode 100644 qcom/parrot-idp-wcn3990-4gb.dtsi create mode 100644 qcom/parrot-idp-wcn3990-amoled-rcm-4gb-overlay.dts create mode 100644 qcom/parrot-idp-wcn3990-amoled-rcm-4gb.dts create mode 100644 qcom/parrot-idp-wcn3990-amoled-rcm-4gb.dtsi create mode 100644 qcom/parrot-idp-wcn3990-amoled-rcm-overlay.dts create mode 100644 qcom/parrot-idp-wcn3990-amoled-rcm.dts create mode 100644 qcom/parrot-idp-wcn3990-amoled-rcm.dtsi create mode 100644 qcom/parrot-idp-wcn3990-overlay.dts create mode 100644 qcom/parrot-idp-wcn3990.dts create mode 100644 qcom/parrot-idp-wcn3990.dtsi create mode 100644 qcom/parrot-idp-wcn6750-amoled-4gb-overlay.dts create mode 100644 qcom/parrot-idp-wcn6750-amoled-4gb.dts create mode 100644 qcom/parrot-idp-wcn6750-amoled-4gb.dtsi create mode 100644 qcom/parrot-idp-wcn6750-amoled-overlay.dts create mode 100644 qcom/parrot-idp-wcn6750-amoled-rcm-4gb-overlay.dts create mode 100644 qcom/parrot-idp-wcn6750-amoled-rcm-4gb.dts create mode 100644 qcom/parrot-idp-wcn6750-amoled-rcm-4gb.dtsi create mode 100644 qcom/parrot-idp-wcn6750-amoled-rcm-overlay.dts create mode 100644 qcom/parrot-idp-wcn6750-amoled-rcm.dts create mode 100644 qcom/parrot-idp-wcn6750-amoled-rcm.dtsi create mode 100644 qcom/parrot-idp-wcn6750-amoled.dts create mode 100644 qcom/parrot-idp-wcn6750-amoled.dtsi create mode 100644 qcom/parrot-idp.dts create mode 100644 qcom/parrot-idp.dtsi create mode 100644 qcom/parrot-pinctrl.dtsi create mode 100644 qcom/parrot-pm7250b.dtsi create mode 100644 qcom/parrot-pm8350b.dtsi create mode 100644 qcom/parrot-pmic-overlay.dtsi create mode 100644 qcom/parrot-qrd-4gb-overlay.dts create mode 100644 qcom/parrot-qrd-4gb.dts create mode 100644 qcom/parrot-qrd-4gb.dtsi create mode 100644 qcom/parrot-qrd-nopmi-overlay.dts create mode 100644 qcom/parrot-qrd-nopmi.dts create mode 100644 qcom/parrot-qrd-overlay.dts create mode 100644 qcom/parrot-qrd-pm7250b.dtsi create mode 100644 qcom/parrot-qrd-pm8350b-overlay.dts create mode 100644 qcom/parrot-qrd-pm8350b.dts create mode 100644 qcom/parrot-qrd-pm8350b.dtsi create mode 100644 qcom/parrot-qrd-wcn6750-4gb-overlay.dts create mode 100644 qcom/parrot-qrd-wcn6750-4gb.dts create mode 100644 qcom/parrot-qrd-wcn6750-4gb.dtsi create mode 100644 qcom/parrot-qrd-wcn6750-overlay.dts create mode 100644 qcom/parrot-qrd-wcn6750.dts create mode 100644 qcom/parrot-qrd-wcn6750.dtsi create mode 100644 qcom/parrot-qrd.dts create mode 100644 qcom/parrot-qrd.dtsi create mode 100644 qcom/parrot-qupv3.dtsi create mode 100644 qcom/parrot-regulators.dtsi create mode 100644 qcom/parrot-reserved-memory.dtsi create mode 100644 qcom/parrot-rumi-overlay.dts create mode 100644 qcom/parrot-rumi.dts create mode 100644 qcom/parrot-rumi.dtsi create mode 100644 qcom/parrot-sg-atp.dts create mode 100644 qcom/parrot-sg-atp.dtsi create mode 100644 qcom/parrot-sg-idp-nopmi.dts create mode 100644 qcom/parrot-sg-idp-pm8350b.dts create mode 100644 qcom/parrot-sg-idp-wcn3990-amoled-rcm.dts create mode 100644 qcom/parrot-sg-idp-wcn3990-amoled-rcm.dtsi create mode 100644 qcom/parrot-sg-idp-wcn3990.dts create mode 100644 qcom/parrot-sg-idp-wcn3990.dtsi create mode 100644 qcom/parrot-sg-idp-wcn6750-amoled-rcm.dts create mode 100644 qcom/parrot-sg-idp-wcn6750-amoled-rcm.dtsi create mode 100644 qcom/parrot-sg-idp-wcn6750-amoled.dts create mode 100644 qcom/parrot-sg-idp-wcn6750-amoled.dtsi create mode 100644 qcom/parrot-sg-idp.dts create mode 100644 qcom/parrot-sg-idp.dtsi create mode 100644 qcom/parrot-sg-qrd-nopmi.dts create mode 100644 qcom/parrot-sg-qrd-pm8350b.dts create mode 100644 qcom/parrot-sg-qrd-wcn6750.dts create mode 100644 qcom/parrot-sg-qrd-wcn6750.dtsi create mode 100644 qcom/parrot-sg-qrd.dts create mode 100644 qcom/parrot-sg-qrd.dtsi create mode 100644 qcom/parrot-sg.dts create mode 100644 qcom/parrot-sg.dtsi create mode 100644 qcom/parrot-stub-regulator.dtsi create mode 100644 qcom/parrot-thermal-overlay.dtsi create mode 100644 qcom/parrot-thermal.dtsi create mode 100644 qcom/parrot-usb.dtsi create mode 100644 qcom/parrot-wcn3990.dtsi create mode 100644 qcom/parrot-wcn6750.dtsi create mode 100644 qcom/parrot.dts create mode 100644 qcom/parrot.dtsi create mode 100644 qcom/parrotp-atp.dts create mode 100644 qcom/parrotp-atp.dtsi create mode 100644 qcom/parrotp-idp-nopmi.dts create mode 100644 qcom/parrotp-idp-pm8350b.dts create mode 100644 qcom/parrotp-idp-wcn3990-amoled-rcm.dts create mode 100644 qcom/parrotp-idp-wcn3990-amoled-rcm.dtsi create mode 100644 qcom/parrotp-idp-wcn3990.dts create mode 100644 qcom/parrotp-idp-wcn3990.dtsi create mode 100644 qcom/parrotp-idp-wcn6750-amoled-rcm.dts create mode 100644 qcom/parrotp-idp-wcn6750-amoled-rcm.dtsi create mode 100644 qcom/parrotp-idp-wcn6750-amoled.dts create mode 100644 qcom/parrotp-idp-wcn6750-amoled.dtsi create mode 100644 qcom/parrotp-idp.dts create mode 100644 qcom/parrotp-idp.dtsi create mode 100644 qcom/parrotp-qrd-nopmi.dts create mode 100644 qcom/parrotp-qrd-pm8350b.dts create mode 100644 qcom/parrotp-qrd-wcn6750.dts create mode 100644 qcom/parrotp-qrd-wcn6750.dtsi create mode 100644 qcom/parrotp-qrd.dts create mode 100644 qcom/parrotp-qrd.dtsi create mode 100644 qcom/parrotp-sg-atp.dts create mode 100644 qcom/parrotp-sg-atp.dtsi create mode 100644 qcom/parrotp-sg-idp-nopmi.dts create mode 100644 qcom/parrotp-sg-idp-pm8350b.dts create mode 100644 qcom/parrotp-sg-idp-wcn3990-amoled-rcm.dts create mode 100644 qcom/parrotp-sg-idp-wcn3990-amoled-rcm.dtsi create mode 100644 qcom/parrotp-sg-idp-wcn3990.dts create mode 100644 qcom/parrotp-sg-idp-wcn3990.dtsi create mode 100644 qcom/parrotp-sg-idp-wcn6750-amoled-rcm.dts create mode 100644 qcom/parrotp-sg-idp-wcn6750-amoled-rcm.dtsi create mode 100644 qcom/parrotp-sg-idp-wcn6750-amoled.dts create mode 100644 qcom/parrotp-sg-idp-wcn6750-amoled.dtsi create mode 100644 qcom/parrotp-sg-idp.dts create mode 100644 qcom/parrotp-sg-idp.dtsi create mode 100644 qcom/parrotp-sg-qrd-nopmi.dts create mode 100644 qcom/parrotp-sg-qrd-pm8350b.dts create mode 100644 qcom/parrotp-sg-qrd-wcn6750.dts create mode 100644 qcom/parrotp-sg-qrd-wcn6750.dtsi create mode 100644 qcom/parrotp-sg-qrd.dts create mode 100644 qcom/parrotp-sg-qrd.dtsi create mode 100644 qcom/parrotp-sg.dts create mode 100644 qcom/parrotp-sg.dtsi create mode 100644 qcom/parrotp.dts create mode 100644 qcom/parrotp.dtsi create mode 100644 qcom/pm6150l.dtsi create mode 100644 qcom/pm6450.dtsi create mode 100644 qcom/pm7250b.dtsi create mode 100644 qcom/pm8350b.dtsi create mode 100644 qcom/pmk8350.dtsi create mode 100644 qcom/pmr735a.dtsi create mode 100644 qcom/waipio-thermal-modem.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index b6f67d4e..b57fb47e 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -74,6 +74,40 @@ pineapple-dtb-$(CONFIG_ARCH_PINEAPPLE) += \ pineapple-overlays-dtb-$(CONFIG_ARCH_PINEAPPLE) += $(PINEAPPLE_BOARDS) $(NOAPQ_PINEAPPLE_BOARDS) $(PINEAPPLE_BASE_DTB) $(PINEAPPLE_APQ_BASE_DTB) dtb-y += $(pineapple-dtb-y) +PARROT_BASE_DTB += parrot.dtb parrotp.dtb parrot-sg.dtb parrotp-sg.dtb +PARROT_4GB_BASE_DTB += parrot-4gb.dtb + +PARROT_BOARDS += \ + parrot-rumi-overlay.dtbo \ + parrot-atp-overlay.dtbo \ + parrot-idp-overlay.dtbo \ + parrot-idp-wcn3990-overlay.dtbo \ + parrot-idp-wcn3990-amoled-rcm-overlay.dtbo \ + parrot-idp-wcn6750-amoled-rcm-overlay.dtbo \ + parrot-idp-wcn6750-amoled-overlay.dtbo \ + parrot-idp-nopmi-overlay.dtbo \ + parrot-idp-pm8350b-overlay.dtbo \ + parrot-qrd-overlay.dtbo \ + parrot-qrd-wcn6750-overlay.dtbo \ + parrot-qrd-nopmi-overlay.dtbo \ + parrot-qrd-pm8350b-overlay.dtbo + +PARROT_4GB_BOARDS += \ + parrot-idp-4gb-overlay.dtbo \ + parrot-idp-wcn3990-4gb-overlay.dtbo \ + parrot-idp-wcn3990-amoled-rcm-4gb-overlay.dtbo \ + parrot-idp-wcn6750-amoled-rcm-4gb-overlay.dtbo \ + parrot-idp-wcn6750-amoled-4gb-overlay.dtbo \ + parrot-qrd-4gb-overlay.dtbo \ + parrot-qrd-wcn6750-4gb-overlay.dtbo \ + + +parrot-dtb-$(CONFIG_ARCH_PARROT) += \ + $(call add-overlays, $(PARROT_BOARDS),$(PARROT_BASE_DTB)) \ + $(call add-overlays, $(PARROT_4GB_BOARDS),$(PARROT_4GB_BASE_DTB)) +parrot-overlays-dtb-$(CONFIG_ARCH_PARROT) += $(PARROT_BOARDS) $(PARROT_BASE_DTB) $(PARROT_4GB_BOARDS) $(PARROT_4GB_BASE_DTB) +dtb-y += $(parrot-dtb-y) + endif ifeq ($(CONFIG_ARCH_PINEAPPLE), y) diff --git a/qcom/diwali-gdsc.dtsi b/qcom/diwali-gdsc.dtsi new file mode 100644 index 00000000..6702c776 --- /dev/null +++ b/qcom/diwali-gdsc.dtsi @@ -0,0 +1,410 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + /* CAM_CC GDSCs */ + cam_cc_bps_gdsc: qcom,gdsc@ad10004 { + compatible = "qcom,gdsc"; + reg = <0xad10004 0x4>; + regulator-name = "cam_cc_bps_gdsc"; + qcom,retain-regs; + qcom,support-hw-trigger; + status = "disabled"; + }; + + cam_cc_ife_0_gdsc: qcom,gdsc@ad13004 { + compatible = "qcom,gdsc"; + reg = <0xad13004 0x4>; + regulator-name = "cam_cc_ife_0_gdsc"; + qcom,retain-regs; + status = "disabled"; + }; + + cam_cc_ife_1_gdsc: qcom,gdsc@ad14004 { + compatible = "qcom,gdsc"; + reg = <0xad14004 0x4>; + regulator-name = "cam_cc_ife_1_gdsc"; + qcom,retain-regs; + status = "disabled"; + }; + + cam_cc_ife_2_gdsc: qcom,gdsc@ad14078 { + compatible = "qcom,gdsc"; + reg = <0xad14078 0x4>; + regulator-name = "cam_cc_ife_2_gdsc"; + qcom,retain-regs; + status = "disabled"; + }; + + cam_cc_ipe_0_gdsc: qcom,gdsc@ad11004 { + compatible = "qcom,gdsc"; + reg = <0xad11004 0x4>; + regulator-name = "cam_cc_ipe_0_gdsc"; + qcom,retain-regs; + qcom,support-hw-trigger; + status = "disabled"; + }; + + cam_cc_titan_top_gdsc: qcom,gdsc@ad15120 { + compatible = "qcom,gdsc"; + reg = <0xad15120 0x4>; + regulator-name = "cam_cc_titan_top_gdsc"; + qcom,retain-regs; + status = "disabled"; + }; + + cam_cc_camss_top_gdsc: qcom,gdsc@adf4004 { + compatible = "qcom,gdsc"; + reg = <0xadf4004 0x4>; + regulator-name = "cam_cc_camss_top_gdsc"; + qcom,retain-regs; + status = "disabled"; + }; + + /* DISP_CC GDSCs */ + disp_cc_mdss_core_gdsc: qcom,gdsc@af09000 { + compatible = "qcom,gdsc"; + reg = <0xaf09000 0x4>; + regulator-name = "disp_cc_mdss_core_gdsc"; + proxy-supply = <&disp_cc_mdss_core_gdsc>; + qcom,proxy-consumer-enable; + qcom,retain-regs; + qcom,support-hw-trigger; + status = "disabled"; + }; + + disp_cc_mdss_core_int2_gdsc: qcom,gdsc@af0b000 { + compatible = "qcom,gdsc"; + reg = <0xaf0b000 0x4>; + regulator-name = "disp_cc_mdss_core_int2_gdsc"; + qcom,retain-regs; + qcom,support-hw-trigger; + status = "disabled"; + }; + + /* DISP_CC_0 GDSCs */ + disp0_cc_mdss_core_gdsc: qcom,disp0-gdsc@af09000 { + compatible = "qcom,gdsc"; + reg = <0xaf09000 0x4>; + regulator-name = "disp0_cc_mdss_core_gdsc"; + proxy-supply = <&disp0_cc_mdss_core_gdsc>; + qcom,proxy-consumer-enable; + qcom,retain-regs; + qcom,support-hw-trigger; + status = "disabled"; + }; + + disp0_cc_mdss_core_int2_gdsc: qcom,disp0-gdsc@af0b000 { + compatible = "qcom,gdsc"; + reg = <0xaf0b000 0x4>; + regulator-name = "disp0_cc_mdss_core_int2_gdsc"; + qcom,retain-regs; + qcom,support-hw-trigger; + status = "disabled"; + }; + + /* DISP_CC_1 GDSCs */ + disp1_cc_mdss_core_gdsc: qcom,disp1-gdsc@15709000 { + compatible = "qcom,gdsc"; + reg = <0x15709000 0x4>; + regulator-name = "disp1_cc_mdss_core_gdsc"; + proxy-supply = <&disp1_cc_mdss_core_gdsc>; + qcom,proxy-consumer-enable; + qcom,retain-regs; + qcom,support-hw-trigger; + status = "disabled"; + }; + + disp1_cc_mdss_core_int2_gdsc: qcom,disp1-gdsc@1570b000 { + compatible = "qcom,gdsc"; + reg = <0x1570b000 0x4>; + regulator-name = "disp1_cc_mdss_core_int2_gdsc"; + qcom,retain-regs; + qcom,support-hw-trigger; + status = "disabled"; + }; + + gcc_apcs_gdsc_vote_ctrl: syscon@162128 { + compatible = "syscon"; + reg = <0x162128 0x4>; + }; + + gcc_apcs_gdsc_sleep_ctrl: syscon@162204 { + compatible = "syscon"; + reg = <0x162204 0x4>; + }; + + /* GCC GDSCs */ + gcc_pcie_0_gdsc: qcom,gdsc@17b004 { + compatible = "qcom,gdsc"; + reg = <0x17b004 0x4>; + regulator-name = "gcc_pcie_0_gdsc"; + qcom,retain-regs; + qcom,support-hw-trigger; + qcom,no-status-check-on-disable; + qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 0>; + status = "disabled"; + }; + + gcc_ufs_phy_gdsc: qcom,gdsc@187004 { + compatible = "qcom,gdsc"; + reg = <0x187004 0x4>; + regulator-name = "gcc_ufs_phy_gdsc"; + qcom,retain-regs; + proxy-supply = <&gcc_ufs_phy_gdsc>; + qcom,proxy-consumer-enable; + status = "disabled"; + }; + + gcc_usb30_prim_gdsc: qcom,gdsc@149004 { + compatible = "qcom,gdsc"; + reg = <0x149004 0x4>; + regulator-name = "gcc_usb30_prim_gdsc"; + qcom,retain-regs; + proxy-supply = <&gcc_usb30_prim_gdsc>; + qcom,proxy-consumer-enable; + status = "disabled"; + }; + + gcc_pcie_0_phy_gdsc: qcom,gdsc@17c000 { + compatible = "qcom,gdsc"; + reg = <0x17c000 0x4>; + regulator-name = "gcc_pcie_0_phy_gdsc"; + qcom,retain-regs; + qcom,no-status-check-on-disable; + qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 3>; + status = "disabled"; + }; + + gcc_pcie_1_gdsc: qcom,gdsc@19d004 { + compatible = "qcom,gdsc"; + reg = <0x19d004 0x4>; + regulator-name = "gcc_pcie_1_gdsc"; + qcom,retain-regs; + qcom,no-status-check-on-disable; + qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 1>; + status = "disabled"; + }; + + gcc_pcie_1_phy_gdsc: qcom,gdsc@19e000 { + compatible = "qcom,gdsc"; + reg = <0x19e000 0x4>; + regulator-name = "gcc_pcie_1_phy_gdsc"; + qcom,retain-regs; + qcom,no-status-check-on-disable; + qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 4>; + status = "disabled"; + }; + + gcc_pcie_2_gdsc: qcom,pcie2-gdsc@19d004 { + compatible = "qcom,gdsc"; + reg = <0x19d004 0x4>; + regulator-name = "gcc_pcie_2_gdsc"; + qcom,retain-regs; + qcom,support-hw-trigger; + qcom,no-status-check-on-disable; + qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 2>; + status = "disabled"; + }; + + gcc_usb3_phy_gdsc: qcom,gdsc@160018 { + compatible = "qcom,gdsc"; + reg = <0x160018 0x4>; + regulator-name = "gcc_usb3_phy_gdsc"; + qcom,retain-regs; + status = "disabled"; + }; + + gcc_venus_gdsc: qcom,gdsc@1b6020 { + compatible = "qcom,gdsc"; + reg = <0x1b6020 0x4>; + regulator-name = "gcc_venus_gdsc"; + qcom,retain-regs; + status = "disabled"; + }; + + gcc_vcodec0_gdsc: qcom,gdsc@1b6044 { + compatible = "qcom,gdsc"; + reg = <0x1b6044 0x4>; + regulator-name = "gcc_vcodec0_gdsc"; + qcom,retain-regs; + qcom,support-hw-trigger; + status = "disabled"; + }; + + hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@18d050 { + compatible = "qcom,gdsc"; + reg = <0x18d050 0x4>; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc"; + qcom,no-status-check-on-disable; + status = "disabled"; + }; + + hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc: qcom,gdsc@18d058 { + compatible = "qcom,gdsc"; + reg = <0x18d058 0x4>; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc"; + qcom,no-status-check-on-disable; + status = "disabled"; + }; + + hlos1_vote_mmnoc_mmu_tbu_hf2_gdsc: qcom,gdsc@18d078 { + compatible = "qcom,gdsc"; + reg = <0x18d078 0x4>; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf2_gdsc"; + qcom,no-status-check-on-disable; + status = "disabled"; + }; + + hlos1_vote_mmnoc_mmu_tbu_hf3_gdsc: qcom,gdsc@18d07c { + compatible = "qcom,gdsc"; + reg = <0x18d07c 0x4>; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf3_gdsc"; + qcom,no-status-check-on-disable; + status = "disabled"; + }; + + hlos1_vote_mmnoc_mmu_tbu_hf4_gdsc: qcom,gdsc@18d088 { + compatible = "qcom,gdsc"; + reg = <0x18d088 0x4>; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf4_gdsc"; + qcom,no-status-check-on-disable; + status = "disabled"; + }; + + hlos1_vote_mmnoc_mmu_tbu_hf5_gdsc: qcom,gdsc@18d08c { + compatible = "qcom,gdsc"; + reg = <0x18d08c 0x4>; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf5_gdsc"; + qcom,no-status-check-on-disable; + status = "disabled"; + }; + + hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc: qcom,gdsc@18d054 { + compatible = "qcom,gdsc"; + reg = <0x18d054 0x4>; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc"; + qcom,no-status-check-on-disable; + status = "disabled"; + }; + + hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc: qcom,gdsc@18d06c { + compatible = "qcom,gdsc"; + reg = <0x18d06c 0x4>; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc"; + qcom,no-status-check-on-disable; + status = "disabled"; + }; + + hlos1_vote_turing_mmu_tbu0_gdsc: qcom,gdsc@18d05c { + compatible = "qcom,gdsc"; + reg = <0x18d05c 0x4>; + regulator-name = "hlos1_vote_turing_mmu_tbu0_gdsc"; + qcom,no-status-check-on-disable; + status = "disabled"; + }; + + hlos1_vote_turing_mmu_tbu1_gdsc: qcom,gdsc@18d060 { + compatible = "qcom,gdsc"; + reg = <0x18d060 0x4>; + regulator-name = "hlos1_vote_turing_mmu_tbu1_gdsc"; + qcom,no-status-check-on-disable; + status = "disabled"; + }; + + /* GPU_CC GDSCs */ + gpu_cc_cx_hw_ctrl: syscon@3d9953c { + compatible = "syscon"; + reg = <0x3d9953c 0x4>; + }; + + /* GPU_CC GDSCs */ + gpu_cc_cx_gdsc: qcom,gdsc@3d99108 { + compatible = "qcom,gdsc"; + reg = <0x3d99108 0x4>; + hw-ctrl-addr = <&gpu_cc_cx_hw_ctrl>; + regulator-name = "gpu_cc_cx_gdsc"; + qcom,no-status-check-on-disable; + qcom,clk-dis-wait-val = <8>; + qcom,retain-regs; + status = "disabled"; + }; + + gpu_cc_gx_domain_addr: syscon@3d99504 { + compatible = "syscon"; + reg = <0x3d99504 0x4>; + }; + + gpu_cc_gx_sw_reset: syscon@3d99058 { + compatible = "syscon"; + reg = <0x3d99058 0x4>; + }; + + gpu_cc_gx_acd_reset: syscon@3d99358 { + compatible = "syscon"; + reg = <0x3d99358 0x4>; + }; + + gpu_cc_gx_acd_iroot_reset: syscon@3d9958c { + compatible = "syscon"; + reg = <0x3d9958c 0x4>; + }; + + gpu_cc_gx_gdsc: qcom,gdsc@3d9905c { + compatible = "qcom,gdsc"; + reg = <0x3d9905c 0x4>; + regulator-name = "gpu_cc_gx_gdsc"; + domain-addr = <&gpu_cc_gx_domain_addr>; + sw-reset = <&gpu_cc_gx_sw_reset>, + <&gpu_cc_gx_acd_reset>, + <&gpu_cc_gx_acd_iroot_reset>; + qcom,reset-aon-logic; + qcom,retain-regs; + status = "disabled"; + }; + + /* VIDEO_CC GDSCs */ + video_cc_mvs0_gdsc: qcom,gdsc@aaf81a4 { + compatible = "qcom,gdsc"; + reg = <0xaaf81a4 0x4>; + regulator-name = "video_cc_mvs0_gdsc"; + qcom,retain-regs; + qcom,support-hw-trigger; + status = "disabled"; + }; + + video_cc_mvs0c_gdsc: qcom,gdsc@aaf8084 { + compatible = "qcom,gdsc"; + reg = <0xaaf8084 0x4>; + regulator-name = "video_cc_mvs0c_gdsc"; + qcom,retain-regs; + status = "disabled"; + }; + + video_cc_mvs1_gdsc: qcom,gdsc@aaf8244 { + compatible = "qcom,gdsc"; + reg = <0xaaf8244 0x4>; + regulator-name = "video_cc_mvs1_gdsc"; + qcom,retain-regs; + qcom,support-hw-trigger; + status = "disabled"; + }; + + video_cc_mvs1c_gdsc: qcom,gdsc@aaf8124 { + compatible = "qcom,gdsc"; + reg = <0xaaf8124 0x4>; + regulator-name = "video_cc_mvs1c_gdsc"; + qcom,retain-regs; + status = "disabled"; + }; + + video_cc_mvsc_gdsc: qcom,gdsc@aaf5004 { + compatible = "qcom,gdsc"; + reg = <0xaaf5004 0x4>; + regulator-name = "video_cc_mvsc_gdsc"; + qcom,retain-regs; + status = "disabled"; + }; +}; diff --git a/qcom/ipcc-test-parrot.dtsi b/qcom/ipcc-test-parrot.dtsi new file mode 100644 index 00000000..bf439c38 --- /dev/null +++ b/qcom/ipcc-test-parrot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ipcc-test.dtsi" + +&soc { + /delete-node/ ipcc-self-ping-slpi; +}; diff --git a/qcom/msm-arm-smmu-parrot.dtsi b/qcom/msm-arm-smmu-parrot.dtsi new file mode 100644 index 00000000..4288eff9 --- /dev/null +++ b/qcom/msm-arm-smmu-parrot.dtsi @@ -0,0 +1,402 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + kgsl_smmu: kgsl-smmu@3da0000 { + compatible = "qcom,qsmmu-v500", "qcom,adreno-smmu"; + reg = <0x3da0000 0x40000>, + <0x3de6000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + qcom,num-context-banks-override = <0x6>; + qcom,num-smr-override = <0x6>; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + dma-coherent; + + qcom,regulator-names = "vdd"; + vdd-supply = <&gpu_cc_cx_gdsc>; + + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + clock-names = + "gpu_cc_cx_gmu", + "gpu_cc_hub_cx_int", + "gpu_cc_hlos1_vote_gpu_smmu", + "gcc_gpu_memnoc_gfx", + "gcc_gpu_snoc_dvm_gfx", + "gpu_cc_ahb"; + + qcom,actlr = + /* All CBs of GFX: +15 deep PF */ + <0x000 0x7ff 0x32B>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + gfx_0_tbu: gfx_0_tbu@3de9000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x3de9000 0x1000>, + <0x3de6200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + qcom,iova-width = <49>; + }; + + gfx_1_tbu: gfx_1_tbu@3ded000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x3ded000 0x1000>, + <0x3de6208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x400 0x400>; + qcom,iova-width = <49>; + }; + }; + + apps_smmu: apps-smmu@15000000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15000000 0x100000>, + <0x151da000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + qcom,num-context-banks-override = <0x4e>; + qcom,num-smr-override = <0x78>; + qcom,handoff-smrs = <0x800 0x402>; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + dma-coherent; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + qcom,actlr = + /* Camera clients, +0 PF */ + <0x8A0 0x4A0 0x1>, + <0xcA0 0x4A0 0x1>, + <0x2000 0xE0 0x1>, + <0x2100 0x60 0x1>, + /* For Display clients, +3 PF */ + <0x800 0x407 0x103>, + <0xc00 0x407 0x103>, + /* For video clients, +0 PF */ + <0x2180 0x27 0x1>, + /* NSP clients, +15PF */ + <0x1000 0x7ff 0x303>; + + interconnects = <&gem_noc MASTER_APPSS_PROC + &cnoc3 SLAVE_TCU>; + qcom,active-only; + + anoc_1_tbu: anoc_1_tbu@151dd000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151dd000 0x1000>, + <0x151da200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + qcom,iova-width = <36>; + qcom,micro-idle; + interconnects = <&gem_noc MASTER_APPSS_PROC + &cnoc3 SLAVE_IMEM>; + qcom,active-only; + }; + + anoc_2_tbu: anoc_2_tbu@151e1000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151e1000 0x1000>, + <0x151da208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x400 0x400>; + qcom,iova-width = <36>; + qcom,micro-idle; + interconnects = <&gem_noc MASTER_APPSS_PROC + &cnoc3 SLAVE_IMEM>; + qcom,active-only; + }; + + mnoc_hf_0_tbu: mnoc_hf_0_tbu@151e5000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151e5000 0x1000>, + <0x151da210 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x800 0x400>; + qcom,iova-width = <36>; + qcom,micro-idle; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>; + interconnects = <&mmss_noc MASTER_CAMNOC_HF + &mc_virt SLAVE_EBI1>; + qcom,active-only; + }; + + mnoc_hf_1_tbu: mnoc_hf_1_tbu@151e9000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151e9000 0x1000>, + <0x151da218 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0xc00 0x400>; + qcom,iova-width = <36>; + qcom,micro-idle; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc>; + interconnects = <&mmss_noc MASTER_CAMNOC_HF + &mc_virt SLAVE_EBI1>; + qcom,active-only; + }; + + compute_1_tbu: compute_1_tbu@151ed000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151ed000 0x1000>, + <0x151da220 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1000 0x400>; + qcom,iova-width = <36>; + qcom,micro-idle; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_turing_mmu_tbu1_gdsc>; + interconnects = <&nsp_noc MASTER_CDSP_PROC + &mc_virt SLAVE_EBI1>; + qcom,active-only; + }; + + compute_0_tbu: compute_0_tbu@151f1000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151f1000 0x1000>, + <0x151da228 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1400 0x400>; + qcom,iova-width = <36>; + qcom,micro-idle; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_turing_mmu_tbu0_gdsc>; + interconnects = <&nsp_noc MASTER_CDSP_PROC + &mc_virt SLAVE_EBI1>; + qcom,active-only; + }; + + lpass_tbu: lpass_tbu@151f5000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151f5000 0x1000>, + <0x151da230 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1800 0x400>; + qcom,iova-width = <36>; + qcom,micro-idle; + interconnects = <&lpass_ag_noc MASTER_LPASS_PROC + &mc_virt SLAVE_EBI1>; + qcom,active-only; + }; + + pcie_tbu: pcie_tbu@151f9000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151f9000 0x1000>, + <0x151da238 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1c00 0x400>; + qcom,iova-width = <36>; + qcom,micro-idle; + interconnects = <&pcie_noc MASTER_PCIE_0 + &mc_virt SLAVE_EBI1>; + qcom,active-only; + }; + + sf_0_tbu: sf_0_tbu@151fd000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151fd000 0x1000>, + <0x151da240 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x2000 0x400>; + qcom,iova-width = <36>; + qcom,micro-idle; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc>; + interconnects = <&mmss_noc MASTER_CAMNOC_SF + &mc_virt SLAVE_EBI1>; + qcom,active-only; + }; + }; + + dma_dev@0x0 { + compatible = "qcom,iommu-dma"; + memory-region = <&system_cma>; + }; + + iommu_test_device { + compatible = "qcom,iommu-debug-test"; + + usecase0_apps { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x7e0 0>; + }; + + usecase1_apps_fastmap { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x7e0 0>; + qcom,iommu-dma = "fastmap"; + }; + + usecase2_apps_atomic { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x7e0 0>; + qcom,iommu-dma = "atomic"; + }; + + usecase3_apps_dma { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x7e1 0>; + dma-coherent; + }; + + usecase4_apps_secure { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x7e0 0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */ + }; + + usecase5_kgsl { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&kgsl_smmu 0x7 0x400>; + }; + + usecase6_kgsl_dma { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&kgsl_smmu 0x407 0x400>; + dma-coherent; + }; + }; +}; diff --git a/qcom/parrot-4gb.dts b/qcom/parrot-4gb.dts new file mode 100644 index 00000000..adf57bfa --- /dev/null +++ b/qcom/parrot-4gb.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrot-4gb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot 4Gb SoC"; + compatible = "qcom,parrot"; + qcom,board-id = <0 0x600>; +}; diff --git a/qcom/parrot-4gb.dtsi b/qcom/parrot-4gb.dtsi new file mode 100644 index 00000000..cea98f38 --- /dev/null +++ b/qcom/parrot-4gb.dtsi @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot.dtsi" +/ { +}; + +&non_secure_display_dma_buf { + status = "disabled"; +}; + +&non_secure_display_memory { + status = "disabled"; +}; + +&mem_client_3_size { + qcom,peripheral-size = <0x200000>; +}; + +&trust_ui_vm_mem { + status = "disabled"; +}; + +&trust_ui_vm_qrtr { + status = "disabled"; +}; + +&trust_ui_vm_vblk0_ring { + status = "disabled"; +}; + +&trust_ui_vm_swiotlb { + status = "disabled"; +}; + +&soc { + + qcom,guestvm_loader@e0b00000 { + status = "disabled"; + }; + + qrtr-gunyah { + status = "disabled"; + }; + + qcom,virtio_backend@0 { + status = "disabled"; + }; + +}; diff --git a/qcom/parrot-atp-overlay.dts b/qcom/parrot-atp-overlay.dts new file mode 100644 index 00000000..c57cbf6f --- /dev/null +++ b/qcom/parrot-atp-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "parrot-wcn3990.dtsi" +#include "parrot-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot ATP"; + compatible = "qcom,parrot-atp", "qcom,parrot", "qcom,atp"; + qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>, + <633 0x10000>, <634 0x10000>, <638 0x10000>; + qcom,board-id = <33 0>; +}; diff --git a/qcom/parrot-atp.dts b/qcom/parrot-atp.dts new file mode 100644 index 00000000..c916fa4f --- /dev/null +++ b/qcom/parrot-atp.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrot.dtsi" +#include "parrot-wcn3990.dtsi" +#include "parrot-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot ATP"; + compatible = "qcom,parrot-atp", "qcom,parrot", "qcom,atp"; + qcom,board-id = <33 0>; +}; diff --git a/qcom/parrot-atp.dtsi b/qcom/parrot-atp.dtsi new file mode 100644 index 00000000..0cd7562a --- /dev/null +++ b/qcom/parrot-atp.dtsi @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +#include "parrot-pm7250b.dtsi" +#include "parrot-pmic-overlay.dtsi" +#include "parrot-thermal-overlay.dtsi" + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pm6450_gpios 1 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + }; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4-waipio"; + + vdda-phy-supply = <&L5B>; + vdda-pll-supply = <&L16B>; + vdda-phy-max-microamp = <140000>; + vdda-pll-max-microamp = <18300>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + + vcc-supply = <&L24B>; + vcc-max-microamp = <1200000>; + + vccq-supply = <&L13B>; + vccq-max-microamp = <1200000>; + + vccq2-supply = <&L19B>; + vccq2-max-microamp = <750000>; + + qcom,vddp-ref-clk-supply = <&L13B>; + qcom,vddp-ref-clk-max-microamp = <100>; + + /* + * ufs-dev-types and nvmem entries are for ufs device + * identification using nvmem interface. Use number of + * ufs devices supported for ufs-dev-types, and nvmem handle + * added by pmic for sdam register. + * + * Default value taken by driver is bit[0] = 0 for 3.x and + * bit[0] = 1 for 2.x driver code takes this as default case. + * + * But Bit value to identify ufs device is not consistent + * across the targets it could be bit[0] = 0/1 for UFS2.x/3x + * and vice versa. If the bit[0] value is not same as default + * value used in driver and if its reverted then use flag + * qcom,ufs-dev-revert to identify ufs device. + */ + ufs-dev-types = <2>; + qcom,ufs-dev-revert; + nvmem-cells = <&ufs_dev>, <&boot_config>; + nvmem-cell-names = "ufs_dev", "boot_conf"; + + status = "ok"; +}; + +&battery_charger { + qcom,thermal-mitigation = <3000000 1500000 1000000 500000>; + qcom,wireless-charging-not-supported; +}; + +&qupv3_se9_spi { + status = "ok"; + + #address-cells = <1>; + #size-cells = <0>; + qcom,spi-touch-active = "focaltech,fts_ts"; + + focaltech@0 { + reg = <0x0>; + spi-max-frequency = <6000000>; + interrupt-parent = <&tlmm>; + interrupts = <65 0x2008>; + focaltech,reset-gpio = <&tlmm 64 0x00>; + focaltech,irq-gpio = <&tlmm 65 0x2008>; + focaltech,display-coords = <0 0 1080 2340>; + focaltech,max-touch-number = <5>; + focaltech,ic-type = <0x3658D488>; + focaltech,touch-type = "primary"; + + vdd-supply = <&L28B>; + + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", "pmx_ts_release"; + pinctrl-0 = <&ts_spi_active>; + pinctrl-1 = <&ts_spi_int_suspend &ts_spi_reset_suspend>; + pinctrl-2 = <&ts_spi_release>; + }; +}; + +&sdhc_1 { + status = "ok"; + + vdd-supply = <&L24B>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L19B>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-current-level = <0 325000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; +}; + +&sdhc_2 { + status = "ok"; + + vdd-supply = <&L9E>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&L6E>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 22000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + cd-gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; +}; + +&usb0 { + usb-role-switch; + extcon = <&eud>; + + dwc3@a600000 { + usb-role-switch; + dr_mode = "otg"; + }; + + port { + usb_port0: endpoint { + remote-endpoint = <&usb_port0_connector>; + }; + }; +}; + +&ucsi { + connector { + port { + usb_port0_connector: endpoint { + remote-endpoint = <&usb_port0>; + }; + }; + }; +}; diff --git a/qcom/parrot-coresight.dtsi b/qcom/parrot-coresight.dtsi new file mode 100644 index 00000000..c9ced5f5 --- /dev/null +++ b/qcom/parrot-coresight.dtsi @@ -0,0 +1,3877 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + audio_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-audio-etm0"; + qcom,inst-id = <5>; + atid = <40>; + + out-ports { + port { + audio_etm0_out_funnel_lpass_lpi: endpoint { + remote-endpoint = + <&funnel_lpass_lpi_in_audio_etm0>; + }; + }; + }; + }; + + tpdm_lpass_lpi: tpdm_lpass_lpi { + compatible = "arm,coresight-dummy-source"; + coresight-name = "coresight-tpdm-lpass-lpi"; + qcom,dummy-source; + + atid = <26>; + + out-ports { + port { + tpdm_lpass_lpi_out_funnel_lpass_lpi: endpoint { + remote-endpoint = + <&funnel_lpass_lpi_in_tpdm_lpass_lpi>; + }; + }; + }; + }; + + tpdm_lpass: tpdm@10844000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10844000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-lpass"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <74>; + out-ports { + port { + tpdm_lpass_out_funnel_lpass: endpoint { + remote-endpoint = + <&funnel_lpass_in_tpdm_lpass>; + }; + }; + }; + }; + + tpdm_dl_lpass: tpdm@10c38000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c38000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-dl-lpass"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <74>; + out-ports { + port { + tpdm_dl_lpass_out_tpda_dl_lpass_10: endpoint { + remote-endpoint = + <&tpda_dl_lpass_10_in_tpdm_dl_lpass>; + }; + }; + }; + }; + + lpass_stm: lpass_stm { + compatible = "arm,coresight-dummy-source"; + coresight-name = "coresight-lpass-stm"; + qcom,dummy-source; + + atid = <25>; + + out-ports { + port { + lpass_stm_out_funnel_lpass_lpi: endpoint { + remote-endpoint = + <&funnel_lpass_lpi_in_lpass_stm>; + }; + }; + }; + }; + + tpdm_swao_prio_0: tpdm@10b09000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10b09000 0x1000>; + reg-names = "tpdm-base"; + + atid = <71>; + coresight-name = "coresight-tpdm-swao-prio-0"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_swao_prio_0_out_tpda_aoss_0: endpoint { + remote-endpoint = + <&tpda_aoss_0_in_tpdm_swao_prio_0>; + }; + }; + }; + }; + + tpdm_swao_prio_1: tpdm@10b0a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10b0a000 0x1000>; + reg-names = "tpdm-base"; + + atid = <71>; + coresight-name = "coresight-tpdm-swao-prio-1"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_swao_prio_1_out_tpda_aoss_1: endpoint { + remote-endpoint = + <&tpda_aoss_1_in_tpdm_swao_prio_1>; + }; + }; + }; + }; + + tpdm_swao_prio_2: tpdm@10b0b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10b0b000 0x1000>; + reg-names = "tpdm-base"; + + atid = <71>; + coresight-name = "coresight-tpdm-swao-prio-2"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_swao_prio_2_out_tpda_aoss_2: endpoint { + remote-endpoint = + <&tpda_aoss_2_in_tpdm_swao_prio_2>; + }; + }; + }; + }; + + tpdm_swao_prio_3: tpdm@10b0c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10b0c000 0x1000>; + reg-names = "tpdm-base"; + + atid = <71>; + coresight-name = "coresight-tpdm-swao-prio-3"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_swao_prio_3_out_tpda_aoss_3: endpoint { + remote-endpoint = + <&tpda_aoss_3_in_tpdm_swao_prio_3>; + }; + }; + }; + }; + + tpdm_swao_1: tpdm@10b0d000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10b0d000 0x1000>; + reg-names = "tpdm-base"; + + atid = <71>; + coresight-name = "coresight-tpdm-swao"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_swao_out_tpda_aoss_4: endpoint { + remote-endpoint = + <&tpda_aoss_4_in_tpdm_swao>; + }; + }; + }; + }; + + tpdm_ddr_ch01: tpdm@10d20000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10d20000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-ddr-ch01"; + + atid = <78>; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_ddr_ch01_out_funnel_ddr_ch01: endpoint { + remote-endpoint = + <&funnel_ddr_ch01_in_tpdm_ddr_ch01>; + }; + }; + }; + }; + + tpdm_ddr: tpdm@10d00000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10d00000 0x1000>; + reg-names = "tpdm-base"; + + atid = <78>; + coresight-name = "coresight-tpdm-ddr"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_ddr_dl0_out_funnel_ddr_dl0: endpoint { + remote-endpoint = + <&funnel_ddr_dl0_in_tpdm_ddr_dl0>; + }; + }; + }; + }; + + tpdm_shrm: tpdm@10d01000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10d01000 0x1000>; + reg-names = "tpdm-base"; + + atid = <78>; + coresight-name = "coresight-tpdm-shrm"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,cmb-msr-skip; + out-ports { + port { + tpdm_shrm_out_funnel_ddr_dl0: endpoint { + remote-endpoint = + <&funnel_ddr_dl0_in_tpdm_shrm>; + }; + }; + }; + }; + + tpdm_turing: tpdm@10980000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10980000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-turing"; + + atid = <78>; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_turing_out_funnel_turing: endpoint { + remote-endpoint = + <&funnel_turing_in_tpdm_turing>; + }; + }; + }; + }; + + tpdm_turing_llm: tpdm_turing_llm { + compatible = "arm,coresight-dummy-source"; + coresight-name = "coresight-tpdm-turing-llm"; + qcom,dummy-source; + + atid = <78>; + + out-ports { + port { + tpdm_turing_llm_out_funnel_turing: endpoint { + remote-endpoint = + <&funnel_turing_in_tpdm_turing_llm>; + }; + }; + }; + }; + + tpdm_gpu: tpdm@10900000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10900000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-gpu"; + + atid = <79>; + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_gpu_out_funnel_gfx_dl: endpoint { + remote-endpoint = + <&funnel_gfx_dl_in_tpdm_gpu>; + }; + }; + }; + }; + + tpdm_prng: tpdm@10841000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10841000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-prng"; + + atid = <78>; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_prng_out_tpda_dl_center_19: endpoint { + remote-endpoint = + <&tpda_dl_center_19_in_tpdm_prng>; + }; + }; + }; + }; + + tpdm_qm: tpdm@109d0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x109d0000 0x1000>; + reg-names = "tpdm-base"; + + atid = <78>; + coresight-name = "coresight-tpdm-qm"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_qm_out_tpda_dl_center_20: endpoint { + remote-endpoint = + <&tpda_dl_center_20_in_tpdm_qm>; + }; + }; + }; + }; + + tpdm_gcc: tpdm@1082c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x1082c000 0x1000>; + reg-names = "tpdm-base"; + + atid = <78>; + coresight-name = "coresight-tpdm-gcc"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_gcc_out_tpda_dl_center_21: endpoint { + remote-endpoint = + <&tpda_dl_center_21_in_tpdm_gcc>; + }; + }; + }; + }; + + tpdm_vsense: tpdm@10840000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10840000 0x1000>; + reg-names = "tpdm-base"; + + atid = <78>; + coresight-name = "coresight-tpdm-vsense"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_vsense_out_tpda_dl_center_22: endpoint { + remote-endpoint = + <&tpda_dl_center_22_in_tpdm_vsense>; + }; + }; + }; + }; + + tpdm_emmc: tpdm@10c23000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c23000 0x1000>; + reg-names = "tpdm-base"; + + atid = <78>; + coresight-name = "coresight-tpdm-emmc"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_sdcc_out_tpda_dl_center_23: endpoint { + remote-endpoint = + <&tpda_dl_center_23_in_tpdm_sdcc>; + }; + }; + }; + }; + + tpdm_sdcc: tpdm@10c20000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c20000 0x1000>; + reg-names = "tpdm-base"; + + atid = <78>; + coresight-name = "coresight-tpdm-sdcc"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,cmb-msr-skip; + + out-ports { + port { + tpdm_sdcc2_out_tpda_dl_lpass_0: endpoint { + remote-endpoint = + <&tpda_dl_lpass_0_in_tpdm_sdcc2>; + }; + }; + }; + }; + + tpdm_ipa: tpdm@10c22000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c22000 0x1000>; + reg-names = "tpdm-base"; + + atid = <78>; + coresight-name = "coresight-tpdm-ipa"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,cmb-msr-skip; + + out-ports { + port { + tpdm_ipa_out_tpda_dl_center_24: endpoint { + remote-endpoint = + <&tpda_dl_center_24_in_tpdm_ipa>; + }; + }; + }; + }; + + tpdm_pimem: tpdm@10850000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10850000 0x1000>; + reg-names = "tpdm-base"; + + atid = <78>; + coresight-name = "coresight-tpdm-pimem"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_pimem_out_tpda_dl_center_25: endpoint { + remote-endpoint = + <&tpda_dl_center_25_in_tpdm_pimem>; + }; + }; + }; + }; + + tpdm_dlct: tpdm@10c28000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c28000 0x1000>; + reg-names = "tpdm-base"; + + atid = <78>; + coresight-name = "coresight-tpdm-dlct"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_dlct_out_tpda_dl_center_26: endpoint { + remote-endpoint = + <&tpda_dl_center_26_in_tpdm_dlct>; + }; + }; + }; + }; + + tpdm_ipcc: tpdm@10c29000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c29000 0x1000>; + reg-names = "tpdm-base"; + + atid = <78>; + coresight-name = "coresight-tpdm-ipcc"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_ipcc_out_tpda_dl_center_27: endpoint { + remote-endpoint = + <&tpda_dl_center_27_in_tpdm_ipcc>; + }; + }; + }; + }; + + snoc: snoc { + compatible = "arm,coresight-dummy-source"; + coresight-name = "coresight-snoc"; + qcom,dummy-source; + + atid = <125>; + out-ports { + port { + snoc_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_snoc>; + }; + }; + }; + }; + + tpdm_spdm: tpdm@1000f000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x1000f000 0x1000>; + reg-names = "tpdm-base"; + + atid = <65>; + coresight-name = "coresight-tpdm-spdm"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_spdm_out_tpda_qdss_1: endpoint { + remote-endpoint = + <&tpda_qdss_1_in_tpdm_spdm>; + }; + }; + }; + }; + + stm: stm@10002000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb962>; + reg = <0x10002000 0x1000>, + <0x16280000 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + atid = <16>; + coresight-name = "coresight-stm"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + stm_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_stm>; + }; + }; + }; + }; + + tpdm_dcc: tpdm@10003000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10003000 0x1000>; + reg-names = "tpdm-base"; + + atid = <65>; + coresight-name = "coresight-tpdm-dcc"; + + qcom,hw-enable-check; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_dcc_out_tpda_qdss_0: endpoint { + remote-endpoint = + <&tpda_qdss_0_in_tpdm_dcc>; + }; + }; + }; + }; + + turing_etm0: turing_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-turing-etm0"; + qcom,inst-id = <13>; + + atid = <38 39>; + + out-ports { + port { + turing_etm0_out_funnel_turing_dup: endpoint { + remote-endpoint = + <&funnel_turing_dup_in_turing_etm0>; + }; + }; + }; + }; + + tpdm_east: tpdm@10c24000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c24000 0x1000>; + reg-names = "tpdm-base"; + + atid = <78>; + coresight-name = "coresight-tpdm-east"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_east_out_tpda_dl_center_19: endpoint { + remote-endpoint = + <&tpda_dl_center_19_in_tpdm_east>; + }; + }; + }; + }; + + tpdm_dl_center2_dsb: tpdm@10ac0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10ac0000 0x1000>; + reg-names = "tpdm-base"; + + atid = <79>; + coresight-name = "coresight-tpdm-dlct2-dsb"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_dlct0_out_tpda_dl_center2_26: endpoint { + remote-endpoint = + <&tpda_dl_center2_26_in_tpdm_dlct0>; + }; + }; + }; + }; + + tpdm_dl_center2_cmb: tpdm@10ac1000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10ac1000 0x1000>; + reg-names = "tpdm-base"; + + atid = <79>; + coresight-name = "coresight-tpdm-dlct2-cmb"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,cmb-msr-skip; + status = "disabled"; + out-ports { + port { + tpdm_dlct1_out_tpda_dl_center2_27: endpoint { + remote-endpoint = + <&tpda_dl_center2_27_in_tpdm_dlct1>; + }; + }; + }; + }; + + tpdm_dl_south0: tpdm@109c0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x109c0000 0x1000>; + reg-names = "tpdm-base"; + + atid = <79>; + coresight-name = "coresight-tpdm-dl-south-dsb"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,cmb-msr-skip; + + out-ports { + port { + tpdm_dl_south0_out_funnel_dl_south: endpoint { + remote-endpoint = + <&funnel_dl_south_in_tpdm_dl_south0>; + }; + }; + }; + }; + + tpdm_dl_south1: tpdm@109c1000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x109c1000 0x1000>; + reg-names = "tpdm-base"; + + atid = <79>; + coresight-name = "coresight-tpdm-dl-south-cmb"; + + clocks = <&aoss_qmp>; + status = "disabled"; + clock-names = "apb_pclk"; + qcom,cmb-msr-skip; + + out-ports { + port { + tpdm_dl_south1_out_funnel_dl_south: endpoint { + remote-endpoint = + <&funnel_dl_south_in_tpdm_dl_south1>; + }; + }; + }; + }; + + tpdm_rdpm: tpdm@10c00000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c00000 0x1000>; + reg-names = "tpdm-base"; + + atid = <79>; + coresight-name = "coresight-tpdm-rdpm"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,cmb-msr-skip; + status = "disabled"; + out-ports { + port { + tpdm_rdpm_out_funnel_dl_center_1: endpoint { + remote-endpoint = + <&funnel_dl_center_1_in_tpdm_rdpm>; + }; + }; + }; + }; + + tpdm_rdpm_mx: tpdm@10c01000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c01000 0x1000>; + reg-names = "tpdm-base"; + + atid = <79>; + coresight-name = "coresight-tpdm-rdpm-mx"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,cmb-msr-skip; + status = "disabled"; + out-ports { + port { + tpdm_rdpm_mx_out_funnel_dl_center_1: endpoint { + remote-endpoint = + <&funnel_dl_center_1_in_tpdm_rdpm_mx>; + }; + }; + }; + }; + + tpdm_llm_silver: tpdm@128a0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x128a0000 0x1000>; + reg-names = "tpdm-base"; + + atid = <66>; + coresight-name = "coresight-tpdm-llm-silver"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_llm_silver_out_tpda_apss_0: endpoint { + remote-endpoint = + <&tpda_apss_0_in_tpdm_llm_silver>; + }; + }; + }; + }; + + tpdm_llm_gold: tpdm@138b0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x128b0000 0x1000>; + reg-names = "tpdm-base"; + + atid = <66>; + coresight-name = "coresight-tpdm-llm-gold"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_llm_gold_out_tpda_apss_1: endpoint { + remote-endpoint = + <&tpda_apss_1_in_tpdm_llm_gold>; + }; + }; + }; + }; + + + tpdm_actpm: tpdm@12860000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x12860000 0x1000>; + reg-names = "tpdm-base"; + + atid = <66>; + coresight-name = "coresight-tpdm-actpm"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_apss0_out_tpda_apss_3: endpoint { + remote-endpoint = + <&tpda_apss_3_in_tpdm_apss0>; + }; + }; + }; + }; + + tpdm_apss: tpdm@12861000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x12861000 0x1000>; + reg-names = "tpdm-base"; + + atid = <66>; + coresight-name = "coresight-tpdm-apss"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_apps1_out_tpda_apss_4: endpoint { + remote-endpoint = + <&tpda_apss_4_in_tpdm_apps1>; + }; + }; + }; + }; + + tpdm_modem_0: tpdm@10800000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10800000 0x1000>; + reg-names = "tpdm-base"; + + atid = <67>; + coresight-name = "coresight-tpdm-modem-0"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_modem_0_out_tpda_modem_0: endpoint { + remote-endpoint = + <&tpda_modem_0_in_tpdm_modem_0>; + }; + }; + }; + }; + + tpdm_modem_1: tpdm@10801000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10801000 0x1000>; + reg-names = "tpdm-base"; + + atid = <67>; + coresight-name = "coresight-tpdm-modem-1"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,cmb-msr-skip; + + out-ports { + port { + tpdm_modem_1_out_tpda_modem_1: endpoint { + remote-endpoint = + <&tpda_modem_1_in_tpdm_modem_1>; + }; + }; + }; + }; + + modem_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-modem-etm0"; + qcom,inst-id = <2>; + + atid = <36 37>; + out-ports { + port { + modem_etm0_out_funnel_modem_q6_dup: endpoint { + remote-endpoint = + <&funnel_modem_q6_dup_in_modem_etm0>; + }; + }; + }; + }; + + modem2_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-modem2-etm0"; + qcom,inst-id = <11>; + + atid = <39>; + out-ports { + port { + modem2_etm0_out_funnel_modem: endpoint { + remote-endpoint = + <&funnel_modem_in_modem2_etm0>; + }; + }; + }; + }; + + modem_diag: modem_diag { + compatible = "arm,coresight-dummy-source"; + coresight-name = "coresight-modem-diag"; + qcom,dummy-source; + + atid = <50>; + out-ports { + port { + modem_diag_out_funnel_modem_q6: endpoint { + remote-endpoint = + <&funnel_modem_q6_in_modem_diag>; + }; + }; + }; + }; + + tpdm_wcss: tpdm@109A4000 { + compatible = "arm,coresight-dummy-source"; + qcom,dummy-source; + + atid = <67>; + coresight-name = "coresight-tpdm-wcss"; + + out-ports { + port { + tpdm_wcss_out_funnel_dl_south: endpoint { + remote-endpoint = + <&funnel_dl_south_in_tpdm_wcss>; + }; + }; + }; + }; + + tpdm_tmess_prng: tpdm@10cc9000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10cc9000 0x1000>; + reg-names = "tpdm-base"; + + atid = <85>; + coresight-name = "coresight-tpdm-tmess-prng"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + tpdm_tmess_prng_out_tpda_tmess_0: endpoint { + remote-endpoint = + <&tpda_tmess_0_in_tpdm_tmess_prng>; + }; + }; + }; + }; + + tpdm_tmess_0: tpdm@10cc0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10cc0000 0x1000>; + reg-names = "tpdm-base"; + + atid = <85>; + coresight-name = "coresight-tpdm-tmess-irq"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + tpdm_tmess_0_out_tpda_tmess_1: endpoint { + remote-endpoint = + <&tpda_tmess_1_in_tpdm_tmess_0>; + }; + }; + }; + }; + + tpdm_tmess_1: tpdm@10cc1000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10cc1000 0x1000>; + reg-names = "tpdm-base"; + + atid = <85>; + coresight-name = "coresight-tpdm-tmess-dsb"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + tpdm_tmess_1_out_tpda_tmess_2: endpoint { + remote-endpoint = + <&tpda_tmess_2_in_tpdm_tmess_1>; + }; + }; + }; + }; + + tpdm_wpss: tpdm@10c70000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c70000 0x1000>; + reg-names = "tpdm-base"; + + atid = <78>; + coresight-name = "coresight-tpdm-wpss-dsb"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_wpss_out_funnel_wpss: endpoint { + remote-endpoint = + <&funnel_wpss_in_tpdm_wpss>; + }; + }; + }; + }; + + tpdm_wpss1: tpdm@10c71000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c71000 0x1000>; + reg-names = "tpdm-base"; + + atid = <78>; + coresight-name = "coresight-tpdm-wpss-cmb"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_wpss_1_out_funnel_wpss: endpoint { + remote-endpoint = + <&funnel_wpss_in_tpdm_wpss_1>; + }; + }; + }; + }; + + wpss_etm: wpss_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-wpss-etm0"; + qcom,inst-id = <3>; + atid = <44>; + + out-ports { + port { + wpss_etm0_out_funnel_wpss: endpoint { + remote-endpoint = + <&funnel_wpss_in_wpss_etm0>; + }; + }; + }; + }; + + funnel_wpss: funnel@10c73000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10c73000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-wpss"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_wpss_in_tpdm_wpss: endpoint { + remote-endpoint = + <&tpdm_wpss_out_funnel_wpss>; + }; + }; + + port@1 { + reg = <1>; + funnel_wpss_in_tpdm_wpss_1: endpoint { + remote-endpoint = + <&tpdm_wpss_1_out_funnel_wpss>; + }; + }; + + port@2 { + reg = <2>; + funnel_wpss_in_wpss_etm0: endpoint { + remote-endpoint = + <&wpss_etm0_out_funnel_wpss>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_wpss_out_tpda_dl_center_5: endpoint { + remote-endpoint = + <&tpda_dl_center_5_in_funnel_wpss>; + source = <&tpdm_wpss>; + }; + }; + + port@1 { + reg = <1>; + funnel_wpss_out_tpda_dl_center_6: endpoint { + remote-endpoint = + <&tpda_dl_center_6_in_funnel_wpss>; + source = <&tpdm_wpss1>; + }; + }; + + port@2 { + reg = <2>; + funnel_wpss_out_funnel_dl_center: endpoint { + remote-endpoint = + <&funnel_dl_center_in_funnel_wpss>; + source = <&wpss_etm>; + }; + }; + + }; + }; + + funnel_lpass_lpi: funnel@10b44000 { + compatible = "arm,coresight-static-funnel"; + coresight-name = "coresight-funnel-lpass_lpi"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_lpass_lpi_in_audio_etm0: endpoint { + remote-endpoint = + <&audio_etm0_out_funnel_lpass_lpi>; + }; + }; + + port@1 { + reg = <1>; + funnel_lpass_lpi_in_lpass_stm: endpoint { + remote-endpoint = + <&lpass_stm_out_funnel_lpass_lpi>; + }; + }; + + port@5 { + reg = <5>; + funnel_lpass_lpi_in_tpdm_lpass_lpi: endpoint { + remote-endpoint = + <&tpdm_lpass_lpi_out_funnel_lpass_lpi>; + }; + }; + + }; + + out-ports { + port { + funnel_lpass_lpi_out_funnel_aoss: endpoint { + remote-endpoint = + <&funnel_aoss_in_funnel_lpass_lpi>; + }; + }; + + }; + }; + + funnel_gfx_dl: funnel@10902000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10902000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-gfx_dl"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + funnel_gfx_dl_in_tpdm_gpu: endpoint { + remote-endpoint = + <&tpdm_gpu_out_funnel_gfx_dl>; + }; + }; + + }; + + out-ports { + port { + funnel_gfx_out_tpda_dl_center2_17: endpoint { + remote-endpoint = + <&tpda_dl_center2_17_in_funnel_gfx>; + }; + }; + + }; + }; + + + funnel_lpass: funnel@10846000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10846000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-lpass"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + funnel_lpass_in_tpdm_lpass: endpoint { + remote-endpoint = + <&tpdm_lpass_out_funnel_lpass>; + }; + }; + + }; + + out-ports { + port { + funnel_lpass_out_tpda_dl_lpass_2: endpoint { + remote-endpoint = + <&tpda_dl_lpass_2_in_funnel_lpass>; + }; + }; + + }; + }; + + funnel_ddr_ch01: funnel@10d22000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10d22000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-ddr_ch01"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + funnel_ddr_ch01_in_tpdm_ddr_ch01: endpoint { + remote-endpoint = + <&tpdm_ddr_ch01_out_funnel_ddr_ch01>; + }; + }; + + }; + + out-ports { + port { + funnel_ddr_ch01_out_funnel_ddr_dl0: endpoint { + remote-endpoint = + <&funnel_ddr_dl0_in_funnel_ddr_ch01>; + }; + }; + + }; + }; + + funnel_ddr_dl0: funnel@10d03000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10d03000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-ddr_dl0"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_ddr_dl0_in_funnel_ddr_ch01: endpoint { + remote-endpoint = + <&funnel_ddr_ch01_out_funnel_ddr_dl0>; + }; + }; + + port@2 { + reg = <2>; + funnel_ddr_dl0_in_tpdm_ddr_dl0: endpoint { + remote-endpoint = + <&tpdm_ddr_dl0_out_funnel_ddr_dl0>; + }; + }; + + port@3 { + reg = <3>; + funnel_ddr_dl0_in_tpdm_shrm: endpoint { + remote-endpoint = + <&tpdm_shrm_out_funnel_ddr_dl0>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_ddr_out_tpda_dl_center_9: endpoint { + remote-endpoint = + <&tpda_dl_center_9_in_funnel_ddr>; + source = <&tpdm_ddr_ch01>; + }; + }; + + port@1 { + reg = <1>; + funnel_ddr_out_tpda_dl_center_11: endpoint { + remote-endpoint = + <&tpda_dl_center_11_in_funnel_ddr>; + source = <&tpdm_ddr>; + }; + }; + + port@2 { + reg = <2>; + funnel_ddr_out_tpda_dl_center_12: endpoint { + remote-endpoint = + <&tpda_dl_center_12_in_funnel_ddr>; + source = <&tpdm_shrm>; + }; + }; + + }; + }; + + funnel_turing_dup: funnel@10984000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10984000 0x1000>, + <0x10983000 0x1000>; + reg-names = "funnel-base-dummy", "funnel-base-real"; + + coresight-name = "coresight-funnel-turing_dup"; + + qcom,duplicate-funnel; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@3 { + reg = <3>; + funnel_turing_dup_in_turing_etm0: endpoint { + remote-endpoint = + <&turing_etm0_out_funnel_turing_dup>; + }; + }; + + }; + + out-ports { + port { + funnel_turing_dup_out_funnel_turing: endpoint { + remote-endpoint = + <&funnel_turing_in_funnel_turing_dup>; + }; + }; + + }; + }; + + funnel_turing: funnel@10983000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10983000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-turing"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_turing_in_tpdm_turing: endpoint { + remote-endpoint = + <&tpdm_turing_out_funnel_turing>; + }; + }; + + port@1 { + reg = <1>; + funnel_turing_in_tpdm_turing_llm: endpoint { + remote-endpoint = + <&tpdm_turing_llm_out_funnel_turing>; + }; + }; + + port@4 { + reg = <4>; + funnel_turing_in_funnel_turing_dup: endpoint { + remote-endpoint = + <&funnel_turing_dup_out_funnel_turing>; + }; + }; + + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_turing_out_tpda_dl_center_15: endpoint { + remote-endpoint = + <&tpda_dl_center_15_in_funnel_turing>; + source = <&tpdm_turing>; + }; + }; + + port@1 { + reg = <1>; + funnel_turing_out_tpda_dl_center_16: endpoint { + remote-endpoint = + <&tpda_dl_center_16_in_funnel_turing>; + source = <&tpdm_turing_llm>; + }; + }; + + port@2 { + reg = <2>; + funnel_turing_out_funnel_dl_center: endpoint { + remote-endpoint = + <&funnel_dl_center_in_funnel_turing>; + }; + }; + + }; + }; + + funnel_dlct_1: funnel@10c02000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10c02000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-dlct1"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + funnel_dl_center_1_in_tpdm_rdpm: endpoint { + remote-endpoint = + <&tpdm_rdpm_out_funnel_dl_center_1>; + }; + }; + + port@2 { + reg = <2>; + funnel_dl_center_1_in_tpdm_rdpm_mx: endpoint { + remote-endpoint = + <&tpdm_rdpm_mx_out_funnel_dl_center_1>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_dl_center_1_out_tpda_dl_center_10: endpoint { + remote-endpoint = + <&tpda_dl_center_10_in_funnel_dl_center_1>; + source = <&tpdm_rdpm>; + }; + }; + + port@1 { + reg = <1>; + funnel_dl_center_1_out_tpda_dl_center_11: endpoint { + remote-endpoint = + <&tpda_dl_center_11_in_funnel_dl_center_1>; + source = <&tpdm_rdpm_mx>; + }; + }; + }; + }; + + tpda_tmess: tpda@10cc4000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + + reg = <0x10cc4000 0x1000>; + reg-names = "tpda-base"; + + qcom,cmb-elem-size = <0 64>, + <1 64>, + <2 32>; + qcom,dsb-elem-size = <1 32>; + + qcom,tpda-atid = <85>; + coresight-name = "coresight-tpda-tmess"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_tmess_0_in_tpdm_tmess_prng: endpoint { + remote-endpoint = + <&tpdm_tmess_prng_out_tpda_tmess_0>; + }; + }; + + port@1 { + reg = <1>; + tpda_tmess_1_in_tpdm_tmess_0: endpoint { + remote-endpoint = + <&tpdm_tmess_0_out_tpda_tmess_1>; + }; + }; + + port@2 { + reg = <2>; + tpda_tmess_2_in_tpdm_tmess_1: endpoint { + remote-endpoint = + <&tpdm_tmess_1_out_tpda_tmess_2>; + }; + }; + + }; + + out-ports { + + port { + tpda_tmess_out_funnel_tmess: endpoint { + remote-endpoint = + <&funnel_tmess_in_tpda_tmess>; + }; + }; + + }; + }; + + funnel_tmess: funnel@10cc5000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10cc5000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-tmess"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + funnel_tmess_in_tpda_tmess: endpoint { + remote-endpoint = + <&tpda_tmess_out_funnel_tmess>; + }; + }; + + }; + + out-ports { + port { + funnel_tmess_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_funnel_tmess>; + }; + }; + + }; + }; + + tpda_modem: tpda@10803000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + + reg = <0x10803000 0x1000>; + reg-names = "tpda-base"; + + qcom,tpda-atid = <67>; + qcom,dsb-elem-size = <0 32>; + qcom,cmb-elem-size = <0 64>; + + coresight-name = "coresight-tpda-modem"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_modem_0_in_tpdm_modem_0: endpoint { + remote-endpoint = + <&tpdm_modem_0_out_tpda_modem_0>; + }; + }; + + port@1 { + reg = <1>; + tpda_modem_1_in_tpdm_modem_1: endpoint { + remote-endpoint = + <&tpdm_modem_1_out_tpda_modem_1>; + }; + }; + + }; + + out-ports { + + port { + tpda_modem_out_funnel_modem: endpoint { + remote-endpoint = + <&funnel_modem_in_tpda_modem>; + }; + }; + + }; + }; + + funnel_modem_q6_dup: funnel@1080d000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x1080d000 0x1000>, + <0x1080c000 0x1000>; + reg-names = "funnel-base-dummy", "funnel-base-real"; + + coresight-name = "coresight-funnel-modem_q6_dup"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,duplicate-funnel; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_modem_q6_dup_in_modem_etm0: endpoint { + remote-endpoint = + <&modem_etm0_out_funnel_modem_q6_dup>; + }; + }; + + }; + + out-ports { + port { + funnel_modem_q6_dup_out_funnel_modem_q6: endpoint { + remote-endpoint = + <&funnel_modem_q6_in_funnel_modem_q6_dup>; + }; + }; + + }; + }; + + funnel_modem_q6: funnel@1080c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x1080c000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-modem_q6"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + funnel_modem_q6_in_funnel_modem_q6_dup: endpoint { + remote-endpoint = + <&funnel_modem_q6_dup_out_funnel_modem_q6>; + }; + }; + + port@2 { + reg = <2>; + funnel_modem_q6_in_modem_diag: endpoint { + remote-endpoint = + <&modem_diag_out_funnel_modem_q6>; + }; + }; + + }; + + out-ports { + port { + funnel_modem_q6_out_funnel_modem: endpoint { + remote-endpoint = + <&funnel_modem_in_funnel_modem_q6>; + }; + }; + + }; + }; + + funnel_modem: funnel@10804000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10804000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-modem"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + funnel_modem_in_modem2_etm0: endpoint { + remote-endpoint = + <&modem2_etm0_out_funnel_modem>; + }; + }; + + port@0 { + reg = <0>; + funnel_modem_in_tpda_modem: endpoint { + remote-endpoint = + <&tpda_modem_out_funnel_modem>; + }; + }; + + port@3 { + reg = <3>; + funnel_modem_in_funnel_modem_q6: endpoint { + remote-endpoint = + <&funnel_modem_q6_out_funnel_modem>; + }; + }; + + }; + + out-ports { + port { + funnel_modem_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_funnel_modem>; + }; + }; + + }; + }; + + tpda_apss: tpda@12863000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + + reg = <0x12863000 0x1000>; + reg-names = "tpda-base"; + + qcom,tpda-atid = <66>; + qcom,dsb-elem-size = <4 32>; + qcom,cmb-elem-size = <0 32>, + <1 32>, + <3 64>; + + coresight-name = "coresight-tpda-apss"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_apss_0_in_tpdm_llm_silver: endpoint { + remote-endpoint = + <&tpdm_llm_silver_out_tpda_apss_0>; + }; + }; + + port@1 { + reg = <1>; + tpda_apss_1_in_tpdm_llm_gold: endpoint { + remote-endpoint = + <&tpdm_llm_gold_out_tpda_apss_1>; + }; + }; + + port@3 { + reg = <3>; + tpda_apss_3_in_tpdm_apss0: endpoint { + remote-endpoint = + <&tpdm_apss0_out_tpda_apss_3>; + }; + }; + + port@4 { + reg = <4>; + tpda_apss_4_in_tpdm_apps1: endpoint { + remote-endpoint = + <&tpdm_apps1_out_tpda_apss_4>; + }; + }; + + }; + + out-ports { + port { + tpda_apss_out_funnel_apss: endpoint { + remote-endpoint = + <&funnel_apss_in_tpda_apss>; + }; + }; + + }; + }; + + funnel_apss: funnel@12810000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x12810000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-apss"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_apss_in_funnel_ete: endpoint { + remote-endpoint = + <&funnel_ete_out_funnel_apss>; + }; + }; + + port@3 { + reg = <3>; + funnel_apss_in_tpda_apss: endpoint { + remote-endpoint = + <&tpda_apss_out_funnel_apss>; + }; + }; + + }; + + out-ports { + port { + funnel_apss_out_funnel_dl_center: endpoint { + remote-endpoint = + <&funnel_dl_center_in_funnel_apss>; + }; + }; + + }; + }; + + tpda_dl_center: tpda@10c2b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + + reg = <0x10c2b000 0x1000>; + reg-names = "tpda-base"; + + qcom,tpda-atid = <78>; + + qcom,dsb-elem-size = <5 32>, + <9 32>, + <11 32>, + <15 32>, + <20 32>, + <21 32>, + <25 32>, + <26 32>; + + qcom,cmb-elem-size = <6 32>, + <11 32>, + <12 64>, + <16 32>, + <19 64>, + <22 32>, + <23 32>, + <24 64>, + <25 64>, + <27 64>; + + coresight-name = "coresight-tpda-dlct0"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@5 { + reg = <5>; + tpda_dl_center_5_in_funnel_wpss: endpoint { + remote-endpoint = + <&funnel_wpss_out_tpda_dl_center_5>; + }; + }; + + port@6 { + reg = <6>; + tpda_dl_center_6_in_funnel_wpss: endpoint { + remote-endpoint = + <&funnel_wpss_out_tpda_dl_center_6>; + }; + }; + + port@9 { + reg = <9>; + tpda_dl_center_9_in_funnel_ddr: endpoint { + remote-endpoint = + <&funnel_ddr_out_tpda_dl_center_9>; + }; + }; + + port@c { + reg = <11>; + tpda_dl_center_11_in_funnel_ddr: endpoint { + remote-endpoint = + <&funnel_ddr_out_tpda_dl_center_11>; + }; + }; + + port@d { + reg = <12>; + tpda_dl_center_12_in_funnel_ddr: endpoint { + remote-endpoint = + <&funnel_ddr_out_tpda_dl_center_12>; + }; + }; + + port@f { + reg = <15>; + tpda_dl_center_15_in_funnel_turing: endpoint { + remote-endpoint = + <&funnel_turing_out_tpda_dl_center_15>; + }; + }; + + port@10 { + reg = <16>; + tpda_dl_center_16_in_funnel_turing: endpoint { + remote-endpoint = + <&funnel_turing_out_tpda_dl_center_16>; + }; + }; + + port@13 { + reg = <19>; + tpda_dl_center_19_in_tpdm_prng: endpoint { + remote-endpoint = + <&tpdm_prng_out_tpda_dl_center_19>; + }; + }; + + port@14 { + reg = <20>; + tpda_dl_center_20_in_tpdm_qm: endpoint { + remote-endpoint = + <&tpdm_qm_out_tpda_dl_center_20>; + }; + }; + + port@15 { + reg = <21>; + tpda_dl_center_21_in_tpdm_gcc: endpoint { + remote-endpoint = + <&tpdm_gcc_out_tpda_dl_center_21>; + }; + }; + + port@16 { + reg = <22>; + tpda_dl_center_22_in_tpdm_vsense: endpoint { + remote-endpoint = + <&tpdm_vsense_out_tpda_dl_center_22>; + }; + }; + + port@17 { + reg = <23>; + tpda_dl_center_23_in_tpdm_sdcc: endpoint { + remote-endpoint = + <&tpdm_sdcc_out_tpda_dl_center_23>; + }; + }; + + port@18 { + reg = <24>; + tpda_dl_center_24_in_tpdm_ipa: endpoint { + remote-endpoint = + <&tpdm_ipa_out_tpda_dl_center_24>; + }; + }; + + port@19 { + reg = <25>; + tpda_dl_center_25_in_tpdm_pimem: endpoint { + remote-endpoint = + <&tpdm_pimem_out_tpda_dl_center_25>; + }; + }; + + port@1a { + reg = <26>; + tpda_dl_center_26_in_tpdm_dlct: endpoint { + remote-endpoint = + <&tpdm_dlct_out_tpda_dl_center_26>; + }; + }; + + port@1b { + reg = <27>; + tpda_dl_center_27_in_tpdm_ipcc: endpoint { + remote-endpoint = + <&tpdm_ipcc_out_tpda_dl_center_27>; + }; + }; + + }; + + out-ports { + + port { + tpda_dl_center_out_funnel_dl_center: endpoint { + remote-endpoint = + <&funnel_dl_center_in_tpda_dl_center>; + }; + }; + + }; + }; + + funnel_dlct0: funnel@10c2c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10c2c000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-dlct0"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_dl_center_in_tpda_dl_center: endpoint { + remote-endpoint = + <&tpda_dl_center_out_funnel_dl_center>; + }; + }; + + port@4 { + reg = <4>; + funnel_dl_center_in_funnel_wpss: endpoint { + remote-endpoint = + <&funnel_wpss_out_funnel_dl_center>; + }; + }; + + port@6 { + reg = <6>; + funnel_dl_center_in_funnel_turing: endpoint { + remote-endpoint = + <&funnel_turing_out_funnel_dl_center>; + }; + }; + + port@7 { + reg = <7>; + funnel_dl_center_in_funnel_apss: endpoint { + remote-endpoint = + <&funnel_apss_out_funnel_dl_center>; + }; + }; + }; + + out-ports { + port { + funnel_dl_center_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_funnel_dl_center>; + }; + }; + + }; + }; + + funnel_dl_south: funnel@109c3000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x109c3000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-dl_south"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + reg = <2>; + funnel_dl_south_in_tpdm_dl_south0: endpoint { + remote-endpoint = + <&tpdm_dl_south0_out_funnel_dl_south>; + }; + }; + + port@3 { + reg = <3>; + funnel_dl_south_in_tpdm_dl_south1: endpoint { + remote-endpoint = + <&tpdm_dl_south1_out_funnel_dl_south>; + }; + }; + + port@4 { + reg = <4>; + funnel_dl_south_in_tpdm_wcss: endpoint { + remote-endpoint = + <&tpdm_wcss_out_funnel_dl_south>; + }; + }; + + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_dl_south_out_tpda_dl_center2_7: endpoint { + remote-endpoint = + <&tpda_dl_center2_7_in_funnel_dl_south>; + source = <&tpdm_dl_south0>; + }; + }; + + port@1 { + reg = <1>; + funnel_dl_south_out_tpda_dl_center2_8: endpoint { + remote-endpoint = + <&tpda_dl_center2_8_in_funnel_dl_south>; + source = <&tpdm_dl_south1>; + }; + }; + + port@2 { + reg = <2>; + funnel_dl_south_out_funnel_dl_center2: endpoint { + remote-endpoint = + <&funnel_dl_center2_in_funnel_dl_south>; + }; + }; + }; + }; + + tpda_dl_center2: tpda@10ac3000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + + reg = <0x10ac3000 0x1000>; + reg-names = "tpda-base"; + + qcom,tpda-atid = <79>; + + qcom,dsb-elem-size = <7 32>, + <9 32>, + <17 32>, + <19 32>, + <26 32>; + + qcom,cmb-elem-size = <8 64>, + <13 64>, + <14 64>, + <27 64>; + + coresight-name = "coresight-tpda-dlct2"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@7 { + reg = <7>; + tpda_dl_center2_7_in_funnel_dl_south: endpoint { + remote-endpoint = + <&funnel_dl_south_out_tpda_dl_center2_7>; + }; + }; + + port@8 { + reg = <8>; + tpda_dl_center2_8_in_funnel_dl_south: endpoint { + remote-endpoint = + <&funnel_dl_south_out_tpda_dl_center2_8>; + }; + }; + + + port@d { + reg = <13>; + tpda_dl_center_10_in_funnel_dl_center_1: endpoint { + remote-endpoint = + <&funnel_dl_center_1_out_tpda_dl_center_10>; + }; + }; + + port@e { + reg = <14>; + tpda_dl_center_11_in_funnel_dl_center_1: endpoint { + remote-endpoint = + <&funnel_dl_center_1_out_tpda_dl_center_11>; + }; + }; + + port@11 { + reg = <17>; + tpda_dl_center2_17_in_funnel_gfx: endpoint { + remote-endpoint = + <&funnel_gfx_out_tpda_dl_center2_17>; + }; + }; + + port@13 { + reg = <19>; + tpda_dl_center_19_in_tpdm_east: endpoint { + remote-endpoint = + <&tpdm_east_out_tpda_dl_center_19>; + }; + }; + + port@1a { + reg = <26>; + tpda_dl_center2_26_in_tpdm_dlct0: endpoint { + remote-endpoint = + <&tpdm_dlct0_out_tpda_dl_center2_26>; + }; + }; + + port@1b { + reg = <27>; + tpda_dl_center2_27_in_tpdm_dlct1: endpoint { + remote-endpoint = + <&tpdm_dlct1_out_tpda_dl_center2_27>; + }; + }; + + }; + + out-ports { + + port { + tpda_dl_center2_out_funnel_dl_center2: endpoint { + remote-endpoint = + <&funnel_dl_center2_in_tpda_dl_center2>; + }; + }; + + }; + }; + + +funnel_dl_center2: funnel@10ac4000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10ac4000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-dlct2"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_dl_center2_in_tpda_dl_center2: endpoint { + remote-endpoint = + <&tpda_dl_center2_out_funnel_dl_center2>; + }; + }; + + port@4 { + reg = <4>; + funnel_dl_center2_in_funnel_dl_south: endpoint { + remote-endpoint = + <&funnel_dl_south_out_funnel_dl_center2>; + }; + }; + + }; + + out-ports { + port { + funnel_dl_center2_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_funnel_dl_center2>; + }; + }; + + }; + }; + + tpda_dl_lpass: tpda@10c3a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + + reg = <0x10c3a000 0x1000>; + reg-names = "tpda-base"; + + qcom,tpda-atid = <74>; + coresight-name = "coresight-tpda-dl-lpass"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,cmb-elem-size = <0 32>; + qcom,dsb-elem-size = <2 32>, + <10 32>; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_dl_lpass_0_in_tpdm_sdcc2: endpoint { + remote-endpoint = + <&tpdm_sdcc2_out_tpda_dl_lpass_0>; + }; + }; + + port@2 { + reg = <2>; + tpda_dl_lpass_2_in_funnel_lpass: endpoint { + remote-endpoint = + <&funnel_lpass_out_tpda_dl_lpass_2>; + }; + }; + + port@10 { + reg = <10>; + tpda_dl_lpass_10_in_tpdm_dl_lpass: endpoint { + remote-endpoint = + <&tpdm_dl_lpass_out_tpda_dl_lpass_10>; + }; + }; + + }; + + out-ports { + + port { + tpda_dl_lpass_out_funnel_dl_lpass: endpoint { + remote-endpoint = + <&funnel_dl_lpass_in_tpda_dl_lpass>; + }; + }; + + }; + }; + + funnel_dl_lpass: funnel@10c3b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10c3b000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-dl-lpass"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + + port { + funnel_dl_lpass_in_tpda_dl_lpass: endpoint { + remote-endpoint = + <&tpda_dl_lpass_out_funnel_dl_lpass>; + }; + }; + + }; + + out-ports { + port { + funnel_dl_lpass_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_funnel_dl_lpass>; + }; + }; + + }; + }; + + tpda_qdss: tpda@10004000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + + reg = <0x10004000 0x1000>; + reg-names = "tpda-base"; + + qcom,tpda-atid = <65>; + coresight-name = "coresight-tpda-qdss"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-elem-size = <0 32>, + <1 32>; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_qdss_0_in_tpdm_dcc: endpoint { + remote-endpoint = + <&tpdm_dcc_out_tpda_qdss_0>; + }; + }; + + port@1 { + reg = <1>; + tpda_qdss_1_in_tpdm_spdm: endpoint { + remote-endpoint = + <&tpdm_spdm_out_tpda_qdss_1>; + }; + }; + + + }; + + out-ports { + + port { + tpda_qdss_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_tpda_qdss>; + }; + }; + + }; + }; + + funnel_in0: funnel@10041000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10041000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in0"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_in0_in_snoc: endpoint { + remote-endpoint = + <&snoc_out_funnel_in0>; + }; + }; + + port@1 { + reg = <1>; + funnel_in0_in_funnel_tmess: endpoint { + remote-endpoint = + <&funnel_tmess_out_funnel_in0>; + }; + }; + + port@6 { + reg = <6>; + funnel_in0_in_tpda_qdss: endpoint { + remote-endpoint = + <&tpda_qdss_out_funnel_in0>; + }; + }; + + port@7 { + reg = <7>; + funnel_in0_in_stm: endpoint { + remote-endpoint = + <&stm_out_funnel_in0>; + }; + }; + }; + + out-ports { + port { + funnel_in0_out_funnel_qdss: endpoint { + remote-endpoint = + <&funnel_qdss_in_funnel_in0>; + }; + }; + + }; + }; + + funnel_in1: funnel@10042000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10042000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in1"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@4 { + reg = <4>; + funnel_in1_in_funnel_modem: endpoint { + remote-endpoint = + <&funnel_modem_out_funnel_in1>; + }; + }; + + port@5 { + reg = <5>; + funnel_in1_in_funnel_dl_lpass: endpoint { + remote-endpoint = + <&funnel_dl_lpass_out_funnel_in1>; + }; + }; + + + port@6 { + reg = <6>; + funnel_in1_in_funnel_dl_center: endpoint { + remote-endpoint = + <&funnel_dl_center_out_funnel_in1>; + }; + }; + + port@7 { + reg = <7>; + funnel_in1_in_funnel_dl_center2: endpoint { + remote-endpoint = + <&funnel_dl_center2_out_funnel_in1>; + }; + }; + + }; + + out-ports { + port { + funnel_in1_out_funnel_qdss: endpoint { + remote-endpoint = + <&funnel_qdss_in_funnel_in1>; + }; + }; + + }; + }; + + funnel_merg: funnel@10045000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10045000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-merg"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + funnel_qdss_in_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_out_funnel_qdss>; + }; + }; + + port@0 { + reg = <0>; + funnel_qdss_in_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_out_funnel_qdss>; + }; + }; + + }; + + out-ports { + port { + funnel_qdss_out_funnel_aoss: endpoint { + remote-endpoint = + <&funnel_aoss_in_funnel_qdss>; + }; + }; + + }; + }; + + tpda_aoss: tpda@10b08000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + + reg = <0x10b08000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-aoss"; + + qcom,tpda-atid = <71>; + qcom,cmb-elem-size = <0 64>, + <1 64>, + <2 64>, + <3 64>; + + qcom,dsb-elem-size = <4 32>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_aoss_0_in_tpdm_swao_prio_0: endpoint { + remote-endpoint = + <&tpdm_swao_prio_0_out_tpda_aoss_0>; + }; + }; + + port@1 { + reg = <1>; + tpda_aoss_1_in_tpdm_swao_prio_1: endpoint { + remote-endpoint = + <&tpdm_swao_prio_1_out_tpda_aoss_1>; + }; + }; + + port@2 { + reg = <2>; + tpda_aoss_2_in_tpdm_swao_prio_2: endpoint { + remote-endpoint = + <&tpdm_swao_prio_2_out_tpda_aoss_2>; + }; + }; + + port@3 { + reg = <3>; + tpda_aoss_3_in_tpdm_swao_prio_3: endpoint { + remote-endpoint = + <&tpdm_swao_prio_3_out_tpda_aoss_3>; + }; + }; + + port@4 { + reg = <4>; + tpda_aoss_4_in_tpdm_swao: endpoint { + remote-endpoint = + <&tpdm_swao_out_tpda_aoss_4>; + }; + }; + + }; + + out-ports { + + port { + tpda_aoss_out_funnel_aoss: endpoint { + remote-endpoint = + <&funnel_aoss_in_tpda_aoss>; + }; + }; + + }; + }; + + funnel_aoss: funnel@10b04000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10b04000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-aoss"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@5 { + reg = <5>; + funnel_aoss_in_funnel_lpass_lpi: endpoint { + remote-endpoint = + <&funnel_lpass_lpi_out_funnel_aoss>; + }; + }; + + port@6 { + reg = <6>; + funnel_aoss_in_tpda_aoss: endpoint { + remote-endpoint = + <&tpda_aoss_out_funnel_aoss>; + }; + }; + + port@7 { + reg = <7>; + funnel_aoss_in_funnel_qdss: endpoint { + remote-endpoint = + <&funnel_qdss_out_funnel_aoss>; + }; + }; + }; + + out-ports { + port { + funnel_aoss_out_tmc_etf: endpoint { + remote-endpoint = + <&tmc_etf_in_funnel_aoss>; + }; + }; + + }; + }; + + dummy_eud: dummy_sink { + compatible = "arm,coresight-dummy-sink"; + + coresight-name = "coresight-eud"; + + qcom,dummy-sink; + in-ports { + port { + eud_in_replicator_swao: endpoint { + remote-endpoint = + <&replicator_swao_out_eud>; + }; + }; + }; + }; + + tmc_etf: tmc@10b05000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb961>; + reg = <0x10b05000 0x1000>; + reg-names = "tmc-base"; + + coresight-name = "coresight-tmc-etf"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + tmc_etf_in_funnel_aoss: endpoint { + remote-endpoint = + <&funnel_aoss_out_tmc_etf>; + }; + }; + }; + + out-ports { + port { + tmc_etf_out_replicator_swao: endpoint { + remote-endpoint = + <&replicator_swao_in_tmc_etf>; + }; + }; + }; + }; + + replicator_swao: replicator@10b06000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + + reg = <0x10b06000 0x1000>; + reg-names = "replicator-base"; + + coresight-name = "coresight-replicator_swao"; + + qcom,replicator-loses-context; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + in-ports { + port { + replicator_swao_in_tmc_etf: endpoint { + remote-endpoint = + <&tmc_etf_out_replicator_swao>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + replicator_swao_out_replicator_qdss: endpoint { + remote-endpoint = + <&replicator_qdss_in_replicator_swao>; + }; + }; + + port@1 { + reg = <1>; + replicator_swao_out_eud: endpoint { + remote-endpoint = + <&eud_in_replicator_swao>; + }; + }; + }; + }; + + replicator_qdss: replicator@10046000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + + reg = <0x10046000 0x1000>; + reg-names = "replicator-base"; + + coresight-name = "coresight-replicator_qdss"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + in-ports { + port { + replicator_qdss_in_replicator_swao: endpoint { + remote-endpoint = + <&replicator_swao_out_replicator_qdss>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + replicator_qdss_out_replicator_etr: endpoint { + remote-endpoint = + <&replicator_etr_in_replicator_qdss>; + }; + }; + }; + }; + + replicator_etr: replicator@1004e000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + + reg = <0x1004e000 0x1000>; + reg-names = "replicator-base"; + + coresight-name = "coresight-replicator_etr"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + replicator_etr_in_replicator_qdss: endpoint { + remote-endpoint = + <&replicator_qdss_out_replicator_etr>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator_etr_out_tmc_etr: endpoint { + remote-endpoint = + <&tmc_etr_in_replicator_etr>; + }; + }; + + port@1 { + reg = <1>; + replicator_etr_out_tmc_etr1: endpoint { + remote-endpoint = + <&tmc_etr1_in_replicator_etr>; + }; + }; + }; + }; + + tmc_etr: tmc@10048000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb961>; + + reg = <0x10048000 0x1000>, + <0x10064000 0x16000>; + reg-names = "tmc-base", "bam-base"; + + qcom,iommu-dma = "bypass"; + iommus = <&apps_smmu 0x04e0 0>, + <&apps_smmu 0x0520 0>; + + qcom,iommu-dma-addr-pool = <0x0 0xffc00000>; + + qcom,sw-usb; + dma-coherent; + coresight-name = "coresight-tmc-etr"; + + coresight-csr = <&csr>; + csr-atid-offset = <0xf8>; + csr-irqctrl-offset = <0x6c>; + byte-cntr-name = "byte-cntr"; + byte-cntr-class-name = "coresight-tmc-etr-stream"; + + interrupts = ; + interrupt-names = "byte-cntr-irq"; + + arm,scatter-gather; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + tmc_etr_in_replicator_etr: endpoint { + remote-endpoint = + <&replicator_etr_out_tmc_etr>; + }; + }; + }; + }; + + tmc_etr1: tmc@1004f000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb961>; + + reg = <0x1004f000 0x1000>; + reg-names = "tmc-base"; + + coresight-name = "coresight-tmc-etr1"; + + iommus = <&apps_smmu 0x0500 0>; + qcom,iommu-dma-addr-pool = <0x0 0xffc00000>; + dma-coherent; + + coresight-csr = <&csr>; + csr-atid-offset = <0x108>; + csr-irqctrl-offset = <0x70>; + byte-cntr-name = "byte-cntr1"; + byte-cntr-class-name = "coresight-tmc-etr1-stream"; + + interrupts = ; + interrupt-names = "byte-cntr-irq"; + + arm,scatter-gather; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + tmc_etr1_in_replicator_etr: endpoint { + remote-endpoint = + <&replicator_etr_out_tmc_etr1>; + }; + }; + }; + }; + + csr: csr@10001000 { + compatible = "qcom,coresight-csr"; + + reg = <0x10001000 0x1000>; + reg-names = "csr-base"; + + coresight-name = "coresight-csr"; + qcom,usb-bam-support; + qcom,perflsheot-set-support; + qcom,hwctrl-set-support; + qcom,set-byte-cntr-support; + qcom,blk-size = <1>; + }; + + swao_csr: csr@10b11000 { + compatible = "qcom,coresight-csr"; + + reg = <0x10b11000 0x1000>, + <0x10b110f8 0x50>; + reg-names = "csr-base", "msr-base"; + + coresight-name = "coresight-swao-csr"; + qcom,timestamp-support; + qcom,msr-support; + qcom,blk-size = <1>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + qc_cti: cti@10010000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10010000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-qc_cti"; + + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cti-gpio-trigout = <16>; + pinctrl-names = "cti-trigout-pctrl"; + pinctrl-0 = <&trigout_a>; + }; + + cti0: cti@10c2a000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10c2a000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-cti0"; + + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + south_cti: cti@109C2000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x109C2000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-dl_south_cti0"; + + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + ddr_dl_0_cti_0: cti@10d02000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10d02000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-ddr_dl_0_cti_0"; + + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + ddr_dl_1_cti_0: cti@10d0c000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10d0c000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-ddr_dl_1_cti_0"; + + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + ddr_ch01_dl_cti_0: cti@10d21000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10d21000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-ddr_ch01_dl_cti_0"; + + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + lpass_dl_cti: cti@10845000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10845000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-lpass_dl_cti"; + + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + gpu_isdb_cti: cti@10961000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10961000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-gpu_isdb_cti"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + gpu_cortex_m3: cti@10962000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10962000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-gpu_cortex_m3"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + turing_dl_cti_0: cti@10982000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10982000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-turing_dl_cti_0"; + + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + turing_q6_cti: cti@1098b000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x1098b000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-turing_q6_cti"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + wlan_q6_cti: cti@10C7B000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10C7B000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-wlan_q6_cti"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + swao_cti: cti@10b00000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10b00000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-swao_cti"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,extended_cti; + }; + + cortex_m3: cti@10b13000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10b13000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-cortex_m3"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + lpass_lpi_cti: cti@10b41000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10b41000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-lpass_lpi_cti"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + lpass_q6_cti: cti@10b4b000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10b4b000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-lpass_q6_cti"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + apss_cti0: cti@128e0000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x128e0000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-apss_cti0"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + apss_cti1: cti@128f0000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x128f0000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-apss_cti1"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + apss_cti2: cti@12900000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x12900000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-apss_cti2"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + riscv_cti: cti@1282b000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x1282b000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-riscv_cti"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + mss_q6_cti: cti@1080b000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x1080b000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-mss_q6_cti"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + mss_vq6_cti: cti@10813000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10813000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-mss_vq6_cti"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + tmess_cti_0: cti@10cc2000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10cc2000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-tmess_cti_0"; + + qcom,extended_cti; + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + tmess_cti_1: cti@10cc3000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10cc3000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-tmess_cti_1"; + + qcom,extended_cti; + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + tmess_cpu: cti@10cd1000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10cd1000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-tmess_cpu"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + apss_atb_cti: cti@12862000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x12862000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-apss_atb_cti"; + + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + ddrss_shrm2: cti@10d11000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10d11000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-ddrss_shrm2"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + Sierra_A6: cti@10C13000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10C13000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-sierra_a6"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + wcss0: cti@109AC000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x109AC000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-sierra_a6"; + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + wcss1: cti@109ad000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x109ad000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-wcss1"; + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + wcss2: cti@109Ae000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x109Ae000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-wcss2"; + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + ipcb_tgu: tgu@10b0e000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb999>; + + reg = <0x10b0e000 0x1000>; + reg-names = "tgu-base"; + + tgu-steps = <3>; + tgu-conditions = <4>; + tgu-regs = <4>; + tgu-timer-counters = <8>; + + coresight-name = "coresight-tgu-ipcb"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + spmi_tgu0: tgu@10b0f000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb999>; + + reg = <0x10b0f000 0x1000>; + reg-names = "tgu-base"; + + tgu-steps = <3>; + tgu-conditions = <4>; + tgu-regs = <9>; + tgu-timer-counters = <8>; + + coresight-name = "coresight-tgu-spmi0"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + spmi_tgu1: tgu@10b10000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb999>; + + reg = <0x10b10000 0x1000>; + reg-names = "tgu-base"; + + tgu-steps = <3>; + tgu-conditions = <4>; + tgu-regs = <9>; + tgu-timer-counters = <8>; + + coresight-name = "coresight-tgu-spmi1"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + etm0 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x12040000 0x1000>; + cpu = <&CPU0>; + + coresight-name = "coresight-etm0"; + qcom,skip-power-up; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + atid = <1>; + out-ports { + port { + ete0_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete0>; + }; + }; + }; + }; + + etm1 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x12140000 0x1000>; + cpu = <&CPU1>; + + coresight-name = "coresight-etm1"; + qcom,skip-power-up; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + atid = <2>; + out-ports { + port { + ete1_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete1>; + }; + }; + }; + }; + + etm2 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x12240000 0x1000>; + cpu = <&CPU2>; + + coresight-name = "coresight-etm2"; + qcom,skip-power-up; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + atid = <3>; + out-ports { + port { + ete2_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete2>; + }; + }; + }; + }; + + etm3 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x12340000 0x1000>; + cpu = <&CPU3>; + + coresight-name = "coresight-etm3"; + qcom,skip-power-up; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + atid = <4>; + out-ports { + port { + ete3_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete3>; + }; + }; + }; + }; + + etm4 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x12440000 0x1000>; + cpu = <&CPU4>; + + coresight-name = "coresight-etm4"; + qcom,skip-power-up; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + atid = <5>; + out-ports { + port { + ete4_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete4>; + }; + }; + }; + }; + + etm5 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x12540000 0x1000>; + cpu = <&CPU5>; + + coresight-name = "coresight-etm5"; + qcom,skip-power-up; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + atid = <6>; + out-ports { + port { + ete5_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete5>; + }; + }; + }; + }; + + etm6 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x12640000 0x1000>; + cpu = <&CPU6>; + + coresight-name = "coresight-etm6"; + qcom,skip-power-up; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + atid = <7>; + out-ports { + port { + ete6_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete6>; + }; + }; + }; + }; + + etm7 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x12740000 0x1000>; + cpu = <&CPU7>; + + coresight-name = "coresight-etm7"; + qcom,skip-power-up; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + atid = <8>; + out-ports { + port { + ete7_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete7>; + }; + }; + }; + }; + + funnel_etm: funnel@12800000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x12800000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-etm"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_ete_out_funnel_apss: endpoint { + remote-endpoint = + <&funnel_apss_in_funnel_ete>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_ete_in_ete0: endpoint { + remote-endpoint = + <&ete0_out_funnel_ete>; + }; + }; + + port@1 { + reg = <1>; + funnel_ete_in_ete1: endpoint { + remote-endpoint = + <&ete1_out_funnel_ete>; + }; + }; + + port@2 { + reg = <2>; + funnel_ete_in_ete2: endpoint { + remote-endpoint = + <&ete2_out_funnel_ete>; + }; + }; + + port@3 { + reg = <3>; + funnel_ete_in_ete3: endpoint { + remote-endpoint = + <&ete3_out_funnel_ete>; + }; + }; + + port@4 { + reg = <4>; + funnel_ete_in_ete4: endpoint { + remote-endpoint = + <&ete4_out_funnel_ete>; + }; + }; + + port@5 { + reg = <5>; + funnel_ete_in_ete5: endpoint { + remote-endpoint = + <&ete5_out_funnel_ete>; + }; + }; + + port@6 { + reg = <6>; + funnel_ete_in_ete6: endpoint { + remote-endpoint = + <&ete6_out_funnel_ete>; + }; + }; + + port@7 { + reg = <7>; + funnel_ete_in_ete7: endpoint { + remote-endpoint = + <&ete7_out_funnel_ete>; + }; + }; + }; + }; +}; diff --git a/qcom/parrot-debug.dtsi b/qcom/parrot-debug.dtsi new file mode 100644 index 00000000..083def43 --- /dev/null +++ b/qcom/parrot-debug.dtsi @@ -0,0 +1,1745 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dump_mem: mem_dump_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0xc00000>; + }; +}; + +&soc { + dcc: dcc_v2@100ff000 { + compatible = "qcom,dcc-v2"; + reg = <0x100ff000 0x1000>, + <0x10080000 0x18000>; + + qcom,transaction_timeout = <0>; + + reg-names = "dcc-base", "dcc-ram-base"; + dcc-ram-offset = <0>; + + link_list_0 { + qcom,curr-link-list = <6>; + qcom,data-sink = "sram"; + qcom,link-list = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + link_list_1 { + qcom,curr-link-list = <4>; + qcom,data-sink = "sram"; + qcom,link-list = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + }; + + mem_dump { + compatible = "qcom,mem-dump"; + memory-region = <&dump_mem>; + + c0_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x0>; + }; + + c100_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x1>; + }; + + c200_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x2>; + }; + + c300_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x3>; + }; + + c400_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x4>; + }; + + c500_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x5>; + }; + + c600_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x6>; + }; + + c700_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x7>; + }; + + cpuss_reg { + qcom,dump-size = <0x30000>; + qcom,dump-id = <0xef>; + }; + + l1_icache0 { + qcom,dump-size = <0x10900>; + qcom,dump-id = <0x60>; + }; + + l1_icache100 { + qcom,dump-size = <0x10900>; + qcom,dump-id = <0x61>; + }; + + l1_icache200 { + qcom,dump-size = <0x10900>; + qcom,dump-id = <0x62>; + }; + + l1_icache300 { + qcom,dump-size = <0x10900>; + qcom,dump-id = <0x63>; + }; + + l1_icache400 { + qcom,dump-size = <0x15100>; + qcom,dump-id = <0x64>; + }; + + l1_icache500 { + qcom,dump-size = <0x15100>; + qcom,dump-id = <0x65>; + }; + + l1_icache600 { + qcom,dump-size = <0x15100>; + qcom,dump-id = <0x66>; + }; + + l1_icache700 { + qcom,dump-size = <0x32100>; + qcom,dump-id = <0x67>; + }; + + l1_dcache0 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x80>; + }; + + l1_dcache100 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x81>; + }; + + l1_dcache200 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x82>; + }; + + l1_dcache300 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x83>; + }; + + l1_dcache400 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x84>; + }; + + l1_dcache500 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x85>; + }; + + l1_dcache600 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x86>; + }; + + l1_dcache700 { + qcom,dump-size = <0x12100>; + qcom,dump-id = <0x87>; + }; + + l1_itlb400 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x24>; + }; + + l1_itlb500 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x25>; + }; + + l1_itlb600 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x26>; + }; + + l1_itlb700 { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x27>; + }; + + l1_dtlb400 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x44>; + }; + + l1_dtlb500 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x45>; + }; + + l1_dtlb600 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x46>; + }; + + l1_dtlb700 { + qcom,dump-size = <0x3a0>; + qcom,dump-id = <0x47>; + }; + + l2_cache400 { + qcom,dump-size = <0x90100>; + qcom,dump-id = <0xc4>; + }; + + l2_cache500 { + qcom,dump-size = <0x90100>; + qcom,dump-id = <0xc5>; + }; + + l2_cache600 { + qcom,dump-size = <0x90100>; + qcom,dump-id = <0xc6>; + }; + + l2_cache700 { + qcom,dump-size = <0x120100>; + qcom,dump-id = <0xc7>; + }; + + l2_tlb0 { + qcom,dump-size = <0x5b00>; + qcom,dump-id = <0x120>; + }; + + l2_tlb100 { + qcom,dump-size = <0x5b00>; + qcom,dump-id = <0x121>; + }; + + l2_tlb200 { + qcom,dump-size = <0x5b00>; + qcom,dump-id = <0x122>; + }; + + l2_tlb300 { + qcom,dump-size = <0x5b00>; + qcom,dump-id = <0x123>; + }; + + l2_tlb400 { + qcom,dump-size = <0x6100>; + qcom,dump-id = <0x124>; + }; + + l2_tlb500 { + qcom,dump-size = <0x6100>; + qcom,dump-id = <0x125>; + }; + + l2_tlb600 { + qcom,dump-size = <0x6100>; + qcom,dump-id = <0x126>; + }; + + l2_tlb700 { + qcom,dump-size = <0xc100>; + qcom,dump-id = <0x127>; + }; + + rpmh { + qcom,dump-size = <0x400000>; + qcom,dump-id = <0xec>; + }; + + rpm_sw { + qcom,dump-size = <0x28000>; + qcom,dump-id = <0xea>; + }; + + pmic { + qcom,dump-size = <0x200000>; + qcom,dump-id = <0xe4>; + }; + + fcm { + qcom,dump-size = <0x8400>; + qcom,dump-id = <0xee>; + }; + + etf_swao { + qcom,dump-size = <0x10000>; + qcom,dump-id = <0xf1>; + }; + + etr_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x100>; + }; + + etr1_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x105>; + }; + + etfswao_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x102>; + }; + + misc_data { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0xe8>; + }; + + etf_lpass { + qcom,dump-size = <0x4000>; + qcom,dump-id = <0xf4>; + }; + + etflpass_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x104>; + }; + + osm_reg { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x163>; + }; + + pcu_reg { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x164>; + }; + + fsm_data { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x165>; + }; + }; +}; diff --git a/qcom/parrot-dma-heaps.dtsi b/qcom/parrot-dma-heaps.dtsi new file mode 100644 index 00000000..f27ed58d --- /dev/null +++ b/qcom/parrot-dma-heaps.dtsi @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + qcom,dma-heaps { + compatible = "qcom,dma-heaps"; + qcom,secure_cdsp { + qcom,dma-heap-name = "qcom,cma-secure-cdsp"; + qcom,dma-heap-type = ; + memory-region = <&cdsp_secure_heap>; + }; + + qcom,adsp { + qcom,dma-heap-name = "qcom,adsp"; + qcom,dma-heap-type = ; + memory-region = <&sdsp_mem>; + }; + + qcom,audio_ml { + qcom,dma-heap-name = "qcom,audio-ml"; + qcom,dma-heap-type = ; + memory-region = <&audio_cma_mem>; + }; + + non_secure_display_dma_buf: qcom,display { + qcom,dma-heap-name = "qcom,display"; + qcom,dma-heap-type = ; + qcom,max-align = <9>; + memory-region = <&non_secure_display_memory>; + }; + + qcom,qseecom { + qcom,dma-heap-name = "qcom,qseecom"; + qcom,dma-heap-type = ; + memory-region = <&qseecom_mem>; + }; + + qcom,qseecom_ta { + qcom,dma-heap-name = "qcom,qseecom-ta"; + qcom,dma-heap-type = ; + memory-region = <&qseecom_ta_mem>; + }; + }; +}; diff --git a/qcom/parrot-idp-4gb-overlay.dts b/qcom/parrot-idp-4gb-overlay.dts new file mode 100644 index 00000000..9cb3260f --- /dev/null +++ b/qcom/parrot-idp-4gb-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "parrot-wcn6750.dtsi" +#include "parrot-idp-4gb.dtsi" +#include "parrot-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot IDP 4GB DDR"; + compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp"; + qcom,msm-id = <537 0x10000>; + qcom,board-id = <34 0x600>; +}; diff --git a/qcom/parrot-idp-4gb.dts b/qcom/parrot-idp-4gb.dts new file mode 100644 index 00000000..df046cf5 --- /dev/null +++ b/qcom/parrot-idp-4gb.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrot-4gb.dtsi" +#include "parrot-wcn6750.dtsi" +#include "parrot-idp-4gb.dtsi" +#include "parrot-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot IDP 4GB DDR"; + compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp"; + qcom,board-id = <34 0x600>; +}; diff --git a/qcom/parrot-idp-4gb.dtsi b/qcom/parrot-idp-4gb.dtsi new file mode 100644 index 00000000..b82bb81e --- /dev/null +++ b/qcom/parrot-idp-4gb.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-idp.dtsi" diff --git a/qcom/parrot-idp-nopmi-overlay.dts b/qcom/parrot-idp-nopmi-overlay.dts new file mode 100644 index 00000000..eba84c44 --- /dev/null +++ b/qcom/parrot-idp-nopmi-overlay.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "parrot-wcn6750.dtsi" +#include "parrot-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot IDP"; + compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp"; + qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>, + <633 0x10000>, <634 0x10000>, <638 0x10000>; + qcom,board-id = <34 0>; + qcom,pmic-id-size = <9>; + qcom,pmic-id = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; +}; diff --git a/qcom/parrot-idp-nopmi.dts b/qcom/parrot-idp-nopmi.dts new file mode 100644 index 00000000..7ffc6702 --- /dev/null +++ b/qcom/parrot-idp-nopmi.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrot.dtsi" +#include "parrot-wcn6750.dtsi" +#include "parrot-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot IDP"; + compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp"; + qcom,board-id = <34 0>; + qcom,pmic-id-size = <9>; + qcom,pmic-id = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; +}; diff --git a/qcom/parrot-idp-overlay.dts b/qcom/parrot-idp-overlay.dts new file mode 100644 index 00000000..59ba2ac8 --- /dev/null +++ b/qcom/parrot-idp-overlay.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "parrot-wcn6750.dtsi" +#include "parrot-idp.dtsi" +#include "parrot-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot IDP"; + compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp"; + qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>, + <633 0x10000>, <634 0x10000>, <638 0x10000>; + qcom,board-id = <34 0>; +}; diff --git a/qcom/parrot-idp-pm7250b.dtsi b/qcom/parrot-idp-pm7250b.dtsi new file mode 100644 index 00000000..a200870b --- /dev/null +++ b/qcom/parrot-idp-pm7250b.dtsi @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-pm7250b.dtsi" + +/ { + qcom,pmic-id-size = <9>; + qcom,pmic-id = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x2E>; +}; + +&battery_charger { + qcom,thermal-mitigation = <3000000 1500000 1000000 500000>; + qcom,wireless-charging-not-supported; +}; + +&usb0 { + usb-role-switch; + extcon = <&eud>; + + dwc3@a600000 { + usb-role-switch; + dr_mode = "otg"; + }; + + port { + usb_port0: endpoint { + remote-endpoint = <&usb_port0_connector>; + }; + }; +}; + +&ucsi { + connector { + port { + usb_port0_connector: endpoint { + remote-endpoint = <&usb_port0>; + }; + }; + }; +}; diff --git a/qcom/parrot-idp-pm8350b-overlay.dts b/qcom/parrot-idp-pm8350b-overlay.dts new file mode 100644 index 00000000..d0cc4845 --- /dev/null +++ b/qcom/parrot-idp-pm8350b-overlay.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "parrot-wcn6750.dtsi" +#include "parrot-idp.dtsi" +#include "parrot-idp-pm8350b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot IDP"; + compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp"; + qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>, + <633 0x10000>, <634 0x10000>, <638 0x10000>; + qcom,board-id = <34 0>; +}; diff --git a/qcom/parrot-idp-pm8350b.dts b/qcom/parrot-idp-pm8350b.dts new file mode 100644 index 00000000..8ee2ec22 --- /dev/null +++ b/qcom/parrot-idp-pm8350b.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrot.dtsi" +#include "parrot-wcn6750.dtsi" +#include "parrot-idp.dtsi" +#include "parrot-idp-pm8350b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot IDP"; + compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp"; + qcom,board-id = <34 0>; +}; diff --git a/qcom/parrot-idp-pm8350b.dtsi b/qcom/parrot-idp-pm8350b.dtsi new file mode 100644 index 00000000..341b43ce --- /dev/null +++ b/qcom/parrot-idp-pm8350b.dtsi @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-pm8350b.dtsi" + +/ { + qcom,pmic-id-size = <9>; + qcom,pmic-id = <0x0 0x0 0x0 0x32 0x0 0x0 0x0 0x0 0x0>; +}; + +&battery_charger { + qcom,thermal-mitigation = <3000000 1500000 1000000 500000>; +}; + +&usb0 { + usb-role-switch; + extcon = <&eud>; + + dwc3@a600000 { + usb-role-switch; + dr_mode = "otg"; + }; + + port { + usb_port0: endpoint { + remote-endpoint = <&usb_port0_connector>; + }; + }; +}; + +&ucsi { + connector { + port { + usb_port0_connector: endpoint { + remote-endpoint = <&usb_port0>; + }; + }; + }; +}; diff --git a/qcom/parrot-idp-wcn3990-4gb-overlay.dts b/qcom/parrot-idp-wcn3990-4gb-overlay.dts new file mode 100644 index 00000000..e9a40f89 --- /dev/null +++ b/qcom/parrot-idp-wcn3990-4gb-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "parrot-wcn3990.dtsi" +#include "parrot-idp-wcn3990-4gb.dtsi" +#include "parrot-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot IDP 4GB DDR + WCN3990"; + compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp"; + qcom,msm-id = <537 0x10000>; + qcom,board-id = <34 0x601>; +}; diff --git a/qcom/parrot-idp-wcn3990-4gb.dts b/qcom/parrot-idp-wcn3990-4gb.dts new file mode 100644 index 00000000..c5850d3d --- /dev/null +++ b/qcom/parrot-idp-wcn3990-4gb.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrot-4gb.dtsi" +#include "parrot-wcn3990.dtsi" +#include "parrot-idp-wcn3990-4gb.dtsi" +#include "parrot-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot IDP 4GB DDR + WCN3990"; + compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp"; + qcom,board-id = <34 0x601>; +}; diff --git a/qcom/parrot-idp-wcn3990-4gb.dtsi b/qcom/parrot-idp-wcn3990-4gb.dtsi new file mode 100644 index 00000000..eab38cc8 --- /dev/null +++ b/qcom/parrot-idp-wcn3990-4gb.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-idp-4gb.dtsi" diff --git a/qcom/parrot-idp-wcn3990-amoled-rcm-4gb-overlay.dts b/qcom/parrot-idp-wcn3990-amoled-rcm-4gb-overlay.dts new file mode 100644 index 00000000..a87a72a8 --- /dev/null +++ b/qcom/parrot-idp-wcn3990-amoled-rcm-4gb-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "parrot-wcn3990.dtsi" +#include "parrot-idp-wcn3990-amoled-rcm-4gb.dtsi" +#include "parrot-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot WCN3990 IDP 4GB DDR + AMOLED + RCM"; + compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp"; + qcom,msm-id = <537 0x10000>; + qcom,board-id = <34 0x603>; +}; diff --git a/qcom/parrot-idp-wcn3990-amoled-rcm-4gb.dts b/qcom/parrot-idp-wcn3990-amoled-rcm-4gb.dts new file mode 100644 index 00000000..23372ff3 --- /dev/null +++ b/qcom/parrot-idp-wcn3990-amoled-rcm-4gb.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrot-4gb.dtsi" +#include "parrot-wcn3990.dtsi" +#include "parrot-idp-wcn3990-amoled-rcm-4gb.dtsi" +#include "parrot-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot WCN3990 IDP 4GB DDR + AMOLED + RCM"; + compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp"; + qcom,board-id = <34 0x603>; +}; diff --git a/qcom/parrot-idp-wcn3990-amoled-rcm-4gb.dtsi b/qcom/parrot-idp-wcn3990-amoled-rcm-4gb.dtsi new file mode 100644 index 00000000..eab38cc8 --- /dev/null +++ b/qcom/parrot-idp-wcn3990-amoled-rcm-4gb.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-idp-4gb.dtsi" diff --git a/qcom/parrot-idp-wcn3990-amoled-rcm-overlay.dts b/qcom/parrot-idp-wcn3990-amoled-rcm-overlay.dts new file mode 100644 index 00000000..d9ced551 --- /dev/null +++ b/qcom/parrot-idp-wcn3990-amoled-rcm-overlay.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "parrot-wcn3990.dtsi" +#include "parrot-idp-wcn3990-amoled-rcm.dtsi" +#include "parrot-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot WCN3990 IDP + AMOLED + RCM"; + compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp"; + qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>, + <633 0x10000>, <634 0x10000>, <638 0x10000>; + qcom,board-id = <34 3>; +}; diff --git a/qcom/parrot-idp-wcn3990-amoled-rcm.dts b/qcom/parrot-idp-wcn3990-amoled-rcm.dts new file mode 100644 index 00000000..09bc3b06 --- /dev/null +++ b/qcom/parrot-idp-wcn3990-amoled-rcm.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrot.dtsi" +#include "parrot-wcn3990.dtsi" +#include "parrot-idp-wcn3990-amoled-rcm.dtsi" +#include "parrot-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot WCN3990 IDP + AMOLED + RCM"; + compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp"; + qcom,board-id = <34 3>; +}; diff --git a/qcom/parrot-idp-wcn3990-amoled-rcm.dtsi b/qcom/parrot-idp-wcn3990-amoled-rcm.dtsi new file mode 100644 index 00000000..b21bcc8f --- /dev/null +++ b/qcom/parrot-idp-wcn3990-amoled-rcm.dtsi @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-idp.dtsi" + +&soc { +}; + +&qupv3_se9_i2c { + status = "disabled"; +}; + +&qupv3_se9_spi { + #address-cells = <1>; + #size-cells = <0>; + status = "ok"; + qcom,touch-active = "goodix,gt9916S"; + + goodix-berlin@0 { + reg = <0>; + spi-max-frequency = <1000000>; + + goodix,avdd-name = "avdd"; + avdd-supply = <&L28B>; + + interrupt-parent = <&tlmm>; + interrupts = <65 0x2008>; + goodix,reset-gpio = <&tlmm 64 0x00>; + goodix,irq-gpio = <&tlmm 65 0x2008>; + goodix,irq-flags = <2>; + goodix,panel-max-x = <1080>; + goodix,panel-max-y = <2400>; + goodix,panel-max-w = <255>; + goodix,panel-max-p = <4096>; + goodix,firmware-name = "goodix_firmware_spi.bin"; + goodix,config-name = "goodix_cfg_group_spi.bin"; + + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", "pmx_ts_release"; + pinctrl-0 = <&ts_spi_active>; + pinctrl-1 = <&ts_spi_int_suspend &ts_spi_reset_suspend>; + pinctrl-2 = <&ts_spi_release>; + + qcom,touch-environment = "pvm"; + }; +}; diff --git a/qcom/parrot-idp-wcn3990-overlay.dts b/qcom/parrot-idp-wcn3990-overlay.dts new file mode 100644 index 00000000..b9605f08 --- /dev/null +++ b/qcom/parrot-idp-wcn3990-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; +#include "parrot-wcn3990.dtsi" +#include "parrot-idp-wcn3990.dtsi" +#include "parrot-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot IDP + WCN3990"; + compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp"; + qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>, + <633 0x10000>, <634 0x10000>, <638 0x10000>; + qcom,board-id = <34 1>; +}; diff --git a/qcom/parrot-idp-wcn3990.dts b/qcom/parrot-idp-wcn3990.dts new file mode 100644 index 00000000..f21fb180 --- /dev/null +++ b/qcom/parrot-idp-wcn3990.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrot.dtsi" +#include "parrot-wcn3990.dtsi" +#include "parrot-idp-wcn3990.dtsi" +#include "parrot-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot IDP + WCN3990"; + compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp"; + qcom,board-id = <34 1>; +}; diff --git a/qcom/parrot-idp-wcn3990.dtsi b/qcom/parrot-idp-wcn3990.dtsi new file mode 100644 index 00000000..e8ec9e92 --- /dev/null +++ b/qcom/parrot-idp-wcn3990.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-idp.dtsi" + +&soc { +}; diff --git a/qcom/parrot-idp-wcn6750-amoled-4gb-overlay.dts b/qcom/parrot-idp-wcn6750-amoled-4gb-overlay.dts new file mode 100644 index 00000000..38fca753 --- /dev/null +++ b/qcom/parrot-idp-wcn6750-amoled-4gb-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "parrot-wcn6750.dtsi" +#include "parrot-idp-wcn6750-amoled-4gb.dtsi" +#include "parrot-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot WCN6750 IDP 4GB DDR + AMOLED"; + compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp"; + qcom,msm-id = <537 0x10000>; + qcom,board-id = <34 0x604>; +}; diff --git a/qcom/parrot-idp-wcn6750-amoled-4gb.dts b/qcom/parrot-idp-wcn6750-amoled-4gb.dts new file mode 100644 index 00000000..366fc881 --- /dev/null +++ b/qcom/parrot-idp-wcn6750-amoled-4gb.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrot-4gb.dtsi" +#include "parrot-wcn6750.dtsi" +#include "parrot-idp-wcn6750-amoled-4gb.dtsi" +#include "parrot-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot WCN6750 IDP 4GB DDR + AMOLED"; + compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp"; + qcom,board-id = <34 0x604>; +}; diff --git a/qcom/parrot-idp-wcn6750-amoled-4gb.dtsi b/qcom/parrot-idp-wcn6750-amoled-4gb.dtsi new file mode 100644 index 00000000..eab38cc8 --- /dev/null +++ b/qcom/parrot-idp-wcn6750-amoled-4gb.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-idp-4gb.dtsi" diff --git a/qcom/parrot-idp-wcn6750-amoled-overlay.dts b/qcom/parrot-idp-wcn6750-amoled-overlay.dts new file mode 100644 index 00000000..41d60a10 --- /dev/null +++ b/qcom/parrot-idp-wcn6750-amoled-overlay.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "parrot-wcn6750.dtsi" +#include "parrot-idp-wcn6750-amoled.dtsi" +#include "parrot-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot WCN6750 IDP + AMOLED"; + compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp"; + qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>, + <633 0x10000>, <634 0x10000>, <638 0x10000>; + qcom,board-id = <34 4>; +}; diff --git a/qcom/parrot-idp-wcn6750-amoled-rcm-4gb-overlay.dts b/qcom/parrot-idp-wcn6750-amoled-rcm-4gb-overlay.dts new file mode 100644 index 00000000..e936c82d --- /dev/null +++ b/qcom/parrot-idp-wcn6750-amoled-rcm-4gb-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "parrot-wcn6750.dtsi" +#include "parrot-idp-wcn6750-amoled-rcm-4gb.dtsi" +#include "parrot-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot WCN6750 IDP 4GB DDR + AMOLED + RCM"; + compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp"; + qcom,msm-id = <537 0x10000>; + qcom,board-id = <34 0x602>; +}; diff --git a/qcom/parrot-idp-wcn6750-amoled-rcm-4gb.dts b/qcom/parrot-idp-wcn6750-amoled-rcm-4gb.dts new file mode 100644 index 00000000..3d712da2 --- /dev/null +++ b/qcom/parrot-idp-wcn6750-amoled-rcm-4gb.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrot-4gb.dtsi" +#include "parrot-wcn6750.dtsi" +#include "parrot-idp-wcn6750-amoled-rcm-4gb.dtsi" +#include "parrot-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot WCN6750 IDP 4GB DDR + AMOLED + RCM"; + compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp"; + qcom,board-id = <34 0x602>; +}; diff --git a/qcom/parrot-idp-wcn6750-amoled-rcm-4gb.dtsi b/qcom/parrot-idp-wcn6750-amoled-rcm-4gb.dtsi new file mode 100644 index 00000000..eab38cc8 --- /dev/null +++ b/qcom/parrot-idp-wcn6750-amoled-rcm-4gb.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-idp-4gb.dtsi" diff --git a/qcom/parrot-idp-wcn6750-amoled-rcm-overlay.dts b/qcom/parrot-idp-wcn6750-amoled-rcm-overlay.dts new file mode 100644 index 00000000..edfce1f6 --- /dev/null +++ b/qcom/parrot-idp-wcn6750-amoled-rcm-overlay.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "parrot-wcn6750.dtsi" +#include "parrot-idp-wcn6750-amoled-rcm.dtsi" +#include "parrot-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot WCN6750 IDP + AMOLED + RCM"; + compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp"; + qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>, + <633 0x10000>, <634 0x10000>, <638 0x10000>; + qcom,board-id = <34 2>; +}; diff --git a/qcom/parrot-idp-wcn6750-amoled-rcm.dts b/qcom/parrot-idp-wcn6750-amoled-rcm.dts new file mode 100644 index 00000000..50c5d72c --- /dev/null +++ b/qcom/parrot-idp-wcn6750-amoled-rcm.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrot.dtsi" +#include "parrot-wcn6750.dtsi" +#include "parrot-idp-wcn6750-amoled-rcm.dtsi" +#include "parrot-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot WCN6750 IDP + AMOLED + RCM"; + compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp"; + qcom,board-id = <34 2>; +}; diff --git a/qcom/parrot-idp-wcn6750-amoled-rcm.dtsi b/qcom/parrot-idp-wcn6750-amoled-rcm.dtsi new file mode 100644 index 00000000..b21bcc8f --- /dev/null +++ b/qcom/parrot-idp-wcn6750-amoled-rcm.dtsi @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-idp.dtsi" + +&soc { +}; + +&qupv3_se9_i2c { + status = "disabled"; +}; + +&qupv3_se9_spi { + #address-cells = <1>; + #size-cells = <0>; + status = "ok"; + qcom,touch-active = "goodix,gt9916S"; + + goodix-berlin@0 { + reg = <0>; + spi-max-frequency = <1000000>; + + goodix,avdd-name = "avdd"; + avdd-supply = <&L28B>; + + interrupt-parent = <&tlmm>; + interrupts = <65 0x2008>; + goodix,reset-gpio = <&tlmm 64 0x00>; + goodix,irq-gpio = <&tlmm 65 0x2008>; + goodix,irq-flags = <2>; + goodix,panel-max-x = <1080>; + goodix,panel-max-y = <2400>; + goodix,panel-max-w = <255>; + goodix,panel-max-p = <4096>; + goodix,firmware-name = "goodix_firmware_spi.bin"; + goodix,config-name = "goodix_cfg_group_spi.bin"; + + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", "pmx_ts_release"; + pinctrl-0 = <&ts_spi_active>; + pinctrl-1 = <&ts_spi_int_suspend &ts_spi_reset_suspend>; + pinctrl-2 = <&ts_spi_release>; + + qcom,touch-environment = "pvm"; + }; +}; diff --git a/qcom/parrot-idp-wcn6750-amoled.dts b/qcom/parrot-idp-wcn6750-amoled.dts new file mode 100644 index 00000000..261d3b43 --- /dev/null +++ b/qcom/parrot-idp-wcn6750-amoled.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrot.dtsi" +#include "parrot-wcn6750.dtsi" +#include "parrot-idp-wcn6750-amoled.dtsi" +#include "parrot-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot WCN6750 IDP + AMOLED"; + compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp"; + qcom,board-id = <34 4>; +}; diff --git a/qcom/parrot-idp-wcn6750-amoled.dtsi b/qcom/parrot-idp-wcn6750-amoled.dtsi new file mode 100644 index 00000000..b21bcc8f --- /dev/null +++ b/qcom/parrot-idp-wcn6750-amoled.dtsi @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-idp.dtsi" + +&soc { +}; + +&qupv3_se9_i2c { + status = "disabled"; +}; + +&qupv3_se9_spi { + #address-cells = <1>; + #size-cells = <0>; + status = "ok"; + qcom,touch-active = "goodix,gt9916S"; + + goodix-berlin@0 { + reg = <0>; + spi-max-frequency = <1000000>; + + goodix,avdd-name = "avdd"; + avdd-supply = <&L28B>; + + interrupt-parent = <&tlmm>; + interrupts = <65 0x2008>; + goodix,reset-gpio = <&tlmm 64 0x00>; + goodix,irq-gpio = <&tlmm 65 0x2008>; + goodix,irq-flags = <2>; + goodix,panel-max-x = <1080>; + goodix,panel-max-y = <2400>; + goodix,panel-max-w = <255>; + goodix,panel-max-p = <4096>; + goodix,firmware-name = "goodix_firmware_spi.bin"; + goodix,config-name = "goodix_cfg_group_spi.bin"; + + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", "pmx_ts_release"; + pinctrl-0 = <&ts_spi_active>; + pinctrl-1 = <&ts_spi_int_suspend &ts_spi_reset_suspend>; + pinctrl-2 = <&ts_spi_release>; + + qcom,touch-environment = "pvm"; + }; +}; diff --git a/qcom/parrot-idp.dts b/qcom/parrot-idp.dts new file mode 100644 index 00000000..cb186647 --- /dev/null +++ b/qcom/parrot-idp.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrot.dtsi" +#include "parrot-wcn6750.dtsi" +#include "parrot-idp.dtsi" +#include "parrot-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot IDP"; + compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp"; + qcom,board-id = <34 0>; +}; diff --git a/qcom/parrot-idp.dtsi b/qcom/parrot-idp.dtsi new file mode 100644 index 00000000..cdc545c5 --- /dev/null +++ b/qcom/parrot-idp.dtsi @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +#include "parrot-pmic-overlay.dtsi" +#include "parrot-thermal-overlay.dtsi" + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pm6450_gpios 1 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + }; +}; + +&pm6450_pwm_1 { + status = "ok"; +}; + +&qupv3_se9_i2c { + #address-cells = <1>; + #size-cells = <0>; + + status = "ok"; + qcom,i2c-touch-active = "novatek,NVT-ts"; + + novatek@62 { + reg = <0x62>; + + interrupt-parent = <&tlmm>; + interrupts = <13 0x2008>; + + pinctrl-names = "pmx_ts_active","pmx_ts_suspend", + "pmx_ts_release"; + + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&ts_release>; + + novatek,reset-gpio = <&tlmm 12 0x00>; + novatek,irq-gpio = <&tlmm 13 0x2008>; + + novatek,trusted-touch-mode = "vm_mode"; + novatek,touch-environment = "pvm"; + novatek,trusted-touch-spi-irq = <566>; + novatek,trusted-touch-io-bases = <0xa8c000 0xa10000>; + novatek,trusted-touch-io-sizes = <0x1000 0x4000>; + novatek,trusted-touch-vm-gpio-list = <&tlmm 10 0 &tlmm 11 0 + &tlmm 12 0 &tlmm 13 0x2008>; + }; + + focaltech@38 { + status = "disabled"; + reg = <0x38>; + + interrupt-parent = <&tlmm>; + interrupts = <13 0x2008>; + focaltech,reset-gpio = <&tlmm 12 0x00>; + focaltech,irq-gpio = <&tlmm 13 0x2008>; + focaltech,display-coords = <0 0 1080 2408>; + focaltech,max-touch-number = <5>; + focaltech,ic-type = <0x8726081C>; + focaltech,touch-type = "primary"; + + pinctrl-names = "pmx_ts_active","pmx_ts_suspend","pmx_ts_release"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&ts_release>; + }; +}; + +&sdhc_1 { + status = "ok"; + + vdd-supply = <&L24B>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L19B>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-current-level = <0 325000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; +}; + +&sdhc_2 { + status = "ok"; + + vdd-supply = <&L9E>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&L6E>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 22000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + cd-gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4-waipio"; + + vdda-phy-supply = <&L5B>; + vdda-pll-supply = <&L16B>; + vdda-phy-max-microamp = <140000>; + vdda-pll-max-microamp = <18300>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + + vcc-supply = <&L24B>; + vcc-max-microamp = <1200000>; + + vccq-supply = <&L13B>; + vccq-max-microamp = <1200000>; + + vccq2-supply = <&L19B>; + vccq2-max-microamp = <750000>; + + qcom,vddp-ref-clk-supply = <&L13B>; + qcom,vddp-ref-clk-max-microamp = <100>; + + /* + * ufs-dev-types and nvmem entries are for ufs device + * identification using nvmem interface. Use number of + * ufs devices supported for ufs-dev-types, and nvmem handle + * added by pmic for sdam register. + * + * Default value taken by driver is bit[0] = 0 for 3.x and + * bit[0] = 1 for 2.x driver code takes this as default case. + * + * But Bit value to identify ufs device is not consistent + * across the targets it could be bit[0] = 0/1 for UFS2.x/3x + * and vice versa. If the bit[0] value is not same as default + * value used in driver and if its reverted then use flag + * qcom,ufs-dev-revert to identify ufs device. + */ + ufs-dev-types = <2>; + qcom,ufs-dev-revert; + nvmem-cells = <&ufs_dev>, <&boot_config>; + nvmem-cell-names = "ufs_dev", "boot_conf"; + + status = "ok"; +}; diff --git a/qcom/parrot-pinctrl.dtsi b/qcom/parrot-pinctrl.dtsi new file mode 100644 index 00000000..28d57699 --- /dev/null +++ b/qcom/parrot-pinctrl.dtsi @@ -0,0 +1,1890 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + tlmm: pinctrl@f000000 { + compatible = "qcom,parrot-tlmm"; + reg = <0xf000000 0x1000000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + wakeup-parent = <&pdc>; + qcom,gpios-reserved = <0 1 2 3 38>; + + + bt_en_sleep: bt_en_sleep { + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + drive-strength = <2>; + output-low; + bias-pull-down; + }; + }; + + pri_aux_pcm_clk { + pri_aux_pcm_clk_sleep: pri_aux_pcm_clk_sleep { + mux { + pins = "gpio98"; + function = "gpio"; + }; + + config { + pins = "gpio98"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_aux_pcm_clk_active: pri_aux_pcm_clk_active { + mux { + pins = "gpio98"; + function = "i2s0_sck"; + }; + + config { + pins = "gpio98"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_aux_pcm_sync { + pri_aux_pcm_sync_sleep: pri_aux_pcm_sync_sleep { + mux { + pins = "gpio99"; + function = "gpio"; + }; + + config { + pins = "gpio99"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_aux_pcm_sync_active: pri_aux_pcm_sync_active { + mux { + pins = "gpio99"; + function = "i2s0_ws"; + }; + + config { + pins = "gpio99"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_aux_pcm_din { + pri_aux_pcm_din_sleep: pri_aux_pcm_din_sleep { + mux { + pins = "gpio101"; + function = "gpio"; + }; + + config { + pins = "gpio101"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_aux_pcm_din_active: pri_aux_pcm_din_active { + mux { + pins = "gpio101"; + function = "i2s0_data0"; + }; + + config { + pins = "gpio101"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_aux_pcm_dout { + pri_aux_pcm_dout_sleep: pri_aux_pcm_dout_sleep { + mux { + pins = "gpio111"; + function = "gpio"; + }; + + config { + pins = "gpio111"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_aux_pcm_dout_active: pri_aux_pcm_dout_active { + mux { + pins = "gpio111"; + function = "i2s0_data1"; + }; + + config { + pins = "gpio111"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_tdm_clk { + pri_tdm_clk_sleep: pri_tdm_clk_sleep { + mux { + pins = "gpio98"; + function = "gpio"; + }; + + config { + pins = "gpio98"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_tdm_clk_active: pri_tdm_clk_active { + mux { + pins = "gpio98"; + function = "i2s0_sck"; + }; + + config { + pins = "gpio98"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_tdm_sync { + pri_tdm_sync_sleep: pri_tdm_sync_sleep { + mux { + pins = "gpio99"; + function = "gpio"; + }; + + config { + pins = "gpio99"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_tdm_sync_active: pri_tdm_sync_active { + mux { + pins = "gpio99"; + function = "i2s0_ws"; + }; + + config { + pins = "gpio99"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_tdm_din { + pri_tdm_din_sleep: pri_tdm_din_sleep { + mux { + pins = "gpio101"; + function = "gpio"; + }; + + config { + pins = "gpio101"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_tdm_din_active: pri_tdm_din_active { + mux { + pins = "gpio101"; + function = "i2s0_data0"; + }; + + config { + pins = "gpio101"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_tdm_dout { + pri_tdm_dout_sleep: pri_tdm_dout_sleep { + mux { + pins = "gpio111"; + function = "gpio"; + }; + + config { + pins = "gpio111"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_tdm_dout_active: pri_tdm_dout_active { + mux { + pins = "gpio111"; + function = "i2s0_data1"; + }; + + config { + pins = "gpio111"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_mi2s_sck { + pri_mi2s_sck_sleep: pri_mi2s_sck_sleep { + mux { + pins = "gpio98"; + function = "gpio"; + }; + + config { + pins = "gpio98"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_sck_active: pri_mi2s_sck_active { + mux { + pins = "gpio98"; + function = "i2s0_sck"; + }; + + config { + pins = "gpio98"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_mi2s_ws { + pri_mi2s_ws_sleep: pri_mi2s_ws_sleep { + mux { + pins = "gpio99"; + function = "gpio"; + }; + + config { + pins = "gpio99"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_ws_active: pri_mi2s_ws_active { + mux { + pins = "gpio99"; + function = "i2s0_ws"; + }; + + config { + pins = "gpio99"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_mi2s_sd0 { + pri_mi2s_sd0_sleep: pri_mi2s_sd0_sleep { + mux { + pins = "gpio101"; + function = "gpio"; + }; + + config { + pins = "gpio101"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_sd0_active: pri_mi2s_sd0_active { + mux { + pins = "gpio101"; + function = "i2s0_data0"; + }; + + config { + pins = "gpio101"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_mi2s_sd1 { + pri_mi2s_sd1_sleep: pri_mi2s_sd1_sleep { + mux { + pins = "gpio111"; + function = "gpio"; + }; + + config { + pins = "gpio111"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_sd1_active: pri_mi2s_sd1_active { + mux { + pins = "gpio111"; + function = "i2s0_data1"; + }; + + config { + pins = "gpio111"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + /* WSA speaker reset pins */ + spkr_1_sd_n { + spkr_1_sd_n_sleep: spkr_1_sd_n_sleep { + mux { + pins = "gpio105"; + function = "gpio"; + }; + + config { + pins = "gpio105"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + + spkr_1_sd_n_active: spkr_1_sd_n_active { + mux { + pins = "gpio105"; + function = "gpio"; + }; + + config { + pins = "gpio105"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; + + spkr_1_1_sd_n { + spkr_1_1_sd_n_sleep: spkr_1_1_sd_n_sleep { + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + + spkr_1_1_sd_n_active: spkr_1_1_sd_n_active { + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; + + spkr_2_sd_n { + spkr_2_sd_n_sleep: spkr_2_sd_n_sleep { + mux { + pins = "gpio106"; + function = "gpio"; + }; + + config { + pins = "gpio106"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + + spkr_2_sd_n_active: spkr_2_sd_n_active { + mux { + pins = "gpio106"; + function = "gpio"; + }; + + config { + pins = "gpio106"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; + + /* WCD reset pin */ + wcd_reset_active: wcd_reset_active { + mux { + pins = "gpio102"; + function = "gpio"; + }; + + config { + pins = "gpio102"; + drive-strength = <16>; + output-high; + }; + }; + + wcd_reset_sleep: wcd_reset_sleep { + mux { + pins = "gpio102"; + function = "gpio"; + }; + + config { + pins = "gpio102"; + drive-strength = <16>; + bias-disable; + output-low; + }; + }; + + qupv3_se3_2uart_pins: qupv3_se3_2uart_pins { + qupv3_se3_2uart_tx_active: qupv3_se3_2uart_tx_active { + mux { + pins = "gpio22"; + function = "qup0_se3_l2"; + }; + + config { + pins = "gpio22"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se3_2uart_rx_active: qupv3_se3_2uart_rx_active { + mux { + pins = "gpio23"; + function = "qup0_se3_l3"; + }; + + config { + pins = "gpio23"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se3_2uart_sleep: qupv3_se3_2uart_sleep { + mux { + pins = "gpio22", "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio22", "gpio23"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se11_4uart_pins: qupv3_se11_4uart_pins { + qupv3_se11_default_cts: qupv3_se11_default_cts { + mux { + pins = "gpio14"; + function = "gpio"; + }; + + config { + pins = "gpio14"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se11_default_rts: qupv3_se11_default_rts { + mux { + pins = "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio15"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se11_default_tx: qupv3_se11_default_tx { + mux { + pins = "gpio16"; + function = "gpio"; + }; + + config { + pins = "gpio16"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se11_default_rx: qupv3_se11_default_rx { + mux { + pins = "gpio17"; + function = "gpio"; + }; + + config { + pins = "gpio17"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se11_cts: qupv3_se11_cts { + mux { + pins = "gpio14"; + function = "qup1_se5_l0"; + }; + + config { + pins = "gpio14"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se11_rts: qupv3_se11_rts { + mux { + pins = "gpio15"; + function = "qup1_se5_l1"; + }; + + config { + pins = "gpio15"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se11_tx: qupv3_se11_tx { + mux { + pins = "gpio16"; + function = "qup1_se5_l2"; + }; + + config { + pins = "gpio16"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se11_rx: qupv3_se11_rx { + mux { + pins = "gpio17"; + function = "qup1_se5_l3"; + }; + + config { + pins = "gpio17"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se0_i2c_pins: qupv3_se0_i2c_pins { + qupv3_se0_i2c_sda_active: qupv3_se0_i2c_sda_active { + mux { + pins = "gpio28"; + function = "qup0_se0_l0"; + }; + + config { + pins = "gpio28"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se0_i2c_scl_active: qupv3_se0_i2c_scl_active { + mux { + pins = "gpio29"; + function = "qup0_se0_l1"; + }; + + config { + pins = "gpio29"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep { + mux { + pins = "gpio28", "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio28", "gpio29"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se0_spi_pins: qupv3_se0_spi_pins { + qupv3_se0_spi_miso_active: qupv3_se0_spi_miso_active { + mux { + pins = "gpio28"; + function = "qup0_se0_l0"; + }; + + config { + pins = "gpio28"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se0_spi_mosi_active: qupv3_se0_spi_mosi_active { + mux { + pins = "gpio29"; + function = "qup0_se0_l1"; + }; + + config { + pins = "gpio29"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se0_spi_clk_active: qupv3_se0_spi_clk_active { + mux { + pins = "gpio30"; + function = "qup0_se0_l2"; + }; + + config { + pins = "gpio30"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se0_spi_cs_active: qupv3_se0_spi_cs_active { + mux { + pins = "gpio31"; + function = "qup0_se0_l3"; + }; + + config { + pins = "gpio31"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se0_spi_sleep: qupv3_se0_spi_sleep { + mux { + pins = "gpio28", "gpio29", + "gpio30", "gpio31"; + function = "gpio"; + }; + + config { + pins = "gpio28", "gpio29", + "gpio30", "gpio31"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se1_i2c_pins: qupv3_se1_i2c_pins { + qupv3_se1_i2c_sda_active: qupv3_se1_i2c_sda_active { + mux { + pins = "gpio0"; + function = "qup0_se1_l0"; + }; + + config { + pins = "gpio0"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se1_i2c_scl_active: qupv3_se1_i2c_scl_active { + mux { + pins = "gpio1"; + function = "qup0_se1_l1"; + }; + + config { + pins = "gpio1"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep { + mux { + pins = "gpio0", "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se1_spi_pins: qupv3_se1_spi_pins { + qupv3_se1_spi_miso_active: qupv3_se1_spi_miso_active { + mux { + pins = "gpio0"; + function = "qup0_se1_l0"; + }; + + config { + pins = "gpio0"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se1_spi_mosi_active: qupv3_se1_spi_mosi_active { + mux { + pins = "gpio1"; + function = "qup0_se1_l1"; + }; + + config { + pins = "gpio1"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se1_spi_clk_active: qupv3_se1_spi_clk_active { + mux { + pins = "gpio2"; + function = "qup0_se1_l2"; + }; + + config { + pins = "gpio2"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se1_spi_cs_active: qupv3_se1_spi_cs_active { + mux { + pins = "gpio3"; + function = "qup0_se1_l3"; + }; + + config { + pins = "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se1_spi_sleep: qupv3_se1_spi_sleep { + mux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se2_i2c_pins: qupv3_se2_i2c_pins { + qupv3_se2_i2c_sda_active: qupv3_se2_i2c_sda_active { + mux { + pins = "gpio24"; + function = "qup0_se2_l0"; + }; + + config { + pins = "gpio24"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se2_i2c_scl_active: qupv3_se2_i2c_scl_active { + mux { + pins = "gpio25"; + function = "qup0_se2_l1"; + }; + + config { + pins = "gpio25"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep { + mux { + pins = "gpio24", "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio24", "gpio25"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se2_spi_pins: qupv3_se2_spi_pins { + qupv3_se2_spi_miso_active: qupv3_se2_spi_miso_active { + mux { + pins = "gpio24"; + function = "qup0_se2_l0"; + }; + + config { + pins = "gpio24"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_mosi_active: qupv3_se2_spi_mosi_active { + mux { + pins = "gpio25"; + function = "qup0_se2_l1"; + }; + + config { + pins = "gpio25"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_clk_active: qupv3_se2_spi_clk_active { + mux { + pins = "gpio34"; + function = "qup1_se2_l2"; + }; + + config { + pins = "gpio34"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_cs_active: qupv3_se2_spi_cs_active { + mux { + pins = "gpio35"; + function = "qup0_se2_l3"; + }; + + config { + pins = "gpio35"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_sleep: qupv3_se2_spi_sleep { + mux { + pins = "gpio24", "gpio25", + "gpio34", "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio24", "gpio25", + "gpio34", "gpio35"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se4_i2c_pins: qupv3_se4_i2c_pins { + qupv3_se4_i2c_sda_active: qupv3_se4_i2c_sda_active { + mux { + pins = "gpio26"; + function = "qup0_se4_l0"; + }; + + config { + pins = "gpio26"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se4_i2c_scl_active: qupv3_se4_i2c_scl_active { + mux { + pins = "gpio27"; + function = "qup0_se4_l1"; + }; + + config { + pins = "gpio27"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep { + mux { + pins = "gpio26", "gpio27"; + function = "gpio"; + }; + + config { + pins = "gpio26", "gpio27"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se4_spi_pins: qupv3_se4_spi_pins { + qupv3_se4_spi_miso_active: qupv3_se4_spi_miso_active { + mux { + pins = "gpio26"; + function = "qup0_se4_l0"; + }; + + config { + pins = "gpio26"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se4_spi_mosi_active: qupv3_se4_spi_mosi_active { + mux { + pins = "gpio27"; + function = "qup0_se4_l1"; + }; + + config { + pins = "gpio27"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se4_spi_clk_active: qupv3_se4_spi_clk_active { + mux { + pins = "gpio34"; + function = "qup0_se4_l2"; + }; + + config { + pins = "gpio34"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se4_spi_cs_active: qupv3_se4_spi_cs_active { + mux { + pins = "gpio35"; + function = "qup0_se4_l3"; + }; + + config { + pins = "gpio35"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se4_spi_sleep: qupv3_se4_spi_sleep { + mux { + pins = "gpio26", "gpio27", + "gpio34", "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio26", "gpio27", + "gpio34", "gpio35"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se5_i2c_pins: qupv3_se5_i2c_pins { + qupv3_se5_i2c_sda_active: qupv3_se5_i2c_sda_active { + mux { + pins = "gpio32"; + function = "qup0_se5_l0"; + }; + + config { + pins = "gpio32"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se5_i2c_scl_active: qupv3_se5_i2c_scl_active { + mux { + pins = "gpio33"; + function = "qup0_se5_l1"; + }; + + config { + pins = "gpio33"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep { + mux { + pins = "gpio32", "gpio33"; + function = "gpio"; + }; + + config { + pins = "gpio32", "gpio33"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se5_spi_pins: qupv3_se5_spi_pins { + qupv3_se5_spi_miso_active: qupv3_se5_spi_miso_active { + mux { + pins = "gpio32"; + function = "qup0_se5_l0"; + }; + + config { + pins = "gpio32"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se5_spi_mosi_active: qupv3_se5_spi_mosi_active { + mux { + pins = "gpio33"; + function = "qup0_se5_l1"; + }; + + config { + pins = "gpio33"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se5_spi_clk_active: qupv3_se5_spi_clk_active { + mux { + pins = "gpio34"; + function = "qup0_se5_l2"; + }; + + config { + pins = "gpio34"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se5_spi_cs_active: qupv3_se5_spi_cs_active { + mux { + pins = "gpio35"; + function = "qup0_se5_l3"; + }; + + config { + pins = "gpio35"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se5_spi_sleep: qupv3_se5_spi_sleep { + mux { + pins = "gpio32", "gpio33", + "gpio34", "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio32", "gpio33", + "gpio34", "gpio35"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se6_i2c_pins: qupv3_se6_i2c_pins { + qupv3_se6_i2c_sda_active: qupv3_se6_i2c_sda_active { + mux { + pins = "gpio4"; + function = "qup1_se0_l0"; + }; + + config { + pins = "gpio4"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se6_i2c_scl_active: qupv3_se6_i2c_scl_active { + mux { + pins = "gpio5"; + function = "qup1_se0_l1"; + }; + + config { + pins = "gpio5"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep { + mux { + pins = "gpio4", "gpio5"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se6_spi_pins: qupv3_se6_spi_pins { + qupv3_se6_spi_miso_active: qupv3_se6_spi_miso_active { + mux { + pins = "gpio4"; + function = "qup1_se0_l0"; + }; + + config { + pins = "gpio4"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se6_spi_mosi_active: qupv3_se6_spi_mosi_active { + mux { + pins = "gpio5"; + function = "qup1_se0_l1"; + }; + + config { + pins = "gpio5"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se6_spi_clk_active: qupv3_se6_spi_clk_active { + mux { + pins = "gpio6"; + function = "qup1_se0_l2"; + }; + + config { + pins = "gpio6"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se6_spi_cs_active: qupv3_se6_spi_cs_active { + mux { + pins = "gpio7"; + function = "qup1_se0_l3"; + }; + + config { + pins = "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se6_spi_sleep: qupv3_se6_spi_sleep { + mux { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se7_i2c_pins: qupv3_se7_i2c_pins { + qupv3_se7_i2c_sda_active: qupv3_se7_i2c_sda_active { + mux { + pins = "gpio8"; + function = "qup1_se1_l0"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se7_i2c_scl_active: qupv3_se7_i2c_scl_active { + mux { + pins = "gpio9"; + function = "qup1_se1_l1"; + }; + + config { + pins = "gpio9"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep { + mux { + pins = "gpio8", "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se7_spi_pins: qupv3_se7_spi_pins { + qupv3_se7_spi_miso_active: qupv3_se7_spi_miso_active { + mux { + pins = "gpio8"; + function = "qup1_se1_l0"; + }; + + config { + pins = "gpio8"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se7_spi_mosi_active: qupv3_se7_spi_mosi_active { + mux { + pins = "gpio9"; + function = "qup1_se1_l1"; + }; + + config { + pins = "gpio9"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se7_spi_clk_active: qupv3_se7_spi_clk_active { + mux { + pins = "gpio6"; + function = "qup1_se1_l2"; + }; + + config { + pins = "gpio6"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se7_spi_cs_active: qupv3_se7_spi_cs_active { + mux { + pins = "gpio7"; + function = "qup1_se1_l3"; + }; + + config { + pins = "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se7_spi_sleep: qupv3_se7_spi_sleep { + mux { + pins = "gpio8", "gpio9", + "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9", + "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se8_i2c_pins: qupv3_se8_i2c_pins { + qupv3_se8_i2c_sda_active: qupv3_se8_i2c_sda_active { + mux { + pins = "gpio18"; + function = "qup1_se2_l0"; + }; + + config { + pins = "gpio18"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se8_i2c_scl_active: qupv3_se8_i2c_scl_active { + mux { + pins = "gpio19"; + function = "qup1_se2_l1"; + }; + + config { + pins = "gpio19"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep { + mux { + pins = "gpio18", "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio18", "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se8_spi_pins: qupv3_se8_spi_pins { + qupv3_se8_spi_miso_active: qupv3_se8_spi_miso_active { + mux { + pins = "gpio18"; + function = "qup1_se2_l0"; + }; + + config { + pins = "gpio18"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se8_spi_mosi_active: qupv3_se8_spi_mosi_active { + mux { + pins = "gpio19"; + function = "qup1_se2_l1"; + }; + + config { + pins = "gpio19"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se8_spi_clk_active: qupv3_se8_spi_clk_active { + mux { + pins = "gpio20"; + function = "qup1_se2_l2"; + }; + + config { + pins = "gpio20"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se8_spi_cs_active: qupv3_se8_spi_cs_active { + mux { + pins = "gpio21"; + function = "qup1_se2_l3"; + }; + + config { + pins = "gpio21"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se8_spi_sleep: qupv3_se8_spi_sleep { + mux { + pins = "gpio18", "gpio19", + "gpio20", "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio18", "gpio19", + "gpio20", "gpio21"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se9_i2c_pins: qupv3_se9_i2c_pins { + qupv3_se9_i2c_sda_active: qupv3_se9_i2c_sda_active { + mux { + pins = "gpio10"; + function = "qup1_se3_l0"; + }; + + config { + pins = "gpio10"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se9_i2c_scl_active: qupv3_se9_i2c_scl_active { + mux { + pins = "gpio11"; + function = "qup1_se3_l1"; + }; + + config { + pins = "gpio11"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep { + mux { + pins = "gpio10", "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio10", "gpio11"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se9_spi_pins: qupv3_se9_spi_pins { + qupv3_se9_spi_miso_active: qupv3_se9_spi_miso_active { + mux { + pins = "gpio10"; + function = "qup1_se3_l0"; + }; + + config { + pins = "gpio10"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se9_spi_mosi_active: qupv3_se9_spi_mosi_active { + mux { + pins = "gpio11"; + function = "qup1_se3_l1"; + }; + + config { + pins = "gpio11"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se9_spi_clk_active: qupv3_se9_spi_clk_active { + mux { + pins = "gpio12"; + function = "qup1_se3_l2"; + }; + + config { + pins = "gpio12"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se9_spi_cs_active: qupv3_se9_spi_cs_active { + mux { + pins = "gpio13"; + function = "qup1_se3_l3"; + }; + + config { + pins = "gpio13"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se9_spi_sleep: qupv3_se9_spi_sleep { + mux { + pins = "gpio10", "gpio11", + "gpio12", "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio10", "gpio11", + "gpio12", "gpio13"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + + /* touchscreen pins */ + pmx_ts_active { + ts_active: ts_active { + mux { + pins = "gpio12", "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio12", "gpio13"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + ts_spi_active: ts_spi_active { + mux { + pins = "gpio64", "gpio65"; + function = "gpio"; + }; + + config { + pins = "gpio64", "gpio65"; + drive-strength = <8>; + bias-pull-up; + }; + }; + }; + + pmx_ts_reset_suspend { + ts_reset_suspend: ts_reset_suspend { + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + ts_spi_reset_suspend: ts_spi_reset_suspend { + mux { + pins = "gpio64"; + function = "gpio"; + }; + + config { + pins = "gpio64"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_int_suspend { + ts_int_suspend: ts_int_suspend { + mux { + pins = "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio13"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + ts_spi_int_suspend: ts_spi_int_suspend { + mux { + pins = "gpio65"; + function = "gpio"; + }; + + config { + pins = "gpio65"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_release { + ts_release: ts_release { + mux { + pins = "gpio12", "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio12", "gpio13"; + drive-strength = <2>; + bias-disable; + }; + }; + + ts_spi_release: ts_spi_release { + mux { + pins = "gpio64", "gpio65"; + function = "gpio"; + }; + + config { + pins = "gpio64", "gpio65"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + sdc1_on: sdc1_on { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_off: sdc1_off { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + trigout_a: trigout_a { + mux { + pins = "gpio26"; + function = "qdss_cti"; + }; + + config { + pins = "gpio26"; + drive-strength = <2>; + bias-disable; + }; + }; + + sdc2_on: sdc2_on { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sd-cd { + pins = "gpio107"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_off: sdc2_off { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + + sd-cd { + pins = "gpio107"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + usb_phy_ps: usb_phy_ps { + usb3phy_portselect_default: usb3phy_portselect_default { + mux { + pins = "gpio100"; + function = "usb0_phy_ps"; + }; + + config { + pins = "gpio100"; + bias-disable; + drive-strength = <2>; + }; + }; + }; + }; + +}; diff --git a/qcom/parrot-pm7250b.dtsi b/qcom/parrot-pm7250b.dtsi new file mode 100644 index 00000000..fac8b00d --- /dev/null +++ b/qcom/parrot-pm7250b.dtsi @@ -0,0 +1,341 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include "pm7250b.dtsi" + +&soc { + qcom,pmic_glink { + status = "okay"; + }; + + qcom,pmic_glink_log { + compatible = "qcom,pmic-glink"; + qcom,pmic-glink-channel = "PMIC_LOGS_ADSP_APPS"; + + qcom,battery_debug { + compatible = "qcom,battery-debug"; + }; + + qcom,charger_ulog_glink { + compatible = "qcom,charger-ulog-glink"; + }; + + spmi_glink_debug: qcom,spmi_glink_debug { + compatible = "qcom,spmi-glink-debug"; + #address-cells = <1>; + #size-cells = <0>; + depends-on-supply = <&spmi1_bus>; + + /* Primary SPMI bus */ + spmi@0 { + reg = <0>; + #address-cells = <2>; + #size-cells = <0>; + + qcom,pm7250b-debug@8 { + compatible = "qcom,spmi-pmic"; + reg = <8 SPMI_USID>; + qcom,can-sleep; + }; + }; + + /* Secondary SPMI bus */ + spmi@1 { + reg = <1>; + #address-cells = <2>; + #size-cells = <0>; + + smb1394_glink_debug: qcom,smb1394-debug@9 { + compatible = "qcom,spmi-pmic"; + reg = <9 SPMI_USID>; + qcom,can-sleep; + }; + + qcom,smb1394-debug@b { + compatible = "qcom,spmi-pmic"; + reg = <11 SPMI_USID>; + qcom,can-sleep; + }; + + qcom,smb1394-debug@c { + compatible = "qcom,spmi-pmic"; + reg = <12 SPMI_USID>; + qcom,can-sleep; + }; + }; + }; + }; +}; + +&glink_edge { + qcom,pmic_glink_rpmsg { + qcom,glink-channels = "PMIC_RTR_ADSP_APPS"; + }; + + qcom,pmic_glink_log_rpmsg { + qcom,glink-channels = "PMIC_LOGS_ADSP_APPS"; + qcom,intents = <0x800 5 + 0xc00 3 + 0x2000 1>; + }; +}; + +&battery_charger { + status = "okay"; +}; + +&ucsi { + status = "okay"; +}; + +&altmode { + status = "okay"; +}; + +&spmi0_debug_bus { + depends-on2-supply = <&smb1394_glink_debug>; + + qcom,pm7250b-debug@8 { + compatible = "qcom,spmi-pmic"; + reg = <8 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pm7250b-debug@9 { + compatible = "qcom,spmi-pmic"; + reg = <9 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; +}; + +&pm7250b_2 { + /* Slave ID - 8 */ + reg = <8 SPMI_USID>; +}; + +&pm7250b_3 { + /* Slave ID - 9 */ + reg = <9 SPMI_USID>; +}; + +&pm7250b_clkdiv { + clocks = <&rpmhcc RPMH_CXO_CLK>; +}; + +&pm7250b_vadc { + interrupts = <0x8 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + + smb1390_therm@e { + qcom,scale-fn-type = ; + }; + + pm7250b_usb_conn_therm { + reg = ; + label = "pm7250b_usb_conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pm7250b_smb_skin_therm { + reg = ; + label = "pm7250b_smb_skin_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm7250b_adc_tm { + interrupts = <0x8 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + io-channels = <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>, + <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>; + + pm7250b_usb_conn_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pm7250b_smb_skin_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&thermal_zones { + socd { + cooling-maps { + socd_apc1 { + trip = <&socd_trip>; + cooling-device = <&APC1_pause 1 1>; + }; + + socd_cdsp1 { + trip = <&socd_trip>; + cooling-device = <&cdsp_sw 4 4>; + }; + + socd_gpu0 { + trip = <&socd_trip>; + cooling-device = <&msm_gpu 2 2>; + }; + }; + }; + + pm7250b-ibat-lvl0 { + trips { + ibat-lvl0 { + temperature = <6000>; + }; + }; + }; + + pm7250b-ibat-lvl1 { + trips { + ibat-lvl1 { + temperature = <7500>; + }; + }; + }; + + pm7250b-bcl-lvl0 { + cooling-maps { + vbat_lte0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_lte_dsc 8 8>; + }; + + vbat_nr0_scg { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_nr_scg_dsc 3 3>; + }; + + vbat_nr0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_nr_dsc 6 6>; + }; + + vbat_cdsp0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cdsp_sw 2 2>; + }; + + vbat_cpu_5 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cpu5_pause 1 1>; + }; + + vbat_gpu0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&msm_gpu 1 1>; + }; + }; + }; + + pm7250b-bcl-lvl1 { + cooling-maps { + vbat_lte1 { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_lte_dsc 10 10>; + }; + + vbat_nr1_scg { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_nr_scg_dsc 10 10>; + }; + + vbat_nr1 { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_nr_dsc 9 9>; + }; + + vbat_cdsp1 { + trip = <&b_bcl_lvl1>; + cooling-device = <&cdsp_sw 4 4>; + }; + + vbat_cpu_6_7 { + trip = <&b_bcl_lvl1>; + cooling-device = <&cpu_6_7_pause 1 1>; + }; + + vbat_gpu1 { + trip = <&b_bcl_lvl1>; + cooling-device = <&msm_gpu 2 2>; + }; + }; + }; + + pm7250b-bcl-lvl2 { + cooling-maps { + vbat_cdsp2 { + trip = <&b_bcl_lvl2>; + cooling-device = <&cdsp_sw 5 THERMAL_NO_LIMIT>; + }; + + vbat_gpu2 { + trip = <&b_bcl_lvl2>; + cooling-device = <&msm_gpu 3 THERMAL_NO_LIMIT>; + }; + }; + }; + + sys-therm-7 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm7250b_adc_tm ADC5_AMUX_THM3_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-therm-6 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm7250b_adc_tm ADC5_AMUX_THM1_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; + + +&pm7250b_tz { + interrupts = <0x8 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; +}; + +&pm7250b_bcl { + interrupts = <0x8 0x1d 0x0 IRQ_TYPE_EDGE_RISING>, + <0x8 0x1d 0x1 IRQ_TYPE_EDGE_RISING>, + <0x8 0x1d 0x2 IRQ_TYPE_EDGE_RISING>; +}; diff --git a/qcom/parrot-pm8350b.dtsi b/qcom/parrot-pm8350b.dtsi new file mode 100644 index 00000000..c685a111 --- /dev/null +++ b/qcom/parrot-pm8350b.dtsi @@ -0,0 +1,376 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include + +&pm6150a_amoled { + /delete-node/ oledb@e000; + /delete-node/ ab@de00; + /delete-node/ ibb@dc00; +}; + +#include "pm8350b.dtsi" + +&soc { + qcom,pmic_glink { + status = "okay"; + }; + + qcom,pmic_glink_log { + compatible = "qcom,pmic-glink"; + qcom,pmic-glink-channel = "PMIC_LOGS_ADSP_APPS"; + + qcom,battery_debug { + compatible = "qcom,battery-debug"; + }; + + qcom,charger_ulog_glink { + compatible = "qcom,charger-ulog-glink"; + }; + + spmi_glink_debug: qcom,spmi_glink_debug { + compatible = "qcom,spmi-glink-debug"; + #address-cells = <1>; + #size-cells = <0>; + depends-on-supply = <&spmi1_bus>; + + /* Primary SPMI bus */ + spmi@0 { + reg = <0>; + #address-cells = <2>; + #size-cells = <0>; + + qcom,pm8350b-debug@3 { + compatible = "qcom,spmi-pmic"; + reg = <3 SPMI_USID>; + qcom,can-sleep; + }; + }; + + /* Secondary SPMI bus */ + spmi@1 { + reg = <1>; + #address-cells = <2>; + #size-cells = <0>; + + smb1394_glink_debug: qcom,smb1394-debug@9 { + compatible = "qcom,spmi-pmic"; + reg = <9 SPMI_USID>; + qcom,can-sleep; + }; + + qcom,smb1394-debug@b { + compatible = "qcom,spmi-pmic"; + reg = <11 SPMI_USID>; + qcom,can-sleep; + }; + + qcom,smb1394-debug@c { + compatible = "qcom,spmi-pmic"; + reg = <12 SPMI_USID>; + qcom,can-sleep; + }; + }; + }; + }; +}; + +&glink_edge { + qcom,pmic_glink_rpmsg { + qcom,glink-channels = "PMIC_RTR_ADSP_APPS"; + }; + + qcom,pmic_glink_log_rpmsg { + qcom,glink-channels = "PMIC_LOGS_ADSP_APPS"; + qcom,intents = <0x800 5 + 0xc00 3 + 0x2000 1>; + }; +}; + +&battery_charger { + status = "okay"; +}; + +&ucsi { + status = "okay"; +}; + +&altmode { + status = "okay"; +}; + +&spmi0_debug_bus { + depends-on2-supply = <&smb1394_glink_debug>; + + qcom,pm8350b-debug@3 { + compatible = "qcom,spmi-pmic"; + reg = <3 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; +}; + +&apps_rsc_drv2 { + rpmh-regulator-ldod1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldod1"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L1D: pm8350b_l1: regulator-pm8350b-l1 { + regulator-name = "pm8350b_l1"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1296000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; +}; + +&pmk8350_sdam_2 { + hap_cl_brake: cl_brake@7c { + reg = <0x7c 0x1>; + bits = <0 8>; + }; +}; + +&pm8350b_haptics { + nvmem-cell-names = "hap_cl_brake"; + nvmem-cells = <&hap_cl_brake>; + nvmem-names = "hap_cfg_sdam"; + nvmem = <&pmk8350_sdam_46>; + qcom,pbs-client = <&pm8350b_pbs2>; +}; + +&pmk8350_vadc { + pm8350b_ref_gnd { + reg = ; + label = "pm8350b_ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + pm8350b_vref_1p25 { + reg = ; + label = "pm8350b_vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + pm8350b_die_temp { + reg = ; + label = "pm8350b_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + pm8350b_vph_pwr { + reg = ; + label = "pm8350b_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + pm8350b_vbat_sns { + reg = ; + label = "pm8350b_vbat_sns"; + qcom,pre-scaling = <1 3>; + }; + + pm8350b_chg_temp { + reg = ; + label = "pm8350b_chg_temp"; + qcom,pre-scaling = <1 1>; + }; + + pm8350b_iin_fb { + reg = ; + label = "pm8350b_iin_fb"; + qcom,pre-scaling = <32 100>; + }; + + pm8350b_ichg_fb { + reg = ; + label = "pm8350b_ichg_fb"; + qcom,pre-scaling = <1000 305185>; + }; + + pm8350b_usb_in_v_div_16 { + reg = ; + label = "pm8350b_usb_in_v_div_16"; + qcom,pre-scaling = <1 16>; + }; + + smb139x_1_smb_temp { + reg = ; + label = "smb139x_1_smb_temp"; + qcom,hw-settle-time = <200>; + }; + + smb139x_1_ichg_smb { + reg = ; + label = "smb139x_1_ichg_smb"; + qcom,hw-settle-time = <200>; + }; + + smb139x_1_iin_smb { + reg = ; + label = "smb139x_1_iin_smb"; + qcom,hw-settle-time = <200>; + }; + + smb139x_2_smb_temp { + reg = ; + label = "smb139x_2_smb_temp"; + qcom,hw-settle-time = <200>; + }; + + smb139x_2_ichg_smb { + reg = ; + label = "smb139x_2_ichg_smb"; + qcom,hw-settle-time = <200>; + }; + + smb139x_2_iin_smb { + reg = ; + label = "smb139x_2_iin_smb"; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8350b_tz { + io-channels = <&pmk8350_vadc PM8350B_ADC7_DIE_TEMP>; + io-channel-names = "thermal"; +}; + +&thermal_zones { + socd { + trips { + socd-trip { + temperature = <90>; + hysteresis = <1>; + }; + }; + + cooling-maps { + socd_apc1 { + trip = <&socd_trip>; + cooling-device = <&APC1_pause 1 1>; + }; + + socd_cdsp1 { + trip = <&socd_trip>; + cooling-device = <&cdsp_sw 4 4>; + }; + + socd_gpu0 { + trip = <&socd_trip>; + cooling-device = <&msm_gpu 2 2>; + }; + }; + }; + + pm8350b-ibat-lvl0 { + trips { + ibat-lvl0 { + temperature = <6000>; + }; + }; + }; + + pm8350b-ibat-lvl1 { + trips { + ibat-lvl1 { + temperature = <7500>; + }; + }; + }; + + pm8350b-bcl-lvl0 { + cooling-maps { + vbat_lte0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_lte_dsc 8 8>; + }; + + vbat_nr0_scg { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_nr_scg_dsc 3 3>; + }; + + vbat_nr0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_nr_dsc 6 6>; + }; + + vbat_cdsp0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cdsp_sw 2 2>; + }; + + vbat_cpu_5 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cpu5_pause 1 1>; + }; + + vbat_gpu0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&msm_gpu 1 1>; + }; + }; + }; + + pm8350b-bcl-lvl1 { + cooling-maps { + vbat_lte1 { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_lte_dsc 10 10>; + }; + + vbat_nr1_scg { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_nr_scg_dsc 10 10>; + }; + + vbat_nr1 { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_nr_dsc 9 9>; + }; + + vbat_cdsp1 { + trip = <&b_bcl_lvl1>; + cooling-device = <&cdsp_sw 4 4>; + }; + + vbat_cpu_6_7 { + trip = <&b_bcl_lvl1>; + cooling-device = <&cpu_6_7_pause 1 1>; + }; + + vbat_gpu1 { + trip = <&b_bcl_lvl1>; + cooling-device = <&msm_gpu 2 2>; + }; + }; + }; + + pm8350b-bcl-lvl2 { + cooling-maps { + vbat_cdsp2 { + trip = <&b_bcl_lvl2>; + cooling-device = <&cdsp_sw 5 THERMAL_NO_LIMIT>; + }; + + vbat_gpu2 { + trip = <&b_bcl_lvl2>; + cooling-device = <&msm_gpu 3 THERMAL_NO_LIMIT>; + }; + }; + }; +}; diff --git a/qcom/parrot-pmic-overlay.dtsi b/qcom/parrot-pmic-overlay.dtsi new file mode 100644 index 00000000..3a2c1a20 --- /dev/null +++ b/qcom/parrot-pmic-overlay.dtsi @@ -0,0 +1,700 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include + +#define PMR735A_SID 6 + +#include "pmk8350.dtsi" +#include "pm6450.dtsi" +#include "pm6150l.dtsi" +#include "pmr735a.dtsi" + +&soc { + reboot_reason { + compatible = "qcom,reboot-reason"; + nvmem-cells = <&restart_reason>; + nvmem-cell-names = "restart_reason"; + }; + + pmic-pon-log { + compatible = "qcom,pmic-pon-log"; + nvmem = <&pmk8350_sdam_5>; + nvmem-names = "pon_log"; + }; +}; + +&pmk8350 { + /delete-node/ pon_pbs@800; + /delete-node/ pon_hlos@1300; + + pon_hlos@1300 { + compatible = "qcom,pm8998-pon"; + reg = <0x1300>, <0x800>; + reg-names = "pon_hlos", "pon_pbs"; + qcom,log-kpd-event; + + pwrkey { + compatible = "qcom,pmk8350-pwrkey"; + interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + }; + + resin { + compatible = "qcom,pmk8350-resin"; + interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + }; + }; +}; + +&pmk8350_vadc { + pinctrl-names = "default"; + pinctrl-0 = <&quiet_therm_default>; + + /delete-node/ pm8350_ref_gnd; + /delete-node/ pm8350_vref_1p25; + /delete-node/ pm8350_die_temp; + /delete-node/ pm8350_vph_pwr; + + /delete-node/ pm8350b_ref_gnd; + /delete-node/ pm8350b_vref_1p25; + /delete-node/ pm8350b_die_temp; + /delete-node/ pm8350b_vph_pwr; + /delete-node/ pm8350b_vbat_sns; + + /delete-node/ pmr735b_ref_gnd; + /delete-node/ pmr735b_vref_1p25; + /delete-node/ pmr735b_die_temp; + + /* PM6450 Channel nodes */ + pm6450_ref_gnd { + reg = ; + label = "pm6450_ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + pm6450_vref_1p25 { + reg = ; + label = "pm6450_vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + pm6450_die_temp { + reg = ; + label = "pm6450_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + pm6450_quiet_therm { + reg = ; + label = "pm6450_quiet_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pmk8350_adc_tm { + io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>, + <&pmk8350_vadc PM6450_ADC7_AMUX1_GPIO2_100K_PU>; + + pmk8350_xo_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pm6450_quiet_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pmk8350_sdam_23 { + adc_scaling: scaling@bf { + reg = <0xbf 0x1>; + bits = <0 2>; + }; +}; + +&pmk8350_sdam_1 { + ufs_dev: ufs_dev@94 { + reg = <0x94 0x1>; + bits = <0 0>; + }; +}; + +&pm6450_gpios { + key_vol_up { + key_vol_up_default: key_vol_up_default { + pins = "gpio1"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; + }; + + quiet_therm { + quiet_therm_default: quiet_therm_default { + pins = "gpio2"; + bias-high-impedance; + }; + }; + + pm8010i_reset { + pm8010i_active: pm8010i_active { + pins = "gpio3"; + function = "normal"; + bias-disable; + output-high; + power-source = <0>; + }; + }; + + pm8010j_reset { + pm8010j_active: pm8010j_active { + pins = "gpio4"; + function = "normal"; + bias-disable; + output-high; + power-source = <0>; + }; + }; +}; + +&pm6150l_revid { + status = "disabled"; +}; + +&pm6150l_4 { + qcom,power-on@800 { + status = "disabled"; + }; +}; + +&pm6150l_clkdiv { + clocks = <&rpmhcc RPMH_CXO_CLK>; +}; + +&pm6150l_vadc { + pinctrl-names = "default"; + pinctrl-0 = <&ufs_therm_default &wide_rfc_therm_default>; + + pa_therm2 { + reg = ; + label = "pa_therm2"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm1 { + reg = ; + label = "pa_therm1"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + ufs_therm { + reg = ; + label = "ufs_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + wide_rfc_therm { + reg = ; + label = "wide_rfc_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm6150l_gpios { + ufs_therm { + ufs_therm_default: ufs_therm_default { + pins = "gpio5"; + bias-high-impedance; + }; + }; + + wide_rfc_therm { + wide_rfc_therm_default: wide_rfc_therm_default { + pins = "gpio7"; + bias-high-impedance; + }; + }; +}; + +&pm6150l_adc_tm { + io-channels = <&pm6150l_vadc ADC5_AMUX_THM1_100K_PU>, + <&pm6150l_vadc ADC5_AMUX_THM3_100K_PU>, + <&pm6150l_vadc ADC5_GPIO1_100K_PU>, + <&pm6150l_vadc ADC5_GPIO3_100K_PU>; + + /* Channel nodes */ + pa_therm2 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm1 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + ufs_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + wide_rfc_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&flash_led { + status = "ok"; + qcom,use-qti-battery-interface; +}; + +&pmr735a_spmi { + reg = <6 SPMI_USID>; +}; + +&pmr735a_tz { + interrupts = <0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels = <&pmk8350_vadc PMR735A_ADC7_DIE_TEMP>; + io-channel-names = "thermal"; +}; + +&thermal_zones { + xo-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm PMK8350_ADC7_AMUX_THM1_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-therm-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm6150l_adc_tm ADC5_GPIO1_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-therm-2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm6150l_adc_tm ADC5_GPIO3_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-therm-3 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm PM6450_ADC7_AMUX1_GPIO2_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-therm-4 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm6150l_adc_tm ADC5_AMUX_THM1_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-therm-5 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm6150l_adc_tm ADC5_AMUX_THM3_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; + +/* + * Each QUP device that's a parent to PMIC must be listed as a critical device + * to GCC + */ +&gcc { + qcom,critical-devices = <&qupv3_se2_i2c>; +}; + +&qupv3_se2_i2c { + #address-cells = <1>; + #size-cells = <0>; + status = "ok"; + + pm8010i@8 { + compatible = "qcom,i2c-pmic"; + reg = <0x8>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pm8010i_active>; + + pm8010-chip@900 { + reg = <0x900>; + + PM8010I_EN: qcom,pm8008-chip-en { + regulator-name = "pm8010i-chip-en"; + }; + }; + + qcom,revid@100 { + reg = <0x100>; + }; + }; + + pm8010i@9 { + compatible = "qcom,i2c-pmic"; + reg = <0x9>; + #address-cells = <1>; + #size-cells = <0>; + + qcom,pm8010i-regulator { + #address-cells = <1>; + #size-cells = <0>; + + pm8008_en-supply = <&PM8010I_EN>; + vdd_l1_l2-supply = <&S8B>; + vdd_l3_l4-supply = <&BOB>; + vdd_l5-supply = <&BOB>; + vdd_l6-supply = <&BOB>; + vdd_l7-supply = <&BOB>; + + L1I: pm8010i_l1: regulator@4000 { + reg = <0x4000>; + regulator-name = "pm8010i_l1"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + qcom,min-dropout-voltage = <88000>; + qcom,hpm-min-load = <30000>; + }; + + L2I: pm8010i_l2: regulator@4100 { + reg = <0x4100>; + regulator-name = "pm8010i_l2"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1150000>; + qcom,min-dropout-voltage = <64000>; + qcom,hpm-min-load = <30000>; + }; + + L3I: pm8010i_l3: regulator@4200 { + reg = <0x4200>; + regulator-name = "pm8010i_l3"; + regulator-min-microvolt = <1328000>; + regulator-max-microvolt = <3000000>; + qcom,min-dropout-voltage = <176000>; + qcom,hpm-min-load = <0>; + }; + + L4I: pm8010i_l4: regulator@4300 { + reg = <0x4300>; + regulator-name = "pm8010i_l4"; + regulator-min-microvolt = <1376000>; + regulator-max-microvolt = <2900000>; + qcom,min-dropout-voltage = <128000>; + qcom,hpm-min-load = <0>; + }; + + L6I: pm8010i_l6: regulator@4500 { + reg = <0x4500>; + regulator-name = "pm8010i_l6"; + regulator-min-microvolt = <1376000>; + regulator-max-microvolt = <2900000>; + qcom,min-dropout-voltage = <128000>; + qcom,hpm-min-load = <0>; + }; + + L7I: pm8010i_l7: regulator@4600 { + reg = <0x4600>; + regulator-name = "pm8010i_l7"; + regulator-min-microvolt = <1248000>; + regulator-max-microvolt = <3000000>; + qcom,min-dropout-voltage = <256000>; + qcom,hpm-min-load = <0>; + }; + }; + }; + + pm8010j@c { + compatible = "qcom,i2c-pmic"; + reg = <0xc>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pm8010j_active>; + + pm8010-chip@900 { + reg = <0x900>; + + PM8010J_EN: qcom,pm8008-chip-en { + regulator-name = "pm8010j-chip-en"; + }; + }; + + qcom,revid@100 { + reg = <0x100>; + }; + }; + + pm8010j@d { + compatible = "qcom,i2c-pmic"; + reg = <0xd>; + #address-cells = <1>; + #size-cells = <0>; + + qcom,pm8010j-regulator { + #address-cells = <1>; + #size-cells = <0>; + + pm8008_en-supply = <&PM8010J_EN>; + vdd_l1_l2-supply = <&S8B>; + vdd_l3_l4-supply = <&S8E>; + vdd_l5-supply = <&BOB>; + vdd_l6-supply = <&BOB>; + vdd_l7-supply = <&BOB>; + + L1J: pm8010j_l1: regulator@4000 { + reg = <0x4000>; + regulator-name = "pm8010j_l1"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1150000>; + qcom,min-dropout-voltage = <48000>; + qcom,hpm-min-load = <30000>; + }; + + L3J: pm8010j_l3: regulator@4200 { + reg = <0x4200>; + regulator-name = "pm8010j_l3"; + regulator-min-microvolt = <1744000>; + regulator-max-microvolt = <1900000>; + qcom,min-dropout-voltage = <72000>; + qcom,hpm-min-load = <0>; + }; + + L4J: pm8010j_l4: regulator@4300 { + reg = <0x4300>; + regulator-name = "pm8010j_l4"; + regulator-min-microvolt = <1664000>; + regulator-max-microvolt = <1888000>; + qcom,min-dropout-voltage = <152000>; + qcom,hpm-min-load = <0>; + }; + + L6J: pm8010j_l6: regulator@4500 { + reg = <0x4500>; + regulator-name = "pm8010j_l6"; + regulator-min-microvolt = <1376000>; + regulator-max-microvolt = <2900000>; + qcom,min-dropout-voltage = <128000>; + qcom,hpm-min-load = <0>; + }; + }; + }; +}; + +&soc { + display_panel_vddio: display_gpio_regulator@1 { + compatible = "qti-regulator-fixed"; + regulator-name = "display_panel_vddio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <233>; + gpio = <&pm6150l_gpios 9 0>; + enable-active-high; + regulator-boot-on; + proxy-supply = <&display_panel_vddio>; + qcom,proxy-consumer-enable; + pinctrl-names = "default"; + pinctrl-0 = <&display_panel_vddio_default>; + }; + + display_panel_avdd: display_gpio_regulator@2 { + compatible = "qti-regulator-fixed"; + regulator-name = "display_panel_avdd"; + regulator-min-microvolt = <5500000>; + regulator-max-microvolt = <5500000>; + regulator-enable-ramp-delay = <233>; + gpio = <&pm6150l_gpios 4 0>; + enable-active-high; + regulator-boot-on; + proxy-supply = <&display_panel_avdd>; + qcom,proxy-consumer-enable; + pinctrl-names = "default"; + pinctrl-0 = <&display_panel_avdd_default>; + }; + + display_panel_extvdd: display_gpio_regulator@3 { + compatible = "qti-regulator-fixed"; + regulator-name = "display_panel_extvdd"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <233>; + gpio = <&pm6150l_gpios 3 0>; + enable-active-high; + regulator-boot-on; + proxy-supply = <&display_panel_extvdd>; + qcom,proxy-consumer-enable; + pinctrl-names = "default"; + pinctrl-0 = <&display_panel_extvdd_default>; + }; + + display_panel_ibb: display_panel_ibb_stub { + compatible = "qcom,stub-regulator"; + regulator-name = "display_panel_ibb"; + regulator-min-microvolt = <4600000>; + regulator-max-microvolt = <6000000>; + }; +}; + +&pm6150l_gpios { + display_panel_supply_ctrl { + display_panel_vddio_default: display_panel_vddio_default { + pins = "gpio9"; + function = "normal"; + input-disable; + output-enable; + bias-disable; + power-source = <0>; + qcom,drive-strength = <2>; + }; + + display_panel_avdd_default: display_panel_avdd_default { + pins = "gpio4"; + function = "normal"; + input-disable; + output-enable; + bias-disable; + power-source = <0>; + qcom,drive-strength = <2>; + }; + + display_panel_extvdd_default: display_panel_extvdd_default { + pins = "gpio3"; + function = "normal"; + input-disable; + output-enable; + bias-disable; + power-source = <0>; + qcom,drive-strength = <2>; + }; + }; + + lcd_backlight_ctrl { + lcd_backlight_en_default: lcd_backlight_en_default { + pins = "gpio10"; + function = "normal"; + input-disable; + output-enable; + bias-disable; + power-source = <0>; + qcom,drive-strength = <2>; + }; + }; +}; + +&pm6450_gpios { + lcd_backlight_ctrl { + lcd_backlight_pwm_default: lcd_backlight_pwm_default { + pins = "gpio7"; + function = "func1"; + input-disable; + output-enable; + bias-disable; + power-source = <1>; /* 1.8V */ + qcom,drive-strength = <2>; + }; + }; +}; diff --git a/qcom/parrot-qrd-4gb-overlay.dts b/qcom/parrot-qrd-4gb-overlay.dts new file mode 100644 index 00000000..565ab6b6 --- /dev/null +++ b/qcom/parrot-qrd-4gb-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "parrot-wcn3990.dtsi" +#include "parrot-qrd-4gb.dtsi" +#include "parrot-qrd-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot QRD 4GB DDR"; + compatible = "qcom,parrot-qrd", "qcom,parrot", "qcom,qrd"; + qcom,msm-id = <537 0x10000>; + qcom,board-id = <0x1000B 0x600>; +}; diff --git a/qcom/parrot-qrd-4gb.dts b/qcom/parrot-qrd-4gb.dts new file mode 100644 index 00000000..c11217cc --- /dev/null +++ b/qcom/parrot-qrd-4gb.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrot-4gb.dtsi" +#include "parrot-wcn3990.dtsi" +#include "parrot-qrd-4gb.dtsi" +#include "parrot-qrd-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot QRD 4GB DDR"; + compatible = "qcom,parrot-qrd", "qcom,parrot", "qcom,qrd"; + qcom,board-id = <0x1000B 0x600>; +}; diff --git a/qcom/parrot-qrd-4gb.dtsi b/qcom/parrot-qrd-4gb.dtsi new file mode 100644 index 00000000..690b6ecd --- /dev/null +++ b/qcom/parrot-qrd-4gb.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-qrd.dtsi" diff --git a/qcom/parrot-qrd-nopmi-overlay.dts b/qcom/parrot-qrd-nopmi-overlay.dts new file mode 100644 index 00000000..cb1ab651 --- /dev/null +++ b/qcom/parrot-qrd-nopmi-overlay.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "parrot-wcn3990.dtsi" +#include "parrot-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot QRD"; + compatible = "qcom,parrot-qrd", "qcom,parrot", "qcom,qrd"; + qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>, + <633 0x10000>, <634 0x10000>, <638 0x10000>; + qcom,board-id = <0x1000B 0>; + qcom,pmic-id-size = <9>; + qcom,pmic-id = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; +}; diff --git a/qcom/parrot-qrd-nopmi.dts b/qcom/parrot-qrd-nopmi.dts new file mode 100644 index 00000000..99aa9f64 --- /dev/null +++ b/qcom/parrot-qrd-nopmi.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrot.dtsi" +#include "parrot-wcn3990.dtsi" +#include "parrot-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot QRD"; + compatible = "qcom,parrot-qrd", "qcom,parrot", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; + qcom,pmic-id-size = <9>; + qcom,pmic-id = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; +}; diff --git a/qcom/parrot-qrd-overlay.dts b/qcom/parrot-qrd-overlay.dts new file mode 100644 index 00000000..3c6e28fe --- /dev/null +++ b/qcom/parrot-qrd-overlay.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "parrot-wcn3990.dtsi" +#include "parrot-qrd.dtsi" +#include "parrot-qrd-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot QRD"; + compatible = "qcom,parrot-qrd", "qcom,parrot", "qcom,qrd"; + qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>, + <633 0x10000>, <634 0x10000>, <638 0x10000>; + qcom,board-id = <0x1000B 0>; +}; diff --git a/qcom/parrot-qrd-pm7250b.dtsi b/qcom/parrot-qrd-pm7250b.dtsi new file mode 100644 index 00000000..81bf28ca --- /dev/null +++ b/qcom/parrot-qrd-pm7250b.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-pm7250b.dtsi" + +/ { + qcom,pmic-id-size = <9>; + qcom,pmic-id = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x2E>; +}; + +&battery_charger { + qcom,thermal-mitigation = <11500000 11000000 10500000 10000000 9500000 + 9000000 8500000 8000000 7500000 7000000 6500000 + 6000000 5500000 5000000 4500000 4000000 3500000 + 3000000 2500000 2000000 1500000 1000000 500000>; + qcom,wireless-charging-not-supported; +}; + +&usb0 { + usb-role-switch; + extcon = <&eud>; + + dwc3@a600000 { + usb-role-switch; + dr_mode = "otg"; + }; + + port { + usb_port0: endpoint { + remote-endpoint = <&usb_port0_connector>; + }; + }; +}; + +&ucsi { + connector { + port { + usb_port0_connector: endpoint { + remote-endpoint = <&usb_port0>; + }; + }; + }; +}; diff --git a/qcom/parrot-qrd-pm8350b-overlay.dts b/qcom/parrot-qrd-pm8350b-overlay.dts new file mode 100644 index 00000000..11642be7 --- /dev/null +++ b/qcom/parrot-qrd-pm8350b-overlay.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "parrot-wcn3990.dtsi" +#include "parrot-qrd.dtsi" +#include "parrot-qrd-pm8350b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot QRD"; + compatible = "qcom,parrot-qrd", "qcom,parrot", "qcom,qrd"; + qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>, + <633 0x10000>, <634 0x10000>, <638 0x10000>; + qcom,board-id = <0x1000B 0>; +}; diff --git a/qcom/parrot-qrd-pm8350b.dts b/qcom/parrot-qrd-pm8350b.dts new file mode 100644 index 00000000..a1b853ad --- /dev/null +++ b/qcom/parrot-qrd-pm8350b.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrot.dtsi" +#include "parrot-wcn3990.dtsi" +#include "parrot-qrd.dtsi" +#include "parrot-qrd-pm8350b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot QRD"; + compatible = "qcom,parrot-qrd", "qcom,parrot", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; +}; diff --git a/qcom/parrot-qrd-pm8350b.dtsi b/qcom/parrot-qrd-pm8350b.dtsi new file mode 100644 index 00000000..e565b3d8 --- /dev/null +++ b/qcom/parrot-qrd-pm8350b.dtsi @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-pm8350b.dtsi" + +/ { + qcom,pmic-id-size = <9>; + qcom,pmic-id = <0x0 0x0 0x0 0x32 0x0 0x0 0x0 0x0 0x0>; +}; + +&battery_charger { + qcom,thermal-mitigation-step = <500000>; +}; + +&usb0 { + usb-role-switch; + extcon = <&eud>; + + dwc3@a600000 { + usb-role-switch; + dr_mode = "otg"; + }; + + port { + usb_port0: endpoint { + remote-endpoint = <&usb_port0_connector>; + }; + }; +}; + +&ucsi { + connector { + port { + usb_port0_connector: endpoint { + remote-endpoint = <&usb_port0>; + }; + }; + }; +}; diff --git a/qcom/parrot-qrd-wcn6750-4gb-overlay.dts b/qcom/parrot-qrd-wcn6750-4gb-overlay.dts new file mode 100644 index 00000000..59758199 --- /dev/null +++ b/qcom/parrot-qrd-wcn6750-4gb-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "parrot-wcn6750.dtsi" +#include "parrot-qrd-wcn6750-4gb.dtsi" +#include "parrot-qrd-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot WCN6750 QRD 4GB DDR"; + compatible = "qcom,parrot-qrd", "qcom,parrot", "qcom,qrd"; + qcom,msm-id = <537 0x10000>; + qcom,board-id = <0x1000B 0x601>; +}; diff --git a/qcom/parrot-qrd-wcn6750-4gb.dts b/qcom/parrot-qrd-wcn6750-4gb.dts new file mode 100644 index 00000000..e4e5d9f8 --- /dev/null +++ b/qcom/parrot-qrd-wcn6750-4gb.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrot-4gb.dtsi" +#include "parrot-wcn6750.dtsi" +#include "parrot-qrd-wcn6750-4gb.dtsi" +#include "parrot-qrd-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot WCN6750 QRD 4GB DDR"; + compatible = "qcom,parrot-qrd", "qcom,parrot", "qcom,qrd"; + qcom,board-id = <0x1000B 0x601>; +}; diff --git a/qcom/parrot-qrd-wcn6750-4gb.dtsi b/qcom/parrot-qrd-wcn6750-4gb.dtsi new file mode 100644 index 00000000..257d2c9f --- /dev/null +++ b/qcom/parrot-qrd-wcn6750-4gb.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-qrd-4gb.dtsi" diff --git a/qcom/parrot-qrd-wcn6750-overlay.dts b/qcom/parrot-qrd-wcn6750-overlay.dts new file mode 100644 index 00000000..f2372fe5 --- /dev/null +++ b/qcom/parrot-qrd-wcn6750-overlay.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "parrot-wcn6750.dtsi" +#include "parrot-qrd-wcn6750.dtsi" +#include "parrot-qrd-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot WCN6750 QRD"; + compatible = "qcom,parrot-qrd", "qcom,parrot", "qcom,qrd"; + qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>, + <633 0x10000>, <634 0x10000>, <638 0x10000>; + qcom,board-id = <0x1000B 1>; +}; diff --git a/qcom/parrot-qrd-wcn6750.dts b/qcom/parrot-qrd-wcn6750.dts new file mode 100644 index 00000000..783be33f --- /dev/null +++ b/qcom/parrot-qrd-wcn6750.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrot.dtsi" +#include "parrot-wcn6750.dtsi" +#include "parrot-qrd-wcn6750.dtsi" +#include "parrot-qrd-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot WCN6750 QRD"; + compatible = "qcom,parrot-qrd", "qcom,parrot", "qcom,qrd"; + qcom,board-id = <0x1000B 1>; +}; diff --git a/qcom/parrot-qrd-wcn6750.dtsi b/qcom/parrot-qrd-wcn6750.dtsi new file mode 100644 index 00000000..5152b9a8 --- /dev/null +++ b/qcom/parrot-qrd-wcn6750.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-qrd.dtsi" + +&soc { +}; diff --git a/qcom/parrot-qrd.dts b/qcom/parrot-qrd.dts new file mode 100644 index 00000000..4ffcec24 --- /dev/null +++ b/qcom/parrot-qrd.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrot.dtsi" +#include "parrot-wcn3990.dtsi" +#include "parrot-qrd.dtsi" +#include "parrot-qrd-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot QRD"; + compatible = "qcom,parrot-qrd", "qcom,parrot", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; +}; diff --git a/qcom/parrot-qrd.dtsi b/qcom/parrot-qrd.dtsi new file mode 100644 index 00000000..73866070 --- /dev/null +++ b/qcom/parrot-qrd.dtsi @@ -0,0 +1,155 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +#include "parrot-pmic-overlay.dtsi" +#include "parrot-thermal-overlay.dtsi" + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pm6450_gpios 1 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + }; +}; + +&usb2_phy0 { + qcom,param-override-seq = < + 0x83 0x6c + 0xcb 0x70 + 0x1e 0x74 + 0x03 0x78>; +}; + +&sdhc_1 { + status = "ok"; + + vdd-supply = <&L24B>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L19B>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-current-level = <0 325000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; +}; + +&sdhc_2 { + status = "ok"; + + vdd-supply = <&L9E>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&L6E>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 22000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + cd-gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4-waipio"; + + vdda-phy-supply = <&L5B>; + vdda-pll-supply = <&L16B>; + vdda-phy-max-microamp = <140000>; + vdda-pll-max-microamp = <18300>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + + vcc-supply = <&L24B>; + vcc-max-microamp = <1200000>; + + vccq-supply = <&L13B>; + vccq-max-microamp = <1200000>; + + vccq2-supply = <&L19B>; + vccq2-max-microamp = <750000>; + + qcom,vddp-ref-clk-supply = <&L13B>; + qcom,vddp-ref-clk-max-microamp = <100>; + + /* + * ufs-dev-types and nvmem entries are for ufs device + * identification using nvmem interface. Use number of + * ufs devices supported for ufs-dev-types, and nvmem handle + * added by pmic for sdam register. + * + * Default value taken by driver is bit[0] = 0 for 3.x and + * bit[0] = 1 for 2.x driver code takes this as default case. + * + * But Bit value to identify ufs device is not consistent + * across the targets it could be bit[0] = 0/1 for UFS2.x/3x + * and vice versa. If the bit[0] value is not same as default + * value used in driver and if its reverted then use flag + * qcom,ufs-dev-revert to identify ufs device. + */ + ufs-dev-types = <2>; + qcom,ufs-dev-revert; + nvmem-cells = <&ufs_dev>, <&boot_config>; + nvmem-cell-names = "ufs_dev", "boot_conf"; + + status = "ok"; +}; + +&qupv3_se9_spi { + #address-cells = <1>; + #size-cells = <0>; + status = "ok"; + qcom,touch-active = "goodix,gt9916S"; + + goodix-berlin@0 { + reg = <0>; + spi-max-frequency = <1000000>; + + goodix,avdd-name = "avdd"; + avdd-supply = <&L28B>; + + interrupt-parent = <&tlmm>; + interrupts = <65 0x2008>; + goodix,reset-gpio = <&tlmm 64 0x00>; + goodix,irq-gpio = <&tlmm 65 0x2008>; + goodix,irq-flags = <2>; + goodix,panel-max-x = <1080>; + goodix,panel-max-y = <2400>; + goodix,panel-max-w = <255>; + goodix,panel-max-p = <4096>; + goodix,firmware-name = "goodix_firmware_spi.bin"; + goodix,config-name = "goodix_cfg_group_spi.bin"; + + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", "pmx_ts_release"; + pinctrl-0 = <&ts_spi_active>; + pinctrl-1 = <&ts_spi_int_suspend &ts_spi_reset_suspend>; + pinctrl-2 = <&ts_spi_release>; + + qcom,touch-environment = "pvm"; + }; +}; diff --git a/qcom/parrot-qupv3.dtsi b/qcom/parrot-qupv3.dtsi new file mode 100644 index 00000000..d4d60775 --- /dev/null +++ b/qcom/parrot-qupv3.dtsi @@ -0,0 +1,583 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + /* QUPv3 SE Instances + * Qup0 0: SE 0 + * Qup0 1: SE 1 + * Qup0 2: SE 2 + * Qup0 3: SE 3 + * Qup0 4: SE 4 + * Qup0 5: SE 5 + * Qup1 0: SE 6 + * Qup1 1: SE 7 + * Qup1 2: SE 8 + * Qup1 3: SE 9 + * Qup1 4: SE 10 + * Qup1 5: SE 11 + */ + + /* GPI Instance */ + gpi_dma0: qcom,gpi-dma@900000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0x900000 0x60000>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0x176 0x0>; + qcom,max-num-gpii = <12>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,gpii-mask = <0x3f>; + qcom,ev-factor = <2>; + qcom,iommu-dma-addr-pool = <0x100000 0x100000>; + dma-coherent; + qcom,gpi-ee-offset = <0x10000>; + status = "ok"; + }; + + /* QUPv3_0 wrapper instance */ + qupv3_0: qcom,qupv3_0_geni_se@9C0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x9C0000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + iommus = <&apps_smmu 0x163 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + dma-coherent; + ranges; + status = "ok"; + + /* Debug UART Instance */ + qupv3_se3_2uart: qcom,qup_uart@98c000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x98c000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&system_noc MASTER_A1NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_2uart_tx_active>, <&qupv3_se3_2uart_rx_active>; + pinctrl-1 = <&qupv3_se3_2uart_sleep>; + status = "disabled"; + }; + + qupv3_se0_i2c: i2c@980000 { + compatible = "qcom,i2c-geni"; + reg = <0x980000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&system_noc MASTER_A1NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_i2c_sda_active>, <&qupv3_se0_i2c_scl_active>; + pinctrl-1 = <&qupv3_se0_i2c_sleep>; + dmas = <&gpi_dma0 0 0 3 64 0>, + <&gpi_dma0 1 0 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se0_spi: spi@980000 { + compatible = "qcom,spi-geni"; + reg = <0x980000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&system_noc MASTER_A1NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_spi_mosi_active>, <&qupv3_se0_spi_miso_active>, + <&qupv3_se0_spi_clk_active>, <&qupv3_se0_spi_cs_active>; + pinctrl-1 = <&qupv3_se0_spi_sleep>; + dmas = <&gpi_dma0 0 0 1 64 0>, + <&gpi_dma0 1 0 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se1_i2c: i2c@984000 { + compatible = "qcom,i2c-geni"; + reg = <0x984000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&system_noc MASTER_A1NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_i2c_sda_active>, <&qupv3_se1_i2c_scl_active>; + pinctrl-1 = <&qupv3_se1_i2c_sleep>; + dmas = <&gpi_dma0 0 1 3 64 0>, + <&gpi_dma0 1 1 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se1_spi: spi@984000 { + compatible = "qcom,spi-geni"; + reg = <0x984000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&system_noc MASTER_A1NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_spi_mosi_active>, <&qupv3_se1_spi_miso_active>, + <&qupv3_se1_spi_clk_active>, <&qupv3_se1_spi_cs_active>; + pinctrl-1 = <&qupv3_se1_spi_sleep>; + dmas = <&gpi_dma0 0 1 1 64 0>, + <&gpi_dma0 1 1 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se2_i2c: i2c@988000 { + compatible = "qcom,i2c-geni"; + reg = <0x988000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&system_noc MASTER_A1NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_i2c_sda_active>, <&qupv3_se2_i2c_scl_active>; + pinctrl-1 = <&qupv3_se2_i2c_sleep>; + dmas = <&gpi_dma0 0 2 3 64 0>, + <&gpi_dma0 1 2 3 64 0>; + dma-names = "tx", "rx"; + qcom,shared; + status = "disabled"; + }; + + qupv3_se2_spi: spi@988000 { + compatible = "qcom,spi-geni"; + reg = <0x988000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&system_noc MASTER_A1NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_spi_mosi_active>, <&qupv3_se2_spi_miso_active>, + <&qupv3_se2_spi_clk_active>, <&qupv3_se2_spi_cs_active>; + pinctrl-1 = <&qupv3_se2_spi_sleep>; + dmas = <&gpi_dma0 0 2 1 64 0>, + <&gpi_dma0 1 2 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se4_i2c: i2c@990000 { + compatible = "qcom,i2c-geni"; + reg = <0x990000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&system_noc MASTER_A1NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_i2c_sda_active>, <&qupv3_se4_i2c_scl_active>; + pinctrl-1 = <&qupv3_se4_i2c_sleep>; + dmas = <&gpi_dma0 0 4 3 64 0>, + <&gpi_dma0 1 4 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se4_spi: spi@990000 { + compatible = "qcom,spi-geni"; + reg = <0x990000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&system_noc MASTER_A1NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_spi_mosi_active>, <&qupv3_se4_spi_miso_active>, + <&qupv3_se4_spi_clk_active>, <&qupv3_se4_spi_cs_active>; + pinctrl-1 = <&qupv3_se4_spi_sleep>; + dmas = <&gpi_dma0 0 4 1 64 0>, + <&gpi_dma0 1 4 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se5_i2c: i2c@994000 { + compatible = "qcom,i2c-geni"; + reg = <0x994000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&system_noc MASTER_A1NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_i2c_sda_active>, <&qupv3_se5_i2c_scl_active>; + pinctrl-1 = <&qupv3_se5_i2c_sleep>; + dmas = <&gpi_dma0 0 5 3 64 0>, + <&gpi_dma0 1 5 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se5_spi: spi@994000 { + compatible = "qcom,spi-geni"; + reg = <0x994000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&system_noc MASTER_A1NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_spi_mosi_active>, <&qupv3_se5_spi_miso_active>, + <&qupv3_se5_spi_clk_active>, <&qupv3_se5_spi_cs_active>; + pinctrl-1 = <&qupv3_se5_spi_sleep>; + dmas = <&gpi_dma0 0 5 1 64 0>, + <&gpi_dma0 1 5 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + }; + + /* GPI Instance */ + gpi_dma1: qcom,gpi-dma@a00000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0xa00000 0x60000>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0x416 0x0>; + qcom,max-num-gpii = <12>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,static-gpii-mask = <0x1>; + qcom,gpii-mask = <0x3e>; + qcom,ev-factor = <2>; + qcom,iommu-dma-addr-pool = <0x100000 0x100000>; + dma-coherent; + qcom,gpi-ee-offset = <0x10000>; + status = "ok"; + }; + + /* QUPv3_1 wrapper instance */ + qupv3_1: qcom,qupv3_1_geni_se@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0xac0000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus = <&apps_smmu 0x403 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + dma-coherent; + ranges; + status = "ok"; + + qupv3_se6_i2c: i2c@a80000 { + compatible = "qcom,i2c-geni"; + reg = <0xa80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_i2c_sda_active>, <&qupv3_se6_i2c_scl_active>; + pinctrl-1 = <&qupv3_se6_i2c_sleep>; + dmas = <&gpi_dma1 0 0 3 64 0>, + <&gpi_dma1 1 0 3 64 0>; + dma-names = "tx", "rx"; + }; + + qupv3_se6_spi: spi@a80000 { + compatible = "qcom,spi-geni"; + reg = <0xa80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_spi_mosi_active>, <&qupv3_se6_spi_miso_active>, + <&qupv3_se6_spi_clk_active>, <&qupv3_se6_spi_cs_active>; + pinctrl-1 = <&qupv3_se6_spi_sleep>; + dmas = <&gpi_dma1 0 0 1 64 0>, + <&gpi_dma1 1 0 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se7_i2c: i2c@a84000 { + compatible = "qcom,i2c-geni"; + reg = <0xa84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_i2c_sda_active>, <&qupv3_se7_i2c_scl_active>; + pinctrl-1 = <&qupv3_se7_i2c_sleep>; + dmas = <&gpi_dma1 0 1 3 64 0>, + <&gpi_dma1 1 1 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se7_spi: spi@a84000 { + compatible = "qcom,spi-geni"; + reg = <0xa84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_spi_mosi_active>, <&qupv3_se7_spi_miso_active>, + <&qupv3_se7_spi_clk_active>, <&qupv3_se7_spi_cs_active>; + pinctrl-1 = <&qupv3_se7_spi_sleep>; + dmas = <&gpi_dma1 0 1 1 64 0>, + <&gpi_dma1 1 1 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se8_i2c: i2c@a88000 { + compatible = "qcom,i2c-geni"; + reg = <0xa88000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_i2c_sda_active>, <&qupv3_se8_i2c_scl_active>; + pinctrl-1 = <&qupv3_se8_i2c_sleep>; + dmas = <&gpi_dma1 0 2 3 64 0>, + <&gpi_dma1 1 2 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se8_spi: spi@a88000 { + compatible = "qcom,spi-geni"; + reg = <0xa88000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_spi_mosi_active>, <&qupv3_se8_spi_miso_active>, + <&qupv3_se8_spi_clk_active>, <&qupv3_se8_spi_cs_active>; + pinctrl-1 = <&qupv3_se8_spi_sleep>; + dmas = <&gpi_dma1 0 2 1 64 0>, + <&gpi_dma1 1 2 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se9_i2c: i2c@a8c000 { + compatible = "qcom,i2c-geni"; + reg = <0xa8c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_i2c_sda_active>, <&qupv3_se9_i2c_scl_active>; + pinctrl-1 = <&qupv3_se9_i2c_sleep>; + dmas = <&gpi_dma1 0 3 3 64 2>, + <&gpi_dma1 1 3 3 64 2>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se9_spi: spi@a8c000 { + compatible = "qcom,spi-geni"; + reg = <0xa8c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_spi_mosi_active>, <&qupv3_se9_spi_miso_active>, + <&qupv3_se9_spi_clk_active>, <&qupv3_se9_spi_cs_active>; + pinctrl-1 = <&qupv3_se9_spi_sleep>; + dmas = <&gpi_dma1 0 3 1 64 2>, + <&gpi_dma1 1 3 1 64 2>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + /* HS UART Instance */ + qupv3_se11_4uart: qcom,qup_uart@a94000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0xa94000 0x4000>; + reg-names = "se_phys"; + interrupts-extended = <&intc GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 17 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "active", "sleep"; + pinctrl-0 = <&qupv3_se11_default_cts>, <&qupv3_se11_default_rts>, + <&qupv3_se11_default_tx>, <&qupv3_se11_default_rx>; + pinctrl-1 = <&qupv3_se11_cts>, <&qupv3_se11_rts>, + <&qupv3_se11_tx>, <&qupv3_se11_rx>; + pinctrl-2 = <&qupv3_se11_cts>, <&qupv3_se11_rts>, + <&qupv3_se11_tx>, <&qupv3_se11_default_rx>; + pinctrl-3 = <&qupv3_se11_default_cts>, <&qupv3_se11_default_rts>, + <&qupv3_se11_default_tx>, <&qupv3_se11_default_rx>; + qcom,wakeup-byte = <0xFD>; + status = "disabled"; + }; + }; +}; diff --git a/qcom/parrot-regulators.dtsi b/qcom/parrot-regulators.dtsi new file mode 100644 index 00000000..6772774d --- /dev/null +++ b/qcom/parrot-regulators.dtsi @@ -0,0 +1,992 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&apps_rsc_drv2 { + rpmh-regulator-cxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "cx.lvl"; + proxy-supply = <&VDD_CX_LEVEL>; + VDD_CX_LEVEL: + S1B_LEVEL: + pm6450_s1_level: regulator-pm6450-s1-level { + regulator-name = "pm6450_s1_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + qcom,init-voltage-level = + ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-voltage = + ; + }; + + VDD_CX_LEVEL_AO: + S1B_LEVEL_AO: + pm6450_s1_level_ao: regulator-pm6450-s1-level-ao { + regulator-name = "pm6450_s1_level_ao"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-gfxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "gfx.lvl"; + VDD_GFX_LEVEL: S3B_LEVEL: + pm6450_s3_level: regulator-pm6450-s3-level { + regulator-name = "pm6450_s3_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-ebilvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "ebi.lvl"; + VDD_EBI_LEVEL: + S5B_LEVEL: + pm6450_s5_level: regulator-pm6450-s5-level { + regulator-name = "pm6450_s5_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-smpb6 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpb6"; + S6B: + pm6450_s6: regulator-pm6450-s6 { + regulator-name = "pm6450_s6"; + qcom,set = ; + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1170000>; + qcom,init-voltage = <1052000>; + }; + }; + + rpmh-regulator-smpb7 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpb7"; + S7B: + pm6450_s7: regulator-pm6450-s7 { + regulator-name = "pm6450_s7"; + qcom,set = ; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <1174000>; + qcom,init-voltage = <972000>; + }; + }; + + rpmh-regulator-smpb8 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpb8"; + S8B: + pm6450_s8: regulator-pm6450-s8 { + regulator-name = "pm6450_s8"; + qcom,set = ; + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1654000>; + qcom,init-voltage = <1272000>; + }; + }; + + rpmh-regulator-smpb9 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpb9"; + S9B: + pm6450_s9: regulator-pm6450-s9 { + regulator-name = "pm6450_s9"; + qcom,set = ; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <2208000>; + qcom,init-voltage = <2208000>; + }; + }; + + rpmh-regulator-ldob1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob1"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L1B: + pm6450_l1: regulator-pm6450-l1 { + regulator-name = "pm6450_l1"; + qcom,set = ; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <650000>; + qcom,init-voltage = <504000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-lcxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "lcx.lvl"; + VDD_LPI_CX_LEVEL: + L2B_LEVEL: + pm6450_l2_level: regulator-pm6450-l2-level { + regulator-name = "pm6450_l2_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-ldob3 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob3"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L3B: + pm6450_l3: regulator-pm6450-l3 { + regulator-name = "pm6450_l3"; + qcom,set = ; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + qcom,init-voltage = <904000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob4 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob4"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L4B: + pm6450_l4: regulator-pm6450-l4 { + regulator-name = "pm6450_l4"; + qcom,set = ; + regulator-min-microvolt = <530000>; + regulator-max-microvolt = <864000>; + qcom,init-voltage = <530000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob5 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob5"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L5B: + pm6450_l5: regulator-pm6450-l5 { + regulator-name = "pm6450_l5"; + qcom,set = ; + regulator-min-microvolt = <830000>; + regulator-max-microvolt = <920000>; + qcom,init-voltage = <880000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob6 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob6"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L6B: + pm6450_l6: regulator-pm6450-l6 { + regulator-name = "pm6450_l6"; + qcom,set = ; + regulator-min-microvolt = <751000>; + regulator-max-microvolt = <824000>; + qcom,init-voltage = <751000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob7 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob7"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L7B: + pm6450_l7: regulator-pm6450-l7 { + regulator-name = "pm6450_l7"; + qcom,set = ; + regulator-min-microvolt = <830000>; + regulator-max-microvolt = <920000>; + qcom,init-voltage = <912000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob8 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob8"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L8B: + pm6450_l8: regulator-pm6450-l8 { + regulator-name = "pm6450_l8"; + qcom,set = ; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + qcom,init-voltage = <870000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-lmxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "lmx.lvl"; + VDD_LPI_MX_LEVEL: + L9B_LEVEL: + pm6450_l9_level: regulator-pm6450-l9-level { + regulator-name = "pm6450_l9_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-ldob10 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob10"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L10B: + pm6450_l10: regulator-pm6450-l10 { + regulator-name = "pm6450_l10"; + qcom,set = ; + regulator-min-microvolt = <824000>; + regulator-max-microvolt = <950000>; + qcom,init-voltage = <824000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob11 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob11"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L11B: + pm6450_l11: regulator-pm6450-l11 { + regulator-name = "pm6450_l11"; + qcom,set = ; + regulator-min-microvolt = <348000>; + regulator-max-microvolt = <888000>; + qcom,init-voltage = <348000>; + }; + }; + + rpmh-regulator-ldob12 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob12"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L12B: + pm6450_l12: regulator-pm6450-l12 { + regulator-name = "pm6450_l12"; + qcom,set = ; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1240000>; + qcom,init-voltage = <1080000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob13 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob13"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L13B: + pm6450_l13: regulator-pm6450-l13 { + regulator-name = "pm6450_l13"; + qcom,set = ; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1304000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob14 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob14"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L14B: + pm6450_l14: regulator-pm6450-l14 { + regulator-name = "pm6450_l14"; + qcom,set = ; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1304000>; + qcom,init-voltage = <1150000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob16 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob16"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L16B: + pm6450_l16: regulator-pm6450-l16 { + regulator-name = "pm6450_l16"; + qcom,set = ; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob17 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob17"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L17B: + pm6450_l17: regulator-pm6450-l17 { + regulator-name = "pm6450_l17"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob18 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob18"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L18B: + pm6450_l18: regulator-pm6450-l18 { + regulator-name = "pm6450_l18"; + qcom,set = ; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + qcom,init-voltage = <1504000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob19 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob19"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L19B: + pm6450_l19: regulator-pm6450-l19 { + regulator-name = "pm6450_l19"; + qcom,set = ; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob20 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob20"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L20B: + pm6450_l20: regulator-pm6450-l20 { + regulator-name = "pm6450_l20"; + qcom,set = ; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + qcom,init-voltage = <1700000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob21 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob21"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L21B: + pm6450_l21: regulator-pm6450-l21 { + regulator-name = "pm6450_l21"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1950000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob22 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob22"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L22B: + pm6450_l22: regulator-pm6450-l22 { + regulator-name = "pm6450_l22"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob23 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob23"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L23B: + pm6450_l23: regulator-pm6450-l23 { + regulator-name = "pm6450_l23"; + qcom,set = ; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob24 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob24"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L24B: + pm6450_l24: regulator-pm6450-l24 { + regulator-name = "pm6450_l24"; + qcom,set = ; + qcom,init-mode = ; + /* + * Remove min/max voltages for this regulator as initial + * voltage of L24B is set to be 2.4v/2.96v during PON + * depending upon the UFS mode. UFS is the only client + * on this and this regulator will only be voted + * for enabling/disabling conditions. + */ + }; + }; + + rpmh-regulator-ldob25 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob25"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L25B: + pm6450_l25: regulator-pm6450-l25 { + regulator-name = "pm6450_l25"; + qcom,set = ; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + qcom,init-voltage = <3072000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob26 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob26"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L26B: + pm6450_l26: regulator-pm6450-l26 { + regulator-name = "pm6450_l26"; + qcom,set = ; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <1620000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob27 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob27"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L27B: + pm6450_l27: regulator-pm6450-l27 { + regulator-name = "pm6450_l27"; + qcom,set = ; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <1620000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob28 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob28"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L28B: + pm6450_l28: regulator-pm6450-l28 { + regulator-name = "pm6450_l28"; + qcom,set = ; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + qcom,init-voltage = <2700000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-msslvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "mss.lvl"; + VDD_MODEM_LEVEL: + S1E_LEVEL: + pm6150l_s1_level: regulator-pm6150l-s1-level { + regulator-name = "pm6150l_s1_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-mxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "mx.lvl"; + proxy-supply = <&VDD_MXA_LEVEL>; + + VDD_MXA_LEVEL: + S3E_LEVEL: + pm6150l_s3_level: regulator-pm6150l-s3-level { + regulator-name = "pm6150l_s3_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + qcom,init-voltage-level = + ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-voltage = + ; + }; + + VDD_MXA_LEVEL_AO: S10C_LEVEL_AO: + pm6150l_s3_level_ao: regulator-pm6150l-s3-level-ao { + regulator-name = "pm6150l_s3_level_ao"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-smpe8 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpe8"; + S8E: + pm6150l_s8: regulator-pm6150l-s8 { + regulator-name = "pm6150l_s8"; + qcom,set = ; + regulator-min-microvolt = <1816000>; + regulator-max-microvolt = <2040000>; + qcom,init-voltage = <1872000>; + }; + }; + + rpmh-regulator-ldoe1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe1"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L1E: + pm6150l_l1: regulator-pm6150l-l1 { + regulator-name = "pm6150l_l1"; + qcom,set = ; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + qcom,init-voltage = <1620000>; + }; + }; + + rpmh-regulator-ldoe4 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe4"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L4E: + pm6150l_l4: regulator-pm6150l-l4 { + regulator-name = "pm6150l_l4"; + qcom,set = ; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <2700000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe5 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe5"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L5E: + pm6150l_l5: regulator-pm6150l-l5 { + regulator-name = "pm6150l_l5"; + qcom,set = ; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <3544000>; + qcom,init-voltage = <1504000>; + }; + }; + + rpmh-regulator-ldoe6 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe6"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L6E: + pm6150l_l6: regulator-pm6150l-l6 { + regulator-name = "pm6150l_l6"; + qcom,set = ; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <1650000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe7 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe7"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L7E: + pm6150l_l7: regulator-pm6150l-l7 { + regulator-name = "pm6150l_l7"; + qcom,set = ; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3544000>; + qcom,init-voltage = <3000000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe8 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe8"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L8E: + pm6150l_l8: regulator-pm6150l-l8 { + regulator-name = "pm6150l_l8"; + qcom,set = ; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + qcom,init-voltage = <1620000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe9 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe9"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L9E: + pm6150l_l9: regulator-pm6150l-l9 { + regulator-name = "pm6150l_l9"; + qcom,set = ; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + qcom,init-voltage = <2700000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe10 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe10"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L10E: + pm6150l_l10: regulator-pm6150l-l10 { + regulator-name = "pm6150l_l10"; + qcom,set = ; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; + qcom,init-voltage = <3000000>; + /* + * Removed init-mode as it needs to be + * set from client votes alone. + */ + }; + }; + + rpmh-regulator-ldoe11 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe11"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L11E: + pm6150l_l11: regulator-pm6150l-l11 { + regulator-name = "pm6150l_l11"; + qcom,set = ; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; + qcom,init-voltage = <3000000>; + }; + }; + + rpmh-regulator-ldog2 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldog2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L2G: + pmr735a_l2: regulator-pmr735a-l2 { + regulator-name = "pmr735a_l2"; + qcom,set = ; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1236000>; + qcom,init-voltage = <1140000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldog3 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldog3"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L3G: + pmr735a_l3: regulator-pmr735a-l3 { + regulator-name = "pmr735a_l3"; + qcom,set = ; + regulator-min-microvolt = <866000>; + regulator-max-microvolt = <939000>; + qcom,init-voltage = <866000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldog4 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldog4"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L4G: + pmr735a_l4: regulator-pmr735a-l4 { + regulator-name = "pmr735a_l4"; + qcom,set = ; + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1854000>; + qcom,init-voltage = <1710000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldog5 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldog5"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L5G: + pmr735a_l5: regulator-pmr735a-l5 { + regulator-name = "pmr735a_l5"; + qcom,set = ; + regulator-min-microvolt = <760000>; + regulator-max-microvolt = <824000>; + qcom,init-voltage = <760000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldog6 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldog6"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L6G: + pmr735a_l6: regulator-pmr735a-l6 { + regulator-name = "pmr735a_l6"; + qcom,set = ; + regulator-min-microvolt = <588000>; + regulator-max-microvolt = <800000>; + qcom,init-voltage = <588000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-bobe1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "bobe1"; + qcom,regulator-type = "pmic5-bob"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1000000>; + qcom,send-defaults; + + BOB: pm6150l_bob: regulator-pm6150l-bob { + regulator-name = "pm6150l_bob"; + qcom,set = ; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + qcom,init-voltage = <3296000>; + qcom,init-mode = ; + }; + + BOB_AO: pm6150l_bob_ao: regulator-pm6150l-bob-ao { + regulator-name = "pm6150l_bob_ao"; + qcom,set = ; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + qcom,init-voltage = <3296000>; + qcom,init-mode = ; + }; + }; +}; diff --git a/qcom/parrot-reserved-memory.dtsi b/qcom/parrot-reserved-memory.dtsi new file mode 100644 index 00000000..d4ab5c93 --- /dev/null +++ b/qcom/parrot-reserved-memory.dtsi @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: hyp_region@80000000 { + no-map; + reg = <0x0 0x80000000 0x0 0x600000>; + }; + + xbl_dtlog_mem: xbl_dtlog_region@80600000 { + no-map; + reg = <0x0 0x80600000 0x0 0x40000>; + }; + + xbl_ramdump_mem: xbl_ramdump_region@80640000 { + no-map; + reg = <0x0 0x80640000 0x0 0x1c0000>; + }; + + aop_image_mem: aop_image_region@80800000 { + no-map; + reg = <0x0 0x80800000 0x0 0x60000>; + }; + + aop_cmd_db_mem: aop_cmd_db_region@80860000 { + compatible = "qcom,cmd-db"; + no-map; + reg = <0x0 0x80860000 0x0 0x20000>; + }; + + aop_config_mem: aop_config_region@80880000 { + no-map; + reg = <0x0 0x80880000 0x0 0x20000>; + }; + + tme_crash_dump_mem: tme_crash_dump_region@808a0000 { + no-map; + reg = <0x0 0x808a0000 0x0 0x40000>; + }; + + tme_log_mem: tme_log_region@808e0000 { + no-map; + reg = <0x0 0x808e0000 0x0 0x4000>; + }; + + uefi_log_mem: uefi_log_region@808e4000 { + no-map; + reg = <0x0 0x808e4000 0x0 0x10000>; + }; + + smem_mem: smem_region@80900000 { + no-map; + reg = <0x0 0x80900000 0x0 0x200000>; + }; + + cpucp_fw_mem: cpucp_fw_region@80b00000 { + no-map; + reg = <0x0 0x80b00000 0x0 0x100000>; + }; + + chipinfo_mem: chipinfo_region@80c00000 { + no-map; + reg = <0x0 0x80c00000 0x0 0x1000>; + }; + + wlan_fw_mem: wlan_fw_region@82a00000 { + no-map; + reg = <0x0 0x82a00000 0x0 0xc00000>; + }; + + camera_mem: camera_region@84b00000 { + no-map; + reg = <0x0 0x84b00000 0x0 0x800000>; + }; + + wpss_mem: wpss_region@85300000 { + no-map; + reg = <0x0 0x85300000 0x0 0x1900000>; + }; + + video_mem: video_region@86c00000 { + no-map; + reg = <0x0 0x86c00000 0x0 0x700000>; + }; + + adsp_mem: adsp_region@87300000 { + no-map; + reg = <0x0 0x87300000 0x0 0x2100000>; + }; + + cdsp_mem: cdsp_region@89400000 { + no-map; + reg = <0x0 0x89400000 0x0 0xa00000>; + }; + + ipa_fw_mem: ipa_fw_region@89e00000 { + no-map; + reg = <0x0 0x89e00000 0x0 0x10000>; + }; + + ipa_gsi_mem: ipa_gsi_region@89e10000 { + no-map; + reg = <0x0 0x89e10000 0x0 0xa000>; + }; + + gpu_microcode_mem: gpu_microcode_region@89e1a000 { + no-map; + reg = <0x0 0x89e1a000 0x0 0x2000>; + }; + + mpss_mem: mpss_region@8bc00000 { + no-map; + reg = <0x0 0x8bc00000 0x0 0xe600000>; + }; + + xbl_sc_mem: xbl_sc_region@a6e00000 { + no-map; + reg = <0x0 0xa6e00000 0x0 0x40000>; + }; + + global_sync_mem: global_sync_region@a6f00000 { + no-map; + reg = <0x0 0xa6f00000 0x0 0x100000>; + }; + + cpusys_vm_mem: cpusys_vm_region@e0600000 { + no-map; + reg = <0x0 0xe0600000 0x0 0x400000>; + }; + + trust_ui_vm_mem: trust_ui_vm_region@e0b00000 { + no-map; + reg = <0x0 0xe0b00000 0x0 0x4af3000>; + }; + + trust_ui_vm_qrtr: trust_ui_vm_qrtr@e55f3000 { + no-map; + reg = <0x0 0xe55f3000 0x0 0x9000>; + }; + + trust_ui_vm_vblk0_ring: trust_ui_vm_vblk0_ring@e55fc000 { + no-map; + reg = <0x0 0xe55fc000 0x0 0x4000>; + gunyah-label = <0x11>; + }; + + trust_ui_vm_swiotlb: trust_ui_vm_swiotlb@e5600000 { + no-map; + reg = <0x0 0xe5600000 0x0 0x100000>; + gunyah-label = <0x12>; + }; + + tz_stat_mem: tz_stat_region@e8800000 { + no-map; + reg = <0x0 0xe8800000 0x0 0x100000>; + }; + + tags_mem: tags_region@e8900000 { + no-map; + reg = <0x0 0xe8900000 0x0 0x680000>; + }; + + qtee_mem: qtee_region@e8f80000 { + no-map; + reg = <0x0 0xe8f80000 0x0 0x500000>; + }; + + trusted_apps_mem: trusted_apps_region@e9480000 { + no-map; + reg = <0x0 0xe9480000 0x0 0x1200000>; + }; +}; diff --git a/qcom/parrot-rumi-overlay.dts b/qcom/parrot-rumi-overlay.dts new file mode 100644 index 00000000..a8bc104e --- /dev/null +++ b/qcom/parrot-rumi-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "parrot-wcn3990.dtsi" +#include "parrot-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot RUMI"; + compatible = "qcom,parrot-rumi", "qcom,parrot", "qcom,rumi"; + qcom,msm-id = <537 0x10000>; + qcom,board-id = <0x1000F 0>; +}; diff --git a/qcom/parrot-rumi.dts b/qcom/parrot-rumi.dts new file mode 100644 index 00000000..5f2078a2 --- /dev/null +++ b/qcom/parrot-rumi.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/memreserve/ 0x90000000 0x00010000; + +#include "parrot.dtsi" +#include "parrot-wcn3990.dtsi" +#include "parrot-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot RUMI"; + compatible = "qcom,parrot-rumi", "qcom,parrot", "qcom,rumi"; + qcom,board-id = <0x1000F 0>; +}; diff --git a/qcom/parrot-rumi.dtsi b/qcom/parrot-rumi.dtsi new file mode 100644 index 00000000..6e6034ad --- /dev/null +++ b/qcom/parrot-rumi.dtsi @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&soc { + timer { + clock-frequency = <500000>; + }; + + timer@17420000 { + clock-frequency = <500000>; + }; + + qcom,wdt@17410000 { + status = "disabled"; + }; + + usb_emuphy: phy@a784000 { + compatible = "qcom,usb-emu-phy"; + reg = <0x0a784000 0x9500>; + + qcom,emu-init-seq = <0xfffff 0x4 + 0xffff0 0x4 + 0x100000 0x20 + 0x0 0x20 + 0x000001A0 0x20 + 0x00100000 0x3c + 0x0 0x3c + 0x0 0x4>; + }; +}; + +&usb0 { + dwc3@a600000 { + usb-phy = <&usb_emuphy>, <&usb_nop_phy>; + dr_mode = "peripheral"; + maximum-speed = "high-speed"; + }; +}; + +&sdhc_1 { + status = "disabled"; + + vdd-supply = <&L24B>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L19B>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; + + /delete-property/ mmc-ddr-1_8v; + /delete-property/ mmc-hs200-1_8v; + /delete-property/ mmc-hs400-1_8v; + /delete-property/ mmc-hs400-enhanced-strobe; + max-frequency = <100000000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; +}; + +&sdhc_2 { + status = "ok"; + vdd-supply = <&L9E>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&L6E>; + qcom,vdd-io-voltage-level = <2960000 2960000>; + qcom,vdd-io-current-level = <0 22000>; + + is_rumi; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + cd-gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qrbtc-sdm845"; + + vdda-phy-supply = <&L5B>; + vdda-pll-supply = <&L17B>; + vdda-phy-max-microamp = <85800>; + vdda-pll-max-microamp = <18300>; + + status = "ok"; +}; + +&ufshc_mem { + limit-tx-hs-gear = <1>; + limit-rx-hs-gear = <1>; + limit-rate = <2>; /* HS Rate-B */ + + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + + vcc-supply = <&L24B>; + vcc-max-microamp = <1200000>; + + vccq-supply = <&L13B>; + vccq-max-microamp = <1200000>; + + vccq2-supply = <&L19B>; + vccq2-max-microamp = <750000>; + + qcom,vddp-ref-clk-supply = <&L13B>; + qcom,vddp-ref-clk-max-microamp = <100>; + + qcom,disable-lpm; + rpm-level = <0>; + spm-level = <0>; + + status = "ok"; +}; + +&qupv3_se3_2uart { + qcom,rumi_platform; +}; + +&tsens0 { + status = "disabled"; +}; diff --git a/qcom/parrot-sg-atp.dts b/qcom/parrot-sg-atp.dts new file mode 100644 index 00000000..ae94c111 --- /dev/null +++ b/qcom/parrot-sg-atp.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrot-sg.dtsi" +#include "parrot-wcn3990.dtsi" +#include "parrot-sg-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot SG ATP"; + compatible = "qcom,parrot-atp", "qcom,parrot", "qcom,atp"; + qcom,board-id = <33 0>; +}; diff --git a/qcom/parrot-sg-atp.dtsi b/qcom/parrot-sg-atp.dtsi new file mode 100644 index 00000000..bc0e5053 --- /dev/null +++ b/qcom/parrot-sg-atp.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-atp.dtsi" diff --git a/qcom/parrot-sg-idp-nopmi.dts b/qcom/parrot-sg-idp-nopmi.dts new file mode 100644 index 00000000..1a0a95f7 --- /dev/null +++ b/qcom/parrot-sg-idp-nopmi.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrot-sg.dtsi" +#include "parrot-wcn6750.dtsi" +#include "parrot-sg-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot SG IDP"; + compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp"; + qcom,board-id = <34 0>; + qcom,pmic-id-size = <9>; + qcom,pmic-id = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; +}; diff --git a/qcom/parrot-sg-idp-pm8350b.dts b/qcom/parrot-sg-idp-pm8350b.dts new file mode 100644 index 00000000..df963274 --- /dev/null +++ b/qcom/parrot-sg-idp-pm8350b.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrot-sg.dtsi" +#include "parrot-wcn6750.dtsi" +#include "parrot-sg-idp.dtsi" +#include "parrot-idp-pm8350b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot SG IDP"; + compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp"; + qcom,board-id = <34 0>; +}; diff --git a/qcom/parrot-sg-idp-wcn3990-amoled-rcm.dts b/qcom/parrot-sg-idp-wcn3990-amoled-rcm.dts new file mode 100644 index 00000000..7375875f --- /dev/null +++ b/qcom/parrot-sg-idp-wcn3990-amoled-rcm.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrot-sg.dtsi" +#include "parrot-wcn3990.dtsi" +#include "parrot-sg-idp-wcn3990-amoled-rcm.dtsi" +#include "parrot-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot SG WCN3990 IDP + AMOLED + RCM"; + compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp"; + qcom,board-id = <34 3>; +}; diff --git a/qcom/parrot-sg-idp-wcn3990-amoled-rcm.dtsi b/qcom/parrot-sg-idp-wcn3990-amoled-rcm.dtsi new file mode 100644 index 00000000..c95e1e28 --- /dev/null +++ b/qcom/parrot-sg-idp-wcn3990-amoled-rcm.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-idp-wcn3990-amoled-rcm.dtsi" diff --git a/qcom/parrot-sg-idp-wcn3990.dts b/qcom/parrot-sg-idp-wcn3990.dts new file mode 100644 index 00000000..e17e4032 --- /dev/null +++ b/qcom/parrot-sg-idp-wcn3990.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrot-sg.dtsi" +#include "parrot-wcn3990.dtsi" +#include "parrot-sg-idp-wcn3990.dtsi" +#include "parrot-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot SG IDP + WCN3990"; + compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp"; + qcom,board-id = <34 1>; +}; diff --git a/qcom/parrot-sg-idp-wcn3990.dtsi b/qcom/parrot-sg-idp-wcn3990.dtsi new file mode 100644 index 00000000..82fd037d --- /dev/null +++ b/qcom/parrot-sg-idp-wcn3990.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-idp-wcn3990.dtsi" diff --git a/qcom/parrot-sg-idp-wcn6750-amoled-rcm.dts b/qcom/parrot-sg-idp-wcn6750-amoled-rcm.dts new file mode 100644 index 00000000..36c4918f --- /dev/null +++ b/qcom/parrot-sg-idp-wcn6750-amoled-rcm.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrot-sg.dtsi" +#include "parrot-wcn6750.dtsi" +#include "parrot-sg-idp-wcn6750-amoled-rcm.dtsi" +#include "parrot-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot SG WCN6750 IDP + AMOLED + RCM"; + compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp"; + qcom,board-id = <34 2>; +}; diff --git a/qcom/parrot-sg-idp-wcn6750-amoled-rcm.dtsi b/qcom/parrot-sg-idp-wcn6750-amoled-rcm.dtsi new file mode 100644 index 00000000..24c7f1e0 --- /dev/null +++ b/qcom/parrot-sg-idp-wcn6750-amoled-rcm.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-idp-wcn6750-amoled-rcm.dtsi" diff --git a/qcom/parrot-sg-idp-wcn6750-amoled.dts b/qcom/parrot-sg-idp-wcn6750-amoled.dts new file mode 100644 index 00000000..7abf0b43 --- /dev/null +++ b/qcom/parrot-sg-idp-wcn6750-amoled.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrot-sg.dtsi" +#include "parrot-wcn6750.dtsi" +#include "parrot-sg-idp-wcn6750-amoled.dtsi" +#include "parrot-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot SG WCN6750 IDP + AMOLED"; + compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp"; + qcom,board-id = <34 4>; +}; diff --git a/qcom/parrot-sg-idp-wcn6750-amoled.dtsi b/qcom/parrot-sg-idp-wcn6750-amoled.dtsi new file mode 100644 index 00000000..d116a8a8 --- /dev/null +++ b/qcom/parrot-sg-idp-wcn6750-amoled.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-idp-wcn6750-amoled.dtsi" diff --git a/qcom/parrot-sg-idp.dts b/qcom/parrot-sg-idp.dts new file mode 100644 index 00000000..6abb7103 --- /dev/null +++ b/qcom/parrot-sg-idp.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrot-sg.dtsi" +#include "parrot-wcn6750.dtsi" +#include "parrot-sg-idp.dtsi" +#include "parrot-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot SG IDP"; + compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp"; + qcom,board-id = <34 0>; +}; diff --git a/qcom/parrot-sg-idp.dtsi b/qcom/parrot-sg-idp.dtsi new file mode 100644 index 00000000..b82bb81e --- /dev/null +++ b/qcom/parrot-sg-idp.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-idp.dtsi" diff --git a/qcom/parrot-sg-qrd-nopmi.dts b/qcom/parrot-sg-qrd-nopmi.dts new file mode 100644 index 00000000..829d060a --- /dev/null +++ b/qcom/parrot-sg-qrd-nopmi.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrot-sg.dtsi" +#include "parrot-wcn3990.dtsi" +#include "parrot-sg-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot SG QRD"; + compatible = "qcom,parrot-qrd", "qcom,parrot", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; + qcom,pmic-id-size = <9>; + qcom,pmic-id = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; +}; diff --git a/qcom/parrot-sg-qrd-pm8350b.dts b/qcom/parrot-sg-qrd-pm8350b.dts new file mode 100644 index 00000000..6adec9b2 --- /dev/null +++ b/qcom/parrot-sg-qrd-pm8350b.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrot-sg.dtsi" +#include "parrot-wcn3990.dtsi" +#include "parrot-sg-qrd.dtsi" +#include "parrot-qrd-pm8350b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot SG QRD"; + compatible = "qcom,parrot-qrd", "qcom,parrot", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; +}; diff --git a/qcom/parrot-sg-qrd-wcn6750.dts b/qcom/parrot-sg-qrd-wcn6750.dts new file mode 100644 index 00000000..8a935708 --- /dev/null +++ b/qcom/parrot-sg-qrd-wcn6750.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrot-sg.dtsi" +#include "parrot-wcn6750.dtsi" +#include "parrot-sg-qrd-wcn6750.dtsi" +#include "parrot-qrd-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot SG WCN6750 QRD"; + compatible = "qcom,parrot-qrd", "qcom,parrot", "qcom,qrd"; + qcom,board-id = <0x1000B 1>; +}; diff --git a/qcom/parrot-sg-qrd-wcn6750.dtsi b/qcom/parrot-sg-qrd-wcn6750.dtsi new file mode 100644 index 00000000..c4b4d42b --- /dev/null +++ b/qcom/parrot-sg-qrd-wcn6750.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-qrd-wcn6750.dtsi" diff --git a/qcom/parrot-sg-qrd.dts b/qcom/parrot-sg-qrd.dts new file mode 100644 index 00000000..29ffb3a1 --- /dev/null +++ b/qcom/parrot-sg-qrd.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrot-sg.dtsi" +#include "parrot-wcn3990.dtsi" +#include "parrot-sg-qrd.dtsi" +#include "parrot-qrd-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot SG QRD"; + compatible = "qcom,parrot-qrd", "qcom,parrot", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; +}; diff --git a/qcom/parrot-sg-qrd.dtsi b/qcom/parrot-sg-qrd.dtsi new file mode 100644 index 00000000..690b6ecd --- /dev/null +++ b/qcom/parrot-sg-qrd.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-qrd.dtsi" diff --git a/qcom/parrot-sg.dts b/qcom/parrot-sg.dts new file mode 100644 index 00000000..6cd57481 --- /dev/null +++ b/qcom/parrot-sg.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrot-sg.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot SG SoC"; + compatible = "qcom,parrot"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/parrot-sg.dtsi b/qcom/parrot-sg.dtsi new file mode 100644 index 00000000..e7cdf660 --- /dev/null +++ b/qcom/parrot-sg.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot.dtsi" + +/ { + + model = "Qualcomm Technologies, Inc. Parrot SG"; + compatible = "qcom,parrot"; + qcom,msm-id = <633 0x10000>; +}; + +&msm_gpu { + /delete-property/qcom,gpu-model; + qcom,gpu-model = "AdrenoA21v1"; +}; diff --git a/qcom/parrot-stub-regulator.dtsi b/qcom/parrot-stub-regulator.dtsi new file mode 100644 index 00000000..9ab96e5a --- /dev/null +++ b/qcom/parrot-stub-regulator.dtsi @@ -0,0 +1,499 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +/ { + VDD_CX_LEVEL: + S1B_LEVEL: + pm6xxx_s1_level: regulator-pm6xxx-s1-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6xxx_s1_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + VDD_GFX_LEVEL: + S3B_LEVEL: + pm6xxx_s3_level: regulator-pm6xxx-s3-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6xxx_s3_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + VDD_EBI_LEVEL: + S5B_LEVEL: + pm6xxx_s5_level: regulator-pm6xxx-s5-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6xxx_s5_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + S6B: + pm6xxx_s6: regulator-pm6xxx-s6 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6xxx_s6"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1170000>; + }; + + S7B: + pm6xxx_s7: regulator-pm6xxx-s7 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6xxx_s7"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <418000>; + regulator-max-microvolt = <1174000>; + }; + + S8B: + pm6xxx_s8: regulator-pm6xxx-s8 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6xxx_s8"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <382000>; + regulator-max-microvolt = <1654000>; + }; + + S9B: + pm6xxx_s9: regulator-pm6xxx-s9 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6xxx_s9"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <2200000>; + }; + + L1B: + pm6xxx_l1: regulator-pm6xxx-l1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6xxx_l1"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <650000>; + }; + + VDD_LPI_CX_LEVEL: + L2B_LEVEL: + pm6xxx_l2_level: regulator-pm6xxx-l2-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6xxx_l2_level"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + L3B: + pm6xxx_l3: regulator-pm6xxx-l3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6xxx_l3"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + }; + + L4B: + pm6xxx_l4: regulator-pm6xxx-l4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6xxx_l4"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <530000>; + regulator-max-microvolt = <864000>; + }; + + L5B: + pm6xxx_l5: regulator-pm6xxx-l5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6xxx_l5"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <830000>; + regulator-max-microvolt = <920000>; + }; + + L6B: + pm6xxx_l6: regulator-pm6xxx-l6 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6xxx_l6"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <751000>; + regulator-max-microvolt = <824000>; + }; + + L7B: + pm6xxx_l7: regulator-pm6xxx-l7 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6xxx_l7"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <830000>; + regulator-max-microvolt = <920000>; + }; + + L8B: + pm6xxx_l8: regulator-pm6xxx-l8 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6xxx_l8"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + }; + + VDD_LPI_MX_LEVEL: + L9B_LEVEL: + pm6xxx_l9_level: regulator-pm6xxx-l9-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6xxx_l9_level"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + L10B: + pm6xxx_l10: regulator-pm6xxx-l10 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6xxx_l10"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <824000>; + regulator-max-microvolt = <950000>; + }; + + L11B: + pm6xxx_l11: regulator-pm6xxx-l11 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6xxx_l11"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <348000>; + regulator-max-microvolt = <888000>; + }; + + L12B: + pm6xxx_l12: regulator-pm6xxx-l12 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6xxx_l12"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1304000>; + }; + + L13B: + pm6xxx_l13: regulator-pm6xxx-l13 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6xxx_l13"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1304000>; + }; + + L14B: + pm6xxx_l14: regulator-pm6xxx-l14 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6xxx_l14"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1304000>; + }; + + L15B: + pm6xxx_l15: regulator-pm6xxx-l15 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6xxx_l15"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <1304000>; + }; + + L16B: + pm6xxx_l16: regulator-pm6xxx-l16 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6xxx_l16"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + }; + + L17B: + pm6xxx_l17: regulator-pm6xxx-l17 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6xxx_l17"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <1170000>; + regulator-max-microvolt = <1304000>; + }; + + L18B: + pm6xxx_l18: regulator-pm6xxx-l18 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6xxx_l18"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + }; + + L19B: + pm6xxx_l19: regulator-pm6xxx-l19 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6xxx_l19"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + }; + + L20B: + pm6xxx_l20: regulator-pm6xxx-l20 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6xxx_l20"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + }; + + L21B: + pm6xxx_l21: regulator-pm6xxx-l21 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6xxx_l21"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <1950000>; + }; + + L22B: + pm6xxx_l22: regulator-pm6xxx-l22 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6xxx_l22"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + }; + + L23B: + pm6xxx_l23: regulator-pm6xxx-l23 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6xxx_l23"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + }; + + L24B: + pm6xxx_l24: regulator-pm6xxx-l24 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6xxx_l24"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3544000>; + }; + + L25B: + pm6xxx_l25: regulator-pm6xxx-l25 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6xxx_l25"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + }; + + L26B: + pm6xxx_l26: regulator-pm6xxx-l26 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6xxx_l26"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + }; + + L27B: + pm6xxx_l27: regulator-pm6xxx-l27 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6xxx_l27"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + }; + + L28B: + pm6xxx_l28: regulator-pm6xxx-l28 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6xxx_l28"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + }; + + VDD_MODEM_LEVEL: + S1E_LEVEL: + pm6150l_s1_level: regulator-pm6150l-s1-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_s1_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + VDD_MXA_LEVEL: + S3E_LEVEL: + pm6150l_s3_level: regulator-pm6150l-s3-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_s3_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + S8E: + pm6150l_s8: regulator-pm6150l-s8 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_s8"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <2040000>; + }; + + L1E: + pm6150l_l1: regulator-pm6150l-l1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_l1"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + }; + + L4E: + pm6150l_l4: regulator-pm6150l-l4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_l4"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + }; + + L5E: + pm6150l_l5: regulator-pm6150l-l5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_l5"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <3544000>; + }; + + L6E: + pm6150l_l6: regulator-pm6150l-l6 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_l6"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3300000>; + }; + + L7E: + pm6150l_l7: regulator-pm6150l-l7 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_l7"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3544000>; + }; + + L8E: + pm6150l_l8: regulator-pm6150l-l8 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_l8"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + }; + + L9E: + pm6150l_l9: regulator-pm6150l-l9 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_l9"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + }; + + L10E: + pm6150l_l10: regulator-pm6150l-l10 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_l10"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; + }; + + L11E: + pm6150l_l11: regulator-pm6150l-l11 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_l11"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; + }; + + BOB: + pm6150l_bob: regulator-pm6150l-bob { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_bob"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <5500000>; + }; + + L2G: + pmr735a_l2: regulator-pmr735a-l2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmr735a_l2"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1236000>; + }; + + L3G: + pmr735a_l3: regulator-pmr735a-l3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmr735a_l3"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <830000>; + regulator-max-microvolt = <939000>; + }; + + L4G: + pmr735a_l4: regulator-pmr735a-l4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmr735a_l4"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1854000>; + }; + + L5G: + pmr735a_l5: regulator-pmr735a-l5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmr735a_l5"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <760000>; + regulator-max-microvolt = <824000>; + }; + + L6G: + pmr735a_l6: regulator-pmr735a-l6 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmr735a_l6"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <588000>; + regulator-max-microvolt = <800000>; + }; +}; diff --git a/qcom/parrot-thermal-overlay.dtsi b/qcom/parrot-thermal-overlay.dtsi new file mode 100644 index 00000000..9eee0535 --- /dev/null +++ b/qcom/parrot-thermal-overlay.dtsi @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&thermal_zones { + pm6150l-bcl-lvl0 { + cooling-maps { + vph_lte0 { + trip = <&l_bcl_lvl0>; + cooling-device = <&modem_lte_dsc 8 8>; + }; + + vph_nr0_scg { + trip = <&l_bcl_lvl0>; + cooling-device = <&modem_nr_scg_dsc 3 3>; + }; + + vph_nr0 { + trip = <&l_bcl_lvl0>; + cooling-device = <&modem_nr_dsc 6 6>; + }; + + vph_cdsp0 { + trip = <&l_bcl_lvl0>; + cooling-device = <&cdsp_sw 2 2>; + }; + + vph_cpu_5 { + trip = <&l_bcl_lvl0>; + cooling-device = <&cpu5_pause 1 1>; + }; + + vph_gpu0 { + trip = <&l_bcl_lvl0>; + cooling-device = <&msm_gpu 1 1>; + }; + }; + }; + + pm6150l-bcl-lvl1 { + cooling-maps { + vph_lte1 { + trip = <&l_bcl_lvl1>; + cooling-device = <&modem_lte_dsc 10 10>; + }; + + vph_nr1_scg { + trip = <&l_bcl_lvl1>; + cooling-device = <&modem_nr_scg_dsc 10 10>; + }; + + vph_nr1 { + trip = <&l_bcl_lvl1>; + cooling-device = <&modem_nr_dsc 9 9>; + }; + + vph_cdsp1 { + trip = <&l_bcl_lvl1>; + cooling-device = <&cdsp_sw 4 4>; + }; + + vph_cpu_6_7 { + trip = <&l_bcl_lvl1>; + cooling-device = <&cpu_6_7_pause 1 1>; + }; + + vph_gpu1 { + trip = <&l_bcl_lvl1>; + cooling-device = <&msm_gpu 2 2>; + }; + }; + }; + + pm6150l-bcl-lvl2 { + cooling-maps { + vph_cdsp2 { + trip = <&l_bcl_lvl2>; + cooling-device = <&cdsp_sw 5 THERMAL_NO_LIMIT>; + }; + + vph_gpu2 { + trip = <&l_bcl_lvl2>; + cooling-device = <&msm_gpu 3 THERMAL_NO_LIMIT>; + }; + }; + }; + + pm6450_tz { + cooling-maps { + pm6450_gpu { + trip = <&pm6450_trip0>; + cooling-device = <&msm_gpu 3 THERMAL_NO_LIMIT>; + }; + + pm6450_cdsp { + trip = <&pm6450_trip0>; + cooling-device = <&cdsp_sw 5 THERMAL_NO_LIMIT>; + }; + }; + }; + + pm6150l_tz { + cooling-maps { + pm6150l_lte { + trip = <&pm6150l_trip0>; + cooling-device = <&modem_lte_dsc 255 255>; + }; + + pm6150l_nr { + trip = <&pm6150l_trip0>; + cooling-device = <&modem_nr_scg_dsc 255 255>; + }; + + pm6150l_cpu0 { + trip = <&pm6150l_trip0>; + cooling-device = <&cpu0_pause 1 1>; + }; + + pm6150l_cpu1 { + trip = <&pm6150l_trip0>; + cooling-device = <&cpu1_pause 1 1>; + }; + + pm6150l_cpu2 { + trip = <&pm6150l_trip0>; + cooling-device = <&cpu2_pause 1 1>; + }; + + pm6150l_cpu3 { + trip = <&pm6150l_trip0>; + cooling-device = <&cpu3_pause 1 1>; + }; + + pm6150l_apc1 { + trip = <&pm6150l_trip0>; + cooling-device = <&APC1_pause 1 1>; + }; + }; + }; +}; diff --git a/qcom/parrot-thermal.dtsi b/qcom/parrot-thermal.dtsi new file mode 100644 index 00000000..2bbd3506 --- /dev/null +++ b/qcom/parrot-thermal.dtsi @@ -0,0 +1,1165 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&msm_gpu { + #cooling-cells = <2>; +}; + +&soc { + tsens0: thermal-sensor@c263000 { + compatible = "qcom,tsens-v2"; + reg = <0x0c263000 0x1ff>, /* TM */ + <0x0c222000 0x1ff>; /* SROT */ + #qcom,sensors = <16>; + interrupts = , + , + ; + interrupt-names = "uplow","critical", "cold"; + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c265000 { + compatible = "qcom,tsens-v2"; + reg = <0x0c265000 0x1ff>, /* TM */ + <0x0c223000 0x1ff>; /* SROT */ + #qcom,sensors = <16>; + interrupts = , + , + ; + interrupt-names = "uplow","critical", "cold"; + #thermal-sensor-cells = <1>; + }; + + qcom,cpu-pause { + compatible = "qcom,thermal-pause"; + + cpu0_pause: cpu0-pause { + qcom,cpus = <&CPU0>; + qcom,cdev-alias = "thermal-pause-1"; + #cooling-cells = <2>; + }; + + cpu1_pause: cpu1-pause { + qcom,cpus = <&CPU1>; + qcom,cdev-alias = "thermal-pause-2"; + #cooling-cells = <2>; + }; + + cpu2_pause: cpu2-pause { + qcom,cpus = <&CPU2>; + qcom,cdev-alias = "thermal-pause-4"; + #cooling-cells = <2>; + }; + + cpu3_pause: cpu3-pause { + qcom,cpus = <&CPU3>; + qcom,cdev-alias = "thermal-pause-8"; + #cooling-cells = <2>; + }; + + cpu5_pause: cpu5-pause { + qcom,cpus = <&CPU5>; + qcom,cdev-alias = "thermal-pause-20"; + #cooling-cells = <2>; + }; + + cpu6_pause: cpu6-pause { + qcom,cpus = <&CPU6>; + qcom,cdev-alias = "thermal-pause-40"; + #cooling-cells = <2>; + }; + + cpu7_pause: cpu7-pause { + qcom,cpus = <&CPU7>; + qcom,cdev-alias = "thermal-pause-80"; + #cooling-cells = <2>; + }; + + APC1_pause: apc1-pause { + qcom,cpus = <&CPU5 &CPU6 &CPU7>; + qcom,cdev-alias = "thermal-pause-E0"; + #cooling-cells = <2>; + }; + + cpu_6_7_pause: cpu-6-7-pause { + qcom,cpus = <&CPU6 &CPU7>; + qcom,cdev-alias = "thermal-pause-C0"; + #cooling-cells = <2>; + }; + + /* Thermal-engine cooling devices */ + pause-cpu0 { + qcom,cpus = <&CPU0>; + qcom,cdev-alias = "pause-cpu0"; + }; + + pause-cpu1 { + qcom,cpus = <&CPU1>; + qcom,cdev-alias = "pause-cpu1"; + }; + + pause-cpu2 { + qcom,cpus = <&CPU2>; + qcom,cdev-alias = "pause-cpu2"; + }; + + pause-cpu3 { + qcom,cpus = <&CPU3>; + qcom,cdev-alias = "pause-cpu3"; + }; + + pause-cpu5 { + qcom,cpus = <&CPU5>; + qcom,cdev-alias = "pause-cpu5"; + }; + + pause-cpu6 { + qcom,cpus = <&CPU6>; + qcom,cdev-alias = "pause-cpu6"; + }; + + pause-cpu7 { + qcom,cpus = <&CPU7>; + qcom,cdev-alias = "pause-cpu7"; + }; + }; + + qcom,cpu-hotplug { + compatible = "qcom,cpu-hotplug"; + + cpu0_hotplug: cpu0-hotplug { + qcom,cpu = <&CPU0>; + qcom,cdev-alias = "cpu-hotplug0"; + #cooling-cells = <2>; + }; + + cpu1_hotplug: cpu1-hotplug { + qcom,cpu = <&CPU1>; + qcom,cdev-alias = "cpu-hotplug1"; + #cooling-cells = <2>; + }; + + cpu2_hotplug: cpu2-hotplug { + qcom,cpu = <&CPU2>; + qcom,cdev-alias = "cpu-hotplug2"; + #cooling-cells = <2>; + }; + + cpu3_hotplug: cpu3-hotplug { + qcom,cpu = <&CPU3>; + qcom,cdev-alias = "cpu-hotplug3"; + #cooling-cells = <2>; + }; + + cpu5_hotplug: cpu5-hotplug { + qcom,cpu = <&CPU5>; + qcom,cdev-alias = "cpu-hotplug5"; + #cooling-cells = <2>; + }; + + cpu6_hotplug: cpu6-hotplug { + qcom,cpu = <&CPU6>; + qcom,cdev-alias = "cpu-hotplug6"; + #cooling-cells = <2>; + }; + + cpu7_hotplug: cpu7-hotplug { + qcom,cpu = <&CPU7>; + qcom,cdev-alias = "cpu-hotplug7"; + #cooling-cells = <2>; + }; + }; + + thermal_ddr_freq_table: thermal-ddr-freq-table { + qcom,freq-tbl = < 2092800 >; + }; + + ddr_cdev: qcom,ddr-cdev { + compatible = "qcom,ddr-cooling-device"; + #cooling-cells = <2>; + qcom,freq-table = <&thermal_ddr_freq_table>; + qcom,bus-width = <4>; + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; + }; + + qmi_tmd: qmi-tmd-devices { + compatible = "qcom,qmi-cooling-devices"; + cdsp { + qcom,instance-id = ; + + cdsp_sw: cdsp { + qcom,qmi-dev-name = "cdsp_sw"; + #cooling-cells = <2>; + }; + + cdsp_hw: cdsp_hw { + qcom,qmi-dev-name = "cdsp_hw"; + #cooling-cells = <2>; + }; + }; + }; + + qcom,cpufreq-cdev { + compatible = "qcom,cpufreq-cdev"; + cpu-cluster0 { + qcom,cpus = <&CPU0 &CPU1 &CPU2 &CPU3>; + }; + + cpu-cluster1 { + qcom,cpus = <&CPU4 &CPU5 &CPU6 &CPU7>; + }; + }; + + qcom,devfreq-cdev { + compatible = "qcom,devfreq-cdev"; + qcom,devfreq = <&msm_gpu>; + }; + + qcom,userspace-cdev { + compatible = "qcom,userspace-cooling-devices"; + + display_fps: display-fps { + qcom,max-level = <3>; + #cooling-cells = <2>; + }; + }; +}; + +#include "waipio-thermal-modem.dtsi" + +&soc { + qmi-tmd-devices { + /delete-node/ modem_usr; + /delete-node/ cdsp_usr; + }; +}; + +&thermal_zones { + /delete-node/ sdr-mmw-therm; + /delete-node/ mmw_pa1; + /delete-node/ mmw_pa2; + /delete-node/ mmw_pa3; + + aoss-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 0>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 1>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 2>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 3>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cpu4_emerg0: cpu4-emerg0-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-1-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 4>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cpu4_emerg1: cpu4-emerg1-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-1-2 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens0 5>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cpu5_emerg0: cpu5-emerg0-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu12_cdev { + trip = <&cpu5_emerg0>; + cooling-device = <&cpu5_pause 1 1>; + }; + }; + }; + + cpu-1-3 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens0 6>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cpu5_emerg1: cpu5-emerg1-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu13_cdev { + trip = <&cpu5_emerg1>; + cooling-device = <&cpu5_pause 1 1>; + }; + }; + }; + + cpu-1-4 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens0 7>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cpu6_emerg0: cpu6-emerg0-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu14_cdev { + trip = <&cpu6_emerg0>; + cooling-device = <&cpu6_pause 1 1>; + }; + }; + }; + + cpu-1-5 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens0 8>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cpu6_emerg1: cpu6-emerg1-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu15_cdev { + trip = <&cpu6_emerg1>; + cooling-device = <&cpu6_pause 1 1>; + }; + }; + }; + + cpu-1-6 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens0 9>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cpu7_emerg0: cpu7-emerg0-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu16_cdev { + trip = <&cpu7_emerg0>; + cooling-device = <&cpu7_pause 1 1>; + }; + }; + }; + + cpu-1-7 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens0 10>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cpu7_emerg1: cpu7-emerg1-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu17_cdev { + trip = <&cpu7_emerg1>; + cooling-device = <&cpu7_pause 1 1>; + }; + }; + }; + + gpuss-0 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens0 11>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + gpu0_tj_cfg: tj_cfg { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + gpu0_cdev { + trip = <&gpu0_tj_cfg>; + cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>; + }; + }; + }; + + gpuss-1 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens0 12>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + gpu1_tj_cfg: tj_cfg { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + gpu1_cdev { + trip = <&gpu1_tj_cfg>; + cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>; + }; + }; + }; + + camera-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 13>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + aoss-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 0>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-0-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 1>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cpu0_emerg: cpu0-emerg-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu00_cdev { + trip = <&cpu0_emerg>; + cooling-device = <&cpu0_pause 1 1>; + }; + }; + }; + + cpu-0-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 2>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cpu1_emerg: cpu1-emerg-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu01_cdev { + trip = <&cpu1_emerg>; + cooling-device = <&cpu1_pause 1 1>; + }; + }; + }; + + cpu-0-2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 3>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cpu2_emerg: cpu2-emerg-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu02_cdev { + trip = <&cpu2_emerg>; + cooling-device = <&cpu2_pause 1 1>; + }; + }; + }; + + cpu-0-3 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 4>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cpu3_emerg: cpu3-emerg-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu03_cdev { + trip = <&cpu3_emerg>; + cooling-device = <&cpu3_pause 1 1>; + }; + }; + }; + + nspss-0 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 5>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + nspss_0_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + nsp_cdev { + trip = <&nspss_0_config>; + cooling-device = <&cdsp_sw THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + nspss-1 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 6>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + nspss_1_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + nsp_cdev { + trip = <&nspss_1_config>; + cooling-device = <&cdsp_sw THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + nspss-2 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 7>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + nspss_2_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + nsp_cdev { + trip = <&nspss_2_config>; + cooling-device = <&cdsp_sw THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + video { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 8>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + ddr { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 9>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + ddr_config0: ddr0-config { + temperature = <90000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + gold_cdev0 { + trip = <&ddr_config0>; + cooling-device = <&CPU4 + THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + gold_cdev1 { + trip = <&ddr_config0>; + cooling-device = <&CPU5 + THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + gold_cdev2 { + trip = <&ddr_config0>; + cooling-device = <&CPU6 + THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + gold_plus_cdev { + trip = <&ddr_config0>; + cooling-device = <&CPU7 + THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + ddr_cdev { + trip = <&ddr_config0>; + cooling-device = <&ddr_cdev 1 1>; + }; + }; + }; + + mdmss-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 10>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdmss-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 11>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdmss-2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 12>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdmss-3 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 13>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + zeroc-0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 128>; + trips { + thermal-engine-config { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + + min_temp_0_trip: cold-trip { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + zeroc-1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 128>; + trips { + thermal-engine-config { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + + min_temp_1_trip: cold-trip { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; +}; diff --git a/qcom/parrot-usb.dtsi b/qcom/parrot-usb.dtsi new file mode 100644 index 00000000..b67043a5 --- /dev/null +++ b/qcom/parrot-usb.dtsi @@ -0,0 +1,315 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&soc { + usb0: ssusb@a600000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0xa600000 0x100000>; + reg-names = "core_base"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>; + clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk"; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + reset-names = "core_reset"; + + interrupts-extended = <&pdc 14 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 15 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + "ss_phy_irq", "dm_hs_phy_irq"; + qcom,use-pdc-interrupts; + + qcom,core-clk-rate = <133333333>; + qcom,core-clk-rate-hs = <66666667>; + qcom,pm-qos-latency = <2>; + qcom,num-gsi-evt-buffs = <0x3>; + qcom,gsi-reg-offset = + <0x0fc /* GSI_GENERAL_CFG */ + 0x110 /* GSI_DBL_ADDR_L */ + 0x120 /* GSI_DBL_ADDR_H */ + 0x130 /* GSI_RING_BASE_ADDR_L */ + 0x144 /* GSI_RING_BASE_ADDR_H */ + 0x1a4>; /* GSI_IF_STS */ + + interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb"; + interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>, + <&aggre1_noc MASTER_USB3_0 &cnoc2 SLAVE_IPA_CFG>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_USB3_0>; + + dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0xa600000 0xd800>; + + iommus = <&apps_smmu 0x80 0x0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + dma-coherent; + + interrupts = ; + usb-phy = <&usb2_phy0>, <&usb_qmp_dp_phy>; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,is-utmi-l1-suspend; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + tx-fifo-resize; + dr_mode = "peripheral"; + maximum-speed = "super-speed"; + }; + + }; + + /* USB port related High Speed PHY */ + usb2_phy0: hsphy@88e3000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x88e3000 0x11c>, + <0x088e2000 0x4>; + reg-names = "hsusb_phy_base", + "eud_enable_reg"; + + vdd-supply = <&L5B>; + vdda18-supply = <&L23B>; + vdda33-supply = <&L25B>; + qcom,vdd-voltage-level = <0 880000 920000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_EUSB3_0_CLKREF_EN>; + clock-names = "ref_clk_src", "ref_clk"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + }; + + /* USB port related QMP USB DP Combo PHY */ + usb_qmp_dp_phy: ssphy@88e8000 { + compatible = "qcom,usb-ssphy-qmp-dp-combo"; + reg = <0x88e8000 0x3000>; + reg-names = "qmp_phy_base"; + + vdd-supply = <&L7B>; + qcom,vdd-voltage-level = <0 912000 912000>; + qcom,vdd-max-load-uA = <47000>; + core-supply = <&L16B>; + + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, + <&gcc GCC_USB3_PHY_PRIM_BCR>; + reset-names = "global_phy_reset", "phy_reset"; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_0_CLKREF_EN>; + clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", + "pipe_clk_ext_src", "ref_clk_src", + "com_aux_clk", "ref_clk"; + + pinctrl-names = "default"; + pinctrl-0 = <&usb3phy_portselect_default>; + + qcom,qmp-phy-reg-offset = + ; + + qcom,qmp-phy-init-seq = + /* */ + ; + }; + + usb_audio_qmi_dev { + compatible = "qcom,usb-audio-qmi-dev"; + iommus = <&apps_smmu 0x180f 0x0>; + qcom,iommu-dma = "disabled"; + qcom,usb-audio-stream-id = <0xf>; + qcom,usb-audio-intr-num = <2>; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + +}; diff --git a/qcom/parrot-wcn3990.dtsi b/qcom/parrot-wcn3990.dtsi new file mode 100644 index 00000000..882065c4 --- /dev/null +++ b/qcom/parrot-wcn3990.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&reserved_memory { + wlan_fw_mem: wlan_fw_region@82a00000 { + no-map; + reg = <0x0 0x82a00000 0x0 0x300000>; + }; +}; + +&soc { + wpss_pas: remoteproc-wpss@8a00000 { + firmware-name = "adrastea/wpss.mdt"; + }; + + bluetooth: bt_wcn3990 { + compatible = "qcom,wcn3990"; + qcom,bt-sw-ctrl-gpio = <&tlmm 61 GPIO_ACTIVE_HIGH>; + qcom,bt-vdd-io-supply = <&L22B>; /* IO */ + qcom,bt-vdd-core-supply = <&L14B>; /* RFA */ + qcom,bt-vdd-pa-supply = <&L10E>; /* CH0 */ + qcom,bt-vdd-xtal-supply = <&L1E>; /* XO */ + + qcom,bt-vdd-io-config = <1700000 1900000 1 0>; + qcom,bt-vdd-core-config = <1304000 1304000 1 0>; + qcom,bt-vdd-pa-config = <3000000 3312000 1 0>; + qcom,bt-vdd-xtal-config = <1700000 1900000 1 0>; + }; +}; diff --git a/qcom/parrot-wcn6750.dtsi b/qcom/parrot-wcn6750.dtsi new file mode 100644 index 00000000..2737d1d9 --- /dev/null +++ b/qcom/parrot-wcn6750.dtsi @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + bluetooth: bt_wcn6750 { + compatible = "qcom,wcn6750-bt"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_en_sleep>; + qcom,bt-reset-gpio = <&tlmm 35 0>; /* BT_EN */ + qcom,bt-sw-ctrl-gpio = <&tlmm 61 0>; /* SW_CTRL */ + qcom,wl-reset-gpio = <&tlmm 36 0>; /* WL_EN */ + tsens = "quiet-therm"; + + qcom,bt-vdd-io-supply = <&L22B>; /* IO */ + qcom,bt-vdd-aon-supply = <&S7B>; + qcom,bt-vdd-dig-supply = <&S7B>; /* BT_CX_MX */ + qcom,bt-vdd-rfacmn-supply = <&S7B>; + qcom,bt-vdd-rfa-0p8-supply = <&S7B>; + qcom,bt-vdd-rfa1-supply = <&S8E>; /*RFA 1p7*/ + qcom,bt-vdd-rfa2-supply = <&S8B>; /*RFA 1p2*/ + qcom,bt-vdd-ipa-2p2-supply = <&S9B>; /*IPA 2p2*/ + //qcom,bt-vdd-asd-supply = <&L11C>; + + /* max voltage are set to regulator max voltage supported */ + qcom,bt-vdd-io-config = <1800000 2000000 0 1>; + qcom,bt-vdd-aon-config = <824000 1174000 0 1>; + qcom,bt-vdd-dig-config = <824000 1174000 0 1>; + qcom,bt-vdd-rfacmn-config = <824000 1174000 0 1>; + qcom,bt-vdd-rfa-0p8-config = <824000 1174000 0 1>; + qcom,bt-vdd-rfa1-config = <1872000 2040000 0 1>; + qcom,bt-vdd-rfa2-config = <1256000 1654000 0 1>; + qcom,bt-vdd-ipa-2p2-config = <2200000 2208000 0 1>; + //qcom,bt-vdd-asd-config = <2800000 3544000 0 1>; + }; + + qcom,smp2p-wpss { + smp2p_wlan_2_in: qcom,smp2p-wlan-2-in { + qcom,entry-name = "wlan_soc_wake"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_wlan_2_out: qcom,smp2p-wlan-2-out { + qcom,entry-name = "wlan_soc_wake"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_wlan_3_out: qcom,smp2p-wlan-3-out { + qcom,entry-name = "wlan_ep_power_save"; + #qcom,smem-state-cells = <1>; + }; + }; + + wpss_pas: remoteproc-wpss@8a00000 { + firmware-name = "qca6750/wpss.mdt"; + }; + + icnss2: qcom,wcn6750 { + compatible = "qcom,wcn6750"; + reg = <0x17210040 0x0>, + <0xb0000000 0x10000>; + reg-names = "msi_addr", "smmu_iova_ipa"; + qcom,rproc-handle = <&wpss_pas>; + iommus = <&apps_smmu 0x1c00 0x1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + qcom,iommu-dma = "fastmap"; + qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal"; + qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; + qcom,iommu-geometry = <0xa0000000 0x10010000>; + dma-coherent; + qcom,fw-prefix; + qcom,wlan; + tsens = "quiet-therm"; + qcom,wlan-msa-fixed-region = <&wlan_fw_mem>; + vdd-cx-mx-supply = <&S7B>; + qcom,vdd-cx-mx-config = <880000 1120000 0 0 1>; + vdd-1.8-xo-supply = <&S8E>; + qcom,vdd-1.8-xo-config = <1872000 2040000 0 0 0>; + vdd-1.3-rfa-supply = <&S8B>; + qcom,vdd-1.3-rfa-config = <1256000 1500000 0 0 0>; + + qcom,smem-states = <&smp2p_wlan_1_out 0>, + <&smp2p_wlan_2_out 0>, + <&smp2p_wlan_3_out 0>; + qcom,smem-state-names = "wlan-smp2p-out", + "wlan-soc-wake-smp2p-out", + "wlan-ep-powersave-smp2p-out"; + + mboxes = <&qmp_aop 0>; + qcom,vreg_ol_cpr ="s7b"; + + icnss_cdev_apss: qcom,icnss_cdev1 { + #cooling-cells = <2>; + }; + + icnss_cdev_wpss: qcom,icnss_cdev2 { + #cooling-cells = <2>; + }; + + qcom,smp2p_map_wlan_1_in { + interrupts-extended = <&smp2p_wlan_1_in 0 0>, + <&smp2p_wlan_1_in 1 0>; + interrupt-names = "qcom,smp2p-force-fatal-error", + "qcom,smp2p-early-crash-ind"; + }; + + qcom,smp2p_map_wlan_2_in { + interrupts-extended = <&smp2p_wlan_2_in 0 0>; + interrupt-names = "qcom,smp2p-soc-wake-ack"; + }; + }; +}; + +&qupv3_se2_i2c { + status = "ok"; +}; diff --git a/qcom/parrot.dts b/qcom/parrot.dts new file mode 100644 index 00000000..b633b976 --- /dev/null +++ b/qcom/parrot.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrot.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot SoC"; + compatible = "qcom,parrot"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/parrot.dtsi b/qcom/parrot.dtsi new file mode 100644 index 00000000..c3c5497c --- /dev/null +++ b/qcom/parrot.dtsi @@ -0,0 +1,2861 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + model = "Qualcomm Technologies, Inc. Parrot"; + compatible = "qcom,parrot"; + qcom,msm-id = <537 0x10000>, <613 0x10000>; + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen: chosen { + stdout-path = "/soc/qcom,qup_uart@98c000:115200n8"; + bootargs = "console=ttyMSM0,115200n8 loglevel=6 log_buf_len=256K kernel.panic_on_rcu_stall=1 loop.max_part=7 pcie_ports=compat allow_mismatched_32bit_el0 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 ftrace_dump_on_oops pstore.compress=none kpti=0 swiotlb=noforce cgroup.memory=nokmem,nosocket kswapd_per_node=2 slub_debug=- allow_file_spec_access cpufreq.default_governor=performance transparent_hugepage=never page_poison=on can.stats_timer=0 disable_dma32=on android12_only.will_be_removed_soon.memblock_nomap_remove=on"; + }; + + memory { device_type = "memory"; reg = <0 0 0 0>; }; + + ddr-regions { }; + + reserved_memory: reserved-memory { }; + + mem-offline { + compatible = "qcom,mem-offline"; + offline-sizes = <0x1 0x40000000 0x0 0x40000000>, + <0x1 0xc0000000 0x0 0x80000000>, + <0x2 0xc0000000 0x1 0x40000000>; + granule = <512>; + mboxes = <&qmp_aop 0>; + }; + + aliases: aliases { + mmc0 = &sdhc_1; /*SDC1 eMMC slot*/ + mmc1 = &sdhc_2; /* SDC2 SD card slot */ + ufshc1 = &ufshc_mem; /* Embedded UFS Slot */ + serial0 = &qupv3_se3_2uart; + hsuart0 = &qupv3_se11_4uart; + }; + + mmio_sram: mmio-sram@17D09100 { + #address-cells = <2>; + #size-cells = <2>; + compatible = "mmio-sram"; + reg = <0x0 0x17D09100 0x0 0x200>; + ranges = <0x0 0x0 0x0 0x17D09100 0x0 0x200>; + + cpu_scp_lpri: scp-shmem@0 { + compatible = "arm,scp-shmem"; + reg = <0x0 0x0 0x0 0x200>; + }; + }; + + firmware: firmware {}; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + cpu-idle-states = <&LITTLE_CPU_OFF &LITTLE_CPU_RAIL_OFF>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0 4>; + next-level-cache = <&L2_0>; + #cooling-cells = <2>; + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + + L3_0: l3-cache { + compatible = "cache"; + cache-level = <3>; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x100>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + cpu-idle-states = <&LITTLE_CPU_OFF &LITTLE_CPU_RAIL_OFF>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0 4>; + next-level-cache = <&L2_1>; + #cooling-cells = <2>; + L2_1: l2-cache { + compatible = "cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x200>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + cpu-idle-states = <&LITTLE_CPU_OFF &LITTLE_CPU_RAIL_OFF>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0 4>; + next-level-cache = <&L2_2>; + #cooling-cells = <2>; + L2_2: l2-cache { + compatible = "cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x300>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + cpu-idle-states = <&LITTLE_CPU_OFF &LITTLE_CPU_RAIL_OFF>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0 4>; + next-level-cache = <&L2_3>; + #cooling-cells = <2>; + L2_3: l2-cache { + compatible = "cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x400>; + capacity-dmips-mhz = <1945>; + dynamic-power-coefficient = <483>; + enable-method = "psci"; + cpu-idle-states = <&BIG_CPU_OFF &BIG_CPU_RAIL_OFF>; + power-domains = <&CPU_PD4>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1 4>; + next-level-cache = <&L2_4>; + #cooling-cells = <2>; + L2_4: l2-cache { + compatible = "cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x500>; + capacity-dmips-mhz = <1945>; + dynamic-power-coefficient = <483>; + enable-method = "psci"; + cpu-idle-states = <&BIG_CPU_OFF &BIG_CPU_RAIL_OFF>; + power-domains = <&CPU_PD5>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1 4>; + next-level-cache = <&L2_5>; + #cooling-cells = <2>; + L2_5: l2-cache { + compatible = "cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x600>; + capacity-dmips-mhz = <1945>; + dynamic-power-coefficient = <483>; + enable-method = "psci"; + cpu-idle-states = <&BIG_CPU_OFF &BIG_CPU_RAIL_OFF>; + power-domains = <&CPU_PD6>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1 4>; + next-level-cache = <&L2_6>; + #cooling-cells = <2>; + L2_6: l2-cache { + compatible = "cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x700>; + capacity-dmips-mhz = <1945>; + dynamic-power-coefficient = <483>; + enable-method = "psci"; + cpu-idle-states = <&BIG_CPU_OFF &BIG_CPU_RAIL_OFF>; + power-domains = <&CPU_PD7>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1 4>; + next-level-cache = <&L2_7>; + #cooling-cells = <2>; + L2_7: l2-cache { + compatible = "cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + + core3 { + cpu = <&CPU7>; + }; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + LITTLE_CPU_OFF: silver-c3 { /* C3 */ + compatible = "arm,idle-state"; + idle-state-name = "pc"; + entry-latency-us = <350>; + exit-latency-us = <900>; + min-residency-us = <1774>; + arm,psci-suspend-param = <0x40000003>; + local-timer-stop; + }; + + LITTLE_CPU_RAIL_OFF: silver-c4 { /* C4 */ + compatible = "arm,idle-state"; + idle-state-name = "rail-pc"; + entry-latency-us = <800>; + exit-latency-us = <750>; + min-residency-us = <4090>; + arm,psci-suspend-param = <0x40000004>; + local-timer-stop; + }; + + BIG_CPU_OFF: gold-c3 { /* C3 */ + compatible = "arm,idle-state"; + idle-state-name = "pc"; + entry-latency-us = <400>; + exit-latency-us = <1550>; + min-residency-us = <2207>; + arm,psci-suspend-param = <0x40000003>; + local-timer-stop; + }; + + BIG_CPU_RAIL_OFF: gold-c4 { /* C4 */ + compatible = "arm,idle-state"; + idle-state-name = "rail-pc"; + entry-latency-us = <600>; + exit-latency-us = <1550>; + min-residency-us = <4791>; + arm,psci-suspend-param = <0x40000004>; + local-timer-stop; + }; + + CLUSTER_OFF: cluster-d4 { /* D4 */ + compatible = "domain-idle-state"; + idle-state-name = "l3-off"; + entry-latency-us = <1050>; + exit-latency-us = <2500>; + min-residency-us = <5309>; + arm,psci-suspend-param = <0x41000044>; + }; + + CX_RET: cx-ret { /* Cx Ret */ + compatible = "domain-idle-state"; + idle-state-name = "cx-ret"; + entry-latency-us = <1561>; + exit-latency-us = <2801>; + min-residency-us = <8550>; + arm,psci-suspend-param = <0x41003344>; + }; + }; + + soc: soc { }; + +}; + +&firmware { + qcom_scm { + compatible = "qcom,scm"; + qcom,dload-mode = <&tcsr 0x13000>; + }; + + qtee_shmbridge { + compatible = "qcom,tee-shared-memory-bridge"; + }; + + qcom_smcinvoke { + compatible = "qcom,smcinvoke"; + }; + +}; + +#include "parrot-usb.dtsi" +#include "parrot-reserved-memory.dtsi" +#include "parrot-coresight.dtsi" +#include "parrot-debug.dtsi" +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + system_cma: linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2000000>; + linux,cma-default; + }; + + ramoops_mem: ramoops_region { + alloc-ranges = <0x0 0x00000000 0xffffffff 0xffffffff>; + size = <0x0 0x200000>; + no-map; + }; + + adsp_mem_heap: adsp_heap_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0xC00000>; + }; + + audio_cma_mem: audio_cma_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + sdsp_mem: sdsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x400000>; + }; + + cdsp_secure_heap: secure_cdsp_region { /* Secure DSP */ + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2800000>; + }; + + va_md_mem: va_md_mem_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x1 0x00000000 0xfffffffe 0xffffffff>; + reusable; + size = <0 0x1000000>; + }; + + non_secure_display_memory: non_secure_display_region { + compatible = "shared-dma-pool"; + reusable; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + size = <0x0 0x5c00000>; + alignment = <0x0 0x400000>; + }; + + qseecom_mem: qseecom_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1400000>; + }; + + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + intc: interrupt-controller@17200000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0x17200000 0x10000>, /* GICD */ + <0x17260000 0x100000>; /* GICR * 8 */ + interrupts = ; + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <19200000>; + }; + + apps_rsc: rsc@17a00000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0x17a00000 0x10000>, + <0x17a10000 0x10000>, + <0x17a20000 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = , + , + ; + qcom,drv-count = <3>; + power-domains = <&CLUSTER_PD>; + + apps_rsc_drv2: drv@2 { + qcom,drv-id = <2>; + qcom,tcs-offset = <0xd00>; + channel@0 { + qcom,tcs-config = , + , + , + , + ; + }; + + rpmhcc: clock-controller { + compatible = "qcom,parrot-rpmh-clk"; + #clock-cells = <1>; + }; + + apps_bcm_voter: bcm_voter { + compatible = "qcom,bcm-voter"; + }; + }; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,parrot-pdc", "qcom,pdc"; + reg = <0xb220000 0x30000>, <0x174000f0 0x64>; + reg-names = "pdc-interrupt-base", "apss-shared-spi-cfg"; + qcom,pdc-ranges = <0 480 94>, <94 609 31>, + <125 63 1>, <126 716 12>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + disp_rsc: rsc@af20000 { + label = "disp_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0xaf20000 0x10000>; + reg-names = "drv-0"; + qcom,drv-count = <1>; + interrupts = ; + clocks = <&dispcc DISP_CC_MDSS_RSCC_AHB_CLK>; + + disp_rsc_drv0: drv@0 { + qcom,tcs-offset = <0x1c00>; + qcom,drv-id = <0>; + channel@0 { + qcom,tcs-config = , + , + , + , + ; + }; + + disp_bcm_voter: bcm_voter { + compatible = "qcom,bcm-voter"; + qcom,tcs-wait = ; + qcom,no-amc; + }; + }; + }; + + memtimer: timer@17420000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x17420000 0x1000>; + clock-frequency = <19200000>; + + frame@17421000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x17421000 0x1000>, + <0x17422000 0x1000>; + }; + + frame@17423000 { + frame-number = <1>; + interrupts = ; + reg = <0x17423000 0x1000>; + status = "disabled"; + }; + + frame@17425000 { + frame-number = <2>; + interrupts = ; + reg = <0x17425000 0x1000>; + status = "disabled"; + }; + + frame@17427000 { + frame-number = <3>; + interrupts = ; + reg = <0x17427000 0x1000>; + status = "disabled"; + }; + + frame@17429000 { + frame-number = <4>; + interrupts = ; + reg = <0x17429000 0x1000>; + status = "disabled"; + }; + + frame@1742b000 { + frame-number = <5>; + interrupts = ; + reg = <0x1742b000 0x1000>; + status = "disabled"; + }; + + frame@1742d000 { + frame-number = <6>; + interrupts = ; + reg = <0x1742d000 0x1000>; + status = "disabled"; + }; + }; + + cpucp: qcom,cpucp@17400000 { + #address-cells = <2>; + #size-cells = <2>; + compatible = "qcom,cpucp"; + reg = <0x17400000 0x10>, + <0x17d90000 0x2000>; + reg-names = "rx", "tx"; + #mbox-cells = <1>; + interrupts = ; + }; + + scmi: qcom,scmi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "arm,scmi"; + mboxes = <&cpucp 0>; + mbox-names = "tx"; + shmem = <&cpu_scp_lpri>; + + scmi_pmu: protocol@86 { + reg = <0x86>; + #clock-cells = <1>; + }; + + scmi_plh: protocol@81 { + reg = <0x81>; + #clock-cells = <1>; + }; + + scmi_cpufreqstat: protocol@84 { + reg = <0x84>; + #clock-cells = <1>; + }; + + scmi_shared_rail: protocol@88 { + reg = <0x88>; + #clock-cells = <1>; + }; + }; + + cpucp_log: qcom,cpucp_log@17d09c00 { + compatible = "qcom,cpucp-log"; + reg = <0x17d09c00 0x200>, <0x17d09e00 0x200>; + mboxes = <&cpucp 1>; + }; + + ipcc_mproc: qcom,ipcc@ed18000 { + compatible = "qcom,ipcc"; + reg = <0xed18000 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + tcsr: syscon@1fc0000 { + compatible = "syscon"; + reg = <0x1fc0000 0x30000>; + }; + + tcsr_mutex_block: syscon@1f40000 { + compatible = "syscon"; + reg = <0x1f40000 0x20000>; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x1000>; + #hwlock-cells = <1>; + }; + + smem: qcom,smem { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + hwlocks = <&tcsr_mutex 3>; + }; + + qcom,smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + }; + + qcom,smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sleepstate_smp2p_out: sleepstate-out { + qcom,entry-name = "sleepstate"; + #qcom,smem-state-cells = <1>; + }; + + sleepstate_smp2p_in: qcom,sleepstate-in { + qcom,entry-name = "sleepstate_see"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_rdbg2_out: qcom,smp2p-rdbg2-out { + qcom,entry-name = "rdbg"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_rdbg2_in: qcom,smp2p-rdbg2-in { + qcom,entry-name = "rdbg"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p_sleepstate { + compatible = "qcom,smp2p-sleepstate"; + qcom,smem-states = <&sleepstate_smp2p_out 0>; + interrupt-parent = <&sleepstate_smp2p_in>; + interrupts = <0 0>; + interrupt-names = "smp2p-sleepstate-in"; + }; + + qcom,smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_rdbg5_out: qcom,smp2p-rdbg5-out { + qcom,entry-name = "rdbg"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_rdbg5_in: qcom,smp2p-rdbg5-in { + qcom,entry-name = "rdbg"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-wpss { + compatible = "qcom,smp2p"; + qcom,smem = <617>, <616>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_WPSS IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <13>; + + wpss_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + wpss_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_wlan_1_in: qcom,smp2p-wlan-1-in { + qcom,entry-name = "wlan"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_wlan_1_out: qcom,smp2p-wlan-1-out { + qcom,entry-name = "wlan"; + #qcom,smem-state-cells = <1>; + }; + }; + + qcom,glinkpkt { + compatible = "qcom,glinkpkt"; + + qcom,glinkpkt-at-mdm0 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DS"; + qcom,glinkpkt-dev-name = "at_mdm0"; + }; + + qcom,glinkpkt-apr-apps2 { + qcom,glinkpkt-edge = "adsp"; + qcom,glinkpkt-ch-name = "apr_apps2"; + qcom,glinkpkt-dev-name = "apr_apps2"; + }; + + qcom,glinkpkt-data40-cntl { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA40_CNTL"; + qcom,glinkpkt-dev-name = "smdcntl8"; + }; + + qcom,glinkpkt-data1 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA1"; + qcom,glinkpkt-dev-name = "smd7"; + }; + + qcom,glinkpkt-data4 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA4"; + qcom,glinkpkt-dev-name = "smd8"; + }; + + qcom,glinkpkt-data11 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA11"; + qcom,glinkpkt-dev-name = "smd11"; + }; + }; + + qcom,glink { + compatible = "qcom,glink"; + }; + + aoss_qmp: power-controller@c300000 { + compatible = "qcom,aoss-qmp"; + reg = <0xc300000 0x400>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_AOP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + qmp_aop: qcom,qmp-aop { + compatible = "qcom,qmp-mbox"; + qcom,qmp = <&aoss_qmp>; + label = "aop"; + #mbox-cells = <1>; + }; + + qmp_tme: qcom,qmp-tme { + compatible = "qcom,qmp-mbox"; + qcom,remote-pid = <14>; + mboxes = <&ipcc_mproc IPCC_CLIENT_TME + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "tme_qmp"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "tme"; + qcom,early-boot; + priority = <0>; + mbox-desc-offset = <0x0>; + #mbox-cells = <1>; + }; + + qcom,tmecom-qmp-client { + compatible = "qcom,tmecom-qmp-client"; + mboxes = <&qmp_tme 0>; + mbox-names = "tmecom"; + label = "tmecom"; + depends-on-supply = <&qmp_tme>; + }; + + qcom,memshare { + compatible = "qcom,memshare"; + + qcom,client_1 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x0>; + qcom,client-id = <0>; + qcom,allocate-boot-time; + label = "modem"; + }; + + qcom,client_2 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x0>; + qcom,client-id = <2>; + label = "modem"; + }; + + mem_client_3_size: qcom,client_3 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x500000>; + qcom,client-id = <1>; + qcom,allocate-on-request; + label = "modem"; + }; + }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <76800000>; + clock-output-names = "xo_board"; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + clock-output-names = "sleep_clk"; + #clock-cells = <0>; + }; + + pcie_0_pipe_clk: pcie_0_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "pcie_0_pipe_clk"; + #clock-cells = <0>; + }; + + ufs_phy_rx_symbol_0_clk: ufs_phy_rx_symbol_0_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "ufs_phy_rx_symbol_0_clk"; + #clock-cells = <0>; + }; + + ufs_phy_rx_symbol_1_clk: ufs_phy_rx_symbol_1_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "ufs_phy_rx_symbol_1_clk"; + #clock-cells = <0>; + }; + + ufs_phy_tx_symbol_0_clk: ufs_phy_tx_symbol_0_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "ufs_phy_tx_symbol_0_clk"; + #clock-cells = <0>; + }; + + usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk"; + #clock-cells = <0>; + }; + }; + + gcc: clock-controller@100000 { + compatible = "qcom,parrot-gcc", "syscon"; + reg = <0x100000 0x1f4200>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mxa-supply = <&VDD_MXA_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, + <&pcie_0_pipe_clk>, <&ufs_phy_rx_symbol_0_clk>, + <&ufs_phy_rx_symbol_1_clk>, <&ufs_phy_tx_symbol_0_clk>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; + clock-names = "bi_tcxo", "sleep_clk", + "pcie_0_pipe_clk", "ufs_phy_rx_symbol_0_clk", + "ufs_phy_rx_symbol_1_clk", "ufs_phy_tx_symbol_0_clk", + "usb3_phy_wrapper_gcc_usb30_pipe_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + camcc: clock-controller@ade0000 { + compatible = "qcom,parrot-camcc", "syscon"; + reg = <0xade0000 0x20000>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mxa-supply = <&VDD_MXA_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_CAMERA_AHB_CLK>; + clock-names = "bi_tcxo", "iface"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,parrot-dispcc", "syscon"; + reg = <0xaf00000 0x20000>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mxa-supply = <&VDD_MXA_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <&gcc GCC_DISP_AHB_CLK>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "iface"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gpucc: clock-controller@3d90000 { + compatible = "qcom,parrot-gpucc", "syscon"; + reg = <0x3d90000 0xa000>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mxa-supply = <&VDD_MXA_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + clock-names = "bi_tcxo", "gpll0_out_main", + "gpll0_out_main_div", "gcc_gpu_snoc_dvm_gfx_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + videocc: clock-controller@1002000 { + compatible = "qcom,parrot-videocc", "syscon"; + reg = <0xaaf0000 0x10000>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mxa-supply = <&VDD_MXA_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <&gcc GCC_VIDEO_AHB_CLK>; + clock-names = "bi_tcxo", "sleep_clk", "iface"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + apsscc: syscon@17aa0000 { + compatible = "syscon"; + reg = <0x17aa0000 0x1c>; + }; + + mccc: syscon@190ba000 { + compatible = "syscon"; + reg = <0x190ba000 0x54>; + }; + + debugcc: debug-clock-controller@0 { + compatible = "qcom,parrot-debugcc"; + qcom,gcc = <&gcc>; + qcom,videocc = <&videocc>; + qcom,dispcc = <&dispcc>; + qcom,camcc = <&camcc>; + qcom,gpucc = <&gpucc>; + qcom,apsscc = <&apsscc>; + qcom,mccc = <&mccc>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc 0>, + <&camcc 0>, + <&dispcc 0>, + <&gpucc 0>, + <&videocc 0>; + clock-names = "xo_clk_src", + "gcc", + "camcc", + "dispcc", + "gpucc", + "videocc"; + #clock-cells = <1>; + }; + + cpufreq_hw: qcom,cpufreq-hw { + compatible = "qcom,cpufreq-epss"; + reg = <0x17d91000 0x1000>, <0x17d92000 0x1000>; + reg-names = "freq-domain0", "freq-domain1"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + qcom,lut-row-size = <4>; + qcom,skip-enable-check; + interrupts = , + ; + interrupt-names = "dcvsh0_int", "dcvsh1_int"; + #freq-domain-cells = <2>; + }; + + qcom,cpufreq-hw-debug { + qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>; + }; + + sdhc1_opp_table: sdhc1-opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-peak-kBps = <1600000 280000>; + opp-avg-kBps = <104000 0>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + opp-peak-kBps = <5600000 1500000>; + opp-avg-kBps = <400000 0>; + }; + }; + + qcom_pmu: qcom,pmu { + compatible = "qcom,pmu"; + reg = < 0x17D09300 0x300>; + reg-names = "pmu-base"; + qcom,pmu-events-tbl = + < 0x0008 0xFF 0xFF 0x02 >, + < 0x0011 0xFF 0xFF 0x00 >, + < 0x0017 0xFF 0xFF 0xFF >, + < 0x002A 0xFF 0xFF 0xFF >, + < 0x4005 0xF0 0xFF 0xFF >; + }; + + ddr_freq_table: ddr-freq-table { + ddr4 { + qcom,ddr-type = <7>; + qcom,freq-tbl = + < 547000 >, + < 768000 >, + < 1017000 >, + < 1353600 >, + < 1555000 >, + < 1708000 >, + < 2092000 >; + }; + + ddr5 { + qcom,ddr-type = <8>; + qcom,freq-tbl = + < 547000 >, + < 768000 >, + < 1555000 >, + < 1708000 >, + < 2092000 >, + < 2736000 >, + < 3196000 >; + }; + }; + + ddrqos_freq_table: ddrqos-freq-table { + qcom,freq-tbl = + < 0 >, + < 1 >; + }; + + qcom_dcvs: qcom,dcvs { + compatible = "qcom,dcvs"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + qcom_l3_dcvs_hw: l3 { + compatible = "qcom,dcvs-hw"; + qcom,dcvs-hw-type = <2>; + qcom,bus-width = <32>; + reg = <0x17d90000 0x4000>, <0x17d90100 0xa0>; + reg-names = "l3-base", "l3tbl-base"; + + l3_dcvs_sp: sp { + compatible = "qcom,dcvs-path"; + qcom,dcvs-path-type = <0>; + qcom,shared-offset = <0x0090>; + }; + }; + + qcom_ddr_dcvs_hw: ddr { + compatible = "qcom,dcvs-hw"; + qcom,dcvs-hw-type = <0>; + qcom,bus-width = <4>; + qcom,freq-tbl = <&ddr_freq_table>; + + ddr_dcvs_sp: sp { + compatible = "qcom,dcvs-path"; + qcom,dcvs-path-type = <0>; + interconnects = <&gem_noc MASTER_APPSS_PROC + &mc_virt SLAVE_EBI1>; + }; + }; + + qcom_ddrqos_dcvs_hw: ddrqos { + compatible = "qcom,dcvs-hw"; + qcom,dcvs-hw-type = <3>; + qcom,bus-width = <1>; + qcom,freq-tbl = <&ddrqos_freq_table>; + + ddrqos_dcvs_sp: sp { + compatible = "qcom,dcvs-path"; + qcom,dcvs-path-type = <0>; + interconnects = <&gem_noc MASTER_APPSS_PROC + &mc_virt SLAVE_EBI1>; + }; + }; + }; + + qcom_memlat: qcom,memlat { + compatible = "qcom,memlat"; + qcom,be-stall-ev = <0x4005>; + + ddr { + compatible = "qcom,memlat-grp"; + qcom,target-dev = <&qcom_ddr_dcvs_hw>; + qcom,sampling-path = <&ddr_dcvs_sp>; + qcom,miss-ev = <0x2A>; + + silver { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,sampling-enabled; + ddr4-tbl { + qcom,ddr-type = <7>; + qcom,cpufreq-memfreq-tbl = + < 1113600 547000 >, + < 1497600 768000 >, + < 1804800 1017000 >; + }; + + ddr5-tbl { + qcom,ddr-type = <8>; + qcom,cpufreq-memfreq-tbl = + < 1113600 547000 >, + < 1497600 768000 >, + < 1804800 1555000 >; + }; + }; + + gold { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,sampling-enabled; + ddr4-tbl { + qcom,ddr-type = <7>; + qcom,cpufreq-memfreq-tbl = + < 960000 547000 >, + < 1190400 1017000 >, + < 1497600 1353600 >, + < 1651200 1555000 >, + < 2112000 1708000 >, + < 2361600 2092000 >; + }; + + ddr5-tbl { + qcom,ddr-type = <8>; + qcom,cpufreq-memfreq-tbl = + < 960000 547000 >, + < 1651200 1555000 >, + < 1900800 1708000 >, + < 2112000 2092000 >, + < 2361600 3196000 >; + }; + }; + + silver-compute { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,sampling-enabled; + qcom,compute-mon; + ddr4-tbl { + qcom,ddr-type = <7>; + qcom,cpufreq-memfreq-tbl = + < 1497600 547000 >, + < 1804800 768000 >; + }; + + ddr5-tbl { + qcom,ddr-type = <8>; + qcom,cpufreq-memfreq-tbl = + < 1497600 547000 >, + < 1804800 768000 >; + }; + }; + + gold-compute { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,sampling-enabled; + qcom,compute-mon; + ddr4-tbl { + qcom,ddr-type = <7>; + qcom,cpufreq-memfreq-tbl = + < 1190400 547000 >, + < 1497600 768000 >, + < 1651200 1017000 >, + < 1900800 1555000 >, + < 2112000 1708000 >, + < 2361600 2092000 >; + }; + + ddr5-tbl { + qcom,ddr-type = <8>; + qcom,cpufreq-memfreq-tbl = + < 1190400 547000 >, + < 1497600 768000 >, + < 2054400 1555000 >, + < 2112000 1708000 >, + < 2361600 2092000 >; + }; + }; + + }; + + l3 { + compatible = "qcom,memlat-grp"; + qcom,target-dev = <&qcom_l3_dcvs_hw>; + qcom,sampling-path = <&l3_dcvs_sp>; + qcom,miss-ev = <0x17>; + + silver { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,cpufreq-memfreq-tbl = + < 300000 307200 >, + < 691200 556800 >, + < 806400 652800 >, + < 940800 806400 >, + < 1113600 940800 >, + < 1324800 1056000 >, + < 1497600 1190400 >, + < 1651200 1248000 >, + < 1804800 1420800 >, + < 1958400 1440000 >; + qcom,sampling-enabled; + }; + + gold { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,cpufreq-memfreq-tbl = + < 300000 307200 >, + < 960000 556800 >, + < 1190400 806400 >, + < 1344000 940800 >, + < 1651200 1190400 >, + < 1900800 1382400 >, + < 2054400 1420800 >, + < 2361600 1440000 >; + qcom,sampling-enabled; + }; + + gold-compute { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,cpufreq-memfreq-tbl = + < 2054400 307200 >, + < 2361600 1420800 >; + qcom,sampling-enabled; + qcom,compute-mon; + }; + + }; + + ddrqos { + compatible = "qcom,memlat-grp"; + qcom,target-dev = <&qcom_ddrqos_dcvs_hw>; + qcom,sampling-path = <&ddrqos_dcvs_sp>; + qcom,miss-ev = <0x2A>; + + ddrqos_gold_lat: gold { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,cpufreq-memfreq-tbl = + < 2300000 0 >, + < 3000000 1 >; + qcom,sampling-enabled; + }; + + }; + }; + + bwmon_ddr: qcom,bwmon-ddr@19091000 { + compatible = "qcom,bwmon5"; + reg = <0x19091000 0x1000>; + reg-names = "base"; + interrupts = ; + qcom,hw-timer-hz = <19200000>; + qcom,count-unit = <0x10000>; + qcom,target-dev = <&qcom_ddr_dcvs_hw>; + }; + + sdhc_1: sdhci@7C4000 { + status = "disabled"; + + compatible = "qcom,sdhci-msm-v5"; + reg = <0x007C4000 0x1000>, <0x007C5000 0x1000>, + <0x007C8000 0x8000>, <0x007D0000 0x9000>; + reg-names = "hc", "cqhci", "cqhci_ice", "cqhci_ice_hwkm"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + bus-width = <8>; + non-removable; + supports-cqe; + + no-sd; + no-sdio; + + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + + qcom,devfreq,freq-table = <50000000 200000000>; + qcom,scaling-lower-bus-speed-mode = "DDR52"; + + cap-mmc-hw-reset; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "iface", "core", "ice_core"; + + qcom,ice-clk-rates = <300000000 100000000>; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x000F642C 0x0 0x01 + 0x2C010800 0x80040868>; + + /* Add dt entry for gcc hw reset */ + resets = <&gcc GCC_EMMC_BCR>; + reset-names = "core_reset"; + + iommus = <&apps_smmu 0x60 0x0>; + dma-coherent; + qcom,iommu-dma = "fastmap"; + + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + + interconnects = <&aggre1_noc MASTER_SDCC_1 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_SDC1>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + operating-points-v2 = <&sdhc1_opp_table>; + + qos0 { + mask = <0xf0>; + vote = <44>; + }; + + qos1 { + mask = <0x0f>; + vote = <44>; + }; + }; + + sdhc2_opp_table: sdhc2-opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-peak-kBps = <1600000 280000>; + opp-avg-kBps = <50000 0>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + opp-peak-kBps = <5600000 1500000>; + opp-avg-kBps = <104000 0>; + }; + }; + + sdhc_2: sdhci@8804000 { + status = "disabled"; + + compatible = "qcom,sdhci-msm-v5"; + reg = <0x08804000 0x1000>; + reg-names = "hc"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + bus-width = <4>; + no-sdio; + no-mmc; + qcom,restore-after-cx-collapse; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>; + clock-names = "iface", "core"; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x0007642C 0x0 0x10 + 0x2C010800 0x80040868>; + + iommus = <&apps_smmu 0x540 0x0>; + dma-coherent; + qcom,iommu-dma = "fastmap"; + + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + + interconnects = <&aggre2_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_SDCC_2>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + operating-points-v2 = <&sdhc2_opp_table>; + + qos0 { + mask = <0xf0>; + vote = <44>; + }; + + qos1 { + mask = <0x0f>; + vote = <44>; + }; + }; + + qcom,rmtfs_sharedmem@0 { + compatible = "qcom,sharedmem-uio"; + reg = <0x0 0x280000>; + reg-names = "rmtfs"; + qcom,client-id = <0x00000001>; + }; + + clk_virt: interconnect@0 { + compatible = "qcom,parrot-clk_virt"; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <1>; + }; + + mc_virt: interconnect@1 { + compatible = "qcom,parrot-mc_virt"; + qcom,bcm-voter-names = "hlos", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; + #interconnect-cells = <1>; + }; + + cnoc2: interconnect@1500000 { + reg = <0x1500000 0x1000>; + compatible = "qcom,parrot-cnoc2"; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <1>; + }; + + cnoc3: interconnect@1502000 { + reg = <0x1502000 0x1000>; + compatible = "qcom,parrot-cnoc3"; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <1>; + }; + + system_noc: interconnect@1680000 { + reg = <0x1680000 0x1E200>; + compatible = "qcom,parrot-system_noc"; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <1>; + }; + + pcie_noc: interconnect@16c0000 { + reg = <0x16C0000 0xE280>; + compatible = "qcom,parrot-pcie_anoc"; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <1>; + clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; + }; + + aggre1_noc: interconnect@16e0000 { + reg = <0x16e0000 0x1C080>; + compatible = "qcom,parrot-aggre1_noc"; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <1>; + clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; + }; + + aggre2_noc: interconnect@1700000 { + reg = <0x1700000 0x31080>; + compatible = "qcom,parrot-aggre2_noc"; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <1>; + clocks = <&rpmhcc RPMH_IPA_CLK>, + <&gcc GCC_SDCC2_AHB_CLK>; + }; + + mmss_noc: interconnect@1740000 { + reg = <0x1740000 0x1f080>; + compatible = "qcom,parrot-mmss_noc"; + qcom,bcm-voter-names = "hlos", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; + #interconnect-cells = <1>; + }; + + gem_noc: interconnect@19100000 { + reg = <0x19100000 0xBB800>; + compatible = "qcom,parrot-gem_noc"; + qcom,bcm-voter-names = "hlos", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; + #interconnect-cells = <1>; + }; + + nsp_noc: interconnect@320C0000 { + reg = <0x320C0000 0x10000>; + compatible = "qcom,parrot-nsp_noc"; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <1>; + }; + + lpass_ag_noc: interconnect@3c40000 { + reg = <0x3c40000 0x17200>; + compatible = "qcom,parrot-lpass_ag_noc"; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <1>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: cpu-pd0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD1: cpu-pd1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD2: cpu-pd2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD3: cpu-pd3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD4: cpu-pd4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD5: cpu-pd5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD6: cpu-pd6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD7: cpu-pd7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CLUSTER_PD: cluster-pd { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_OFF &CX_RET>; + }; + }; + + slimbam: bamdma@3304000 { + compatible = "qcom,bam-v1.7.0"; + qcom,controlled-remotely; + reg = <0x3304000 0x20000>, <0x326b000 0x1000>; + reg-names = "bam", "bam_remote_mem"; + num-channels = <31>; + interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + qcom,ee = <1>; + qcom,num-ees = <2>; + }; + + slim_msm: slim@3340000 { + compatible = "qcom,slim-ngd-v1.5.0"; + reg = <0x3340000 0x2C000>, <0x326a000 0x1000>; + reg-names = "ctrl", "slimbus_remote_mem"; + interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>; + qcom,apps-ch-pipes = <0x0>; + qcom,ea-pc = <0x440>; + dmas = <&slimbam 3>, <&slimbam 4>; + dma-names = "rx", "tx"; + #address-cells = <1>; + #size-cells = <0>; + status = "ok"; + }; + + cluster-device { + compatible = "qcom,lpm-cluster-dev"; + power-domains = <&CLUSTER_PD>; + }; + + cpuss-sleep-stats@17800054 { + compatible = "qcom,cpuss-sleep-stats"; + reg = <0x17800054 0x4>, <0x17810054 0x4>, <0x17820054 0x4>, + <0x17830054 0x4>, <0x17840054 0x4>, <0x17850054 0x4>, + <0x17860054 0x4>, <0x17870054 0x4>, <0x17880098 0x4>, + <0x178C0000 0x10000>; + reg-names = "seq_lpm_cntr_cfg_cpu0", "seq_lpm_cntr_cfg_cpu1", + "seq_lpm_cntr_cfg_cpu2", "seq_lpm_cntr_cfg_cpu3", + "seq_lpm_cntr_cfg_cpu4", "seq_lpm_cntr_cfg_cpu5", + "seq_lpm_cntr_cfg_cpu6", "seq_lpm_cntr_cfg_cpu7", + "l3_seq_lpm_cntr_cfg", "apss_seq_mem_base"; + num-cpus = <8>; + }; + + sram@c3f0000 { + compatible = "qcom,rpmh-stats-v3"; + reg = <0xc3f0000 0x400>; + ss-name = "modem", "adsp", "adsp_island", + "cdsp", "apss", "wpss"; + qcom,qmp = <&aoss_qmp>; + }; + + sys-pm-vx@c320000 { + compatible = "qcom,sys-pm-violators", "qcom,sys-pm-parrot"; + reg = <0xc320000 0x0400>; + qcom,qmp = <&aoss_qmp>; + }; + + qcom_tzlog: tz-log@146AA720 { + compatible = "qcom,tz-log"; + reg = <0x146AA720 0x3000>; + qcom,hyplog-enabled; + hyplog-address-offset = <0x410>; + hyplog-size-offset = <0x414>; + tmecrashdump-address-offset = <0x808a0000>; + status = "ok"; + }; + + qcom_qseecom: qseecom@c1700000 { + memory-region = <&qseecom_mem>; + qseecom_mem = <&qseecom_mem>; + qseecom_ta_mem = <&qseecom_ta_mem>; + qcom,hlos-num-ce-hw-instances = <1>; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,no-clock-support; + qcom,appsbl-qseecom-support; + qcom,commonlib64-loaded-by-uefi; + qcom,qsee-reentrancy-support = <2>; + qcom,no-user-contig-mem-support; + }; + + qcom_cedev: qcedev@1de0000 { + compatible = "qcom,qcedev"; + reg = <0x1de0000 0x20000>, + <0x1dc4000 0x24000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = ; + qcom,bam-pipe-pair = <2>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,ce-hw-shared; + qcom,bam-ee = <0>; + qcom,smmu-s1-enable; + qcom,no-clock-support; + interconnect-names = "data_path"; + interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; + iommus = <&apps_smmu 0x0484 0x0011>; + qcom,iommu-dma = "atomic"; + dma-coherent; + + qcom_cedev_ns_cb { + compatible = "qcom,qcedev,context-bank"; + label = "ns_context"; + iommus = <&apps_smmu 0x488 0x0>, + <&apps_smmu 0x49A 0x0>, + <&apps_smmu 0x49F 0x0>, + <&apps_smmu 0x498 0x5>; + dma-coherent; + }; + + qcom_cedev_s_cb { + compatible = "qcom,qcedev,context-bank"; + label = "secure_context"; + iommus = <&apps_smmu 0x492 0x0>, + <&apps_smmu 0x497 0x0>, + <&apps_smmu 0x49B 0x0>, + <&apps_smmu 0x49E 0x0>; + qcom,iommu-vmid = <0x9>; + qcom,secure-context-bank; + }; + }; + + ufsphy_mem: ufsphy_mem@1d87000 { + reg = <0x1d87000 0xe10>; + reg-names = "phy_mem"; + #phy-cells = <0>; + + lanes-per-direction = <2>; + clock-names = "ref_clk_src", + "ref_aux_clk", "qref_clk", + "rx_sym0_mux_clk", "rx_sym1_mux_clk", "tx_sym0_mux_clk", + "rx_sym0_phy_clk", "rx_sym1_phy_clk", "tx_sym0_phy_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_0_CLKREF_EN>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC>, + <&ufs_phy_rx_symbol_0_clk>, + <&ufs_phy_rx_symbol_1_clk>, + <&ufs_phy_tx_symbol_0_clk>; + resets = <&ufshc_mem 0>; + status = "disabled"; + }; + + ufshc_mem: ufshc@1d84000 { + compatible = "qcom,ufshc"; + reg = <0x1d84000 0x3000>, + <0x1d88000 0x8000>, + <0x1d90000 0x9000>; + reg-names = "ufs_mem", "ufs_ice", "ufs_ice_hwkm"; + interrupts = ; + phys = <&ufsphy_mem>; + phy-names = "ufsphy"; + #reset-cells = <1>; + + lanes-per-direction = <2>; + dev-ref-clk-freq = <0>; /* 19.2 MHz */ + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + freq-table-hz = + <75000000 300000000>, + <0 0>, + <0 0>, + <75000000 300000000>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + + interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_UFS_MEM_CFG>; + interconnect-names = "ufs-ddr", "cpu-ufs"; + + qcom,ufs-bus-bw,name = "ufshc_mem"; + qcom,ufs-bus-bw,num-cases = <26>; + qcom,ufs-bus-bw,num-paths = <2>; + qcom,ufs-bus-bw,vectors-KBps = + /* + * During HS G3 UFS runs at nominal voltage corner, vote + * higher bandwidth to push other buses in the data path + * to run at nominal to achieve max throughput. + * 4GBps pushes BIMC to run at nominal. + * 200MBps pushes CNOC to run at nominal. + * Vote for half of this bandwidth for HS G3 1-lane. + * For max bandwidth, vote high enough to push the buses + * to run in turbo voltage corner. + */ + <0 0>, <0 0>, /* No vote */ + <922 0>, <1000 0>, /* PWM G1 */ + <1844 0>, <1000 0>, /* PWM G2 */ + <3688 0>, <1000 0>, /* PWM G3 */ + <7376 0>, <1000 0>, /* PWM G4 */ + <1844 0>, <1000 0>, /* PWM G1 L2 */ + <3688 0>, <1000 0>, /* PWM G2 L2 */ + <7376 0>, <1000 0>, /* PWM G3 L2 */ + <14752 0>, <1000 0>, /* PWM G4 L2 */ + <127796 0>, <1000 0>, /* HS G1 RA */ + <255591 0>, <1000 0>, /* HS G2 RA */ + <1492582 0>, <102400 0>, /* HS G3 RA */ + <2915200 0>, <204800 0>, /* HS G4 RA */ + <255591 0>, <1000 0>, /* HS G1 RA L2 */ + <511181 0>, <1000 0>, /* HS G2 RA L2 */ + <1492582 0>, <204800 0>, /* HS G3 RA L2 */ + <2915200 0>, <409600 0>, /* HS G4 RA L2 */ + <149422 0>, <1000 0>, /* HS G1 RB */ + <298189 0>, <1000 0>, /* HS G2 RB */ + <1492582 0>, <102400 0>, /* HS G3 RB */ + <2915200 0>, <204800 0>, /* HS G4 RB */ + <298189 0>, <1000 0>, /* HS G1 RB L2 */ + <596378 0>, <1000 0>, /* HS G2 RB L2 */ + /* As UFS working in HS G3 RB L2 mode, aggregated + * bandwidth (AB) should take care of providing + * optimum throughput requested. However, as tested, + * in order to scale up CNOC clock, instantaneous + * bindwidth (IB) needs to be given a proper value too. + */ + <1492582 0>, <204800 409600>, /* HS G3 RB L2 KBPs */ + <2915200 0>, <409600 409600>, /* HS G4 RB L2 */ + <7643136 0>, <307200 0>; /* Max. bandwidth */ + + qcom,bus-vector-names = "MIN", + "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", + "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", + "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1", + "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2", + "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1", + "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2", + "MAX"; + + reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + iommus = <&apps_smmu 0x20 0x0>; + qcom,iommu-dma = "fastmap"; + dma-coherent; + + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + + status = "disabled"; + + qos0 { + mask = <0xf0>; + vote = <44>; + perf; + }; + + qos1 { + mask = <0x0f>; + vote = <44>; + }; + }; + + eud: qcom,msm-eud@88e0000 { + compatible = "qcom,msm-eud"; + interrupt-names = "eud_irq"; + interrupt-parent = <&pdc>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x088e0000 0x2000>, + <0x088e2000 0x1000>; + reg-names = "eud_base", "eud_mode_mgr2"; + clocks = <&gcc GCC_EUSB3_0_CLKREF_EN>; + clock-names = "eud_clkref_clk"; + qcom,secure-eud-en; + status = "ok"; + }; + + qcom,secure-buffer { + compatible = "qcom,secure-buffer"; + qcom,vmid-cp-camera-preview-ro; + }; + + qcom,mem-buf { + compatible = "qcom,mem-buf"; + qcom,mem-buf-capabilities = "supplier"; + qcom,vmid = <3>; + }; + + qcom,mem-buf-msgq { + compatible = "qcom,mem-buf-msgq"; + }; + + trust_ui_vm: qcom,trust_ui_vm@e55fc000 { + reg = <0xe55fc000 0x104000>; + vm_name = "trustedvm"; + shared-buffers = <&trust_ui_vm_vblk0_ring &trust_ui_vm_swiotlb>; + }; + + qcom,virtio_backend@0 { + compatible = "qcom,virtio_backend"; + qcom,vm = <&trust_ui_vm>; + qcom,label = <0x11>; + }; + + qrtr-gunyah { + compatible = "qcom,qrtr-gunyah"; + qcom,master; + gunyah-label = <3>; + peer-name = <2>; + shared-buffer = <&trust_ui_vm_qrtr>; + }; + + qcom,mpm2-sleep-counter@c221000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0xc221000 0x1000>; + clock-frequency = <32768>; + }; + + qcom,msm-imem@146aa000 { + compatible = "qcom,msm-imem"; + ranges = <0x0 0x146aa000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 0x8>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 0x4>; + }; + + dload_type@1c { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x1c 0x4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 0x20>; + }; + + kaslr_offset@6d0 { + compatible = "qcom,msm-imem-kaslr_offset"; + reg = <0x6d0 0xc>; + }; + + pil@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x94c 0xc8>; + }; + + pil@6dc { + compatible = "qcom,msm-imem-pil-disable-timeout"; + reg = <0x6dc 0x4>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 0xc8>; + }; + }; + + cpu_pmu: cpu-pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + msm_gpu: qcom,kgsl-3d0@3d00000 { }; + + adsp_pas: remoteproc-adsp@03000000 { + compatible = "qcom,parrot-adsp-pas"; + reg = <0x03000000 0x10000>; + status = "ok"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + cx-supply = <&VDD_LPI_CX_LEVEL>; + cx-uV-uA = ; + mx-supply = <&VDD_LPI_MX_LEVEL>; + mx-uV-uA = ; + reg-names = "cx", "mx"; + + interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; + interconnect-names = "crypto_ddr"; + + qcom,qmp = <&aoss_qmp>; + memory-region = <&adsp_mem>; + + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 0>, + <&adsp_smp2p_in 2 0>, + <&adsp_smp2p_in 1 0>, + <&adsp_smp2p_in 3 0>, + <&adsp_smp2p_in 7 0>; + + interrupt-names = "wdog", + "fatal", + "handover", + "ready", + "stop-ack", + "shutdown-ack"; + + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + glink_edge: glink-edge { + qcom,remote-pid = <2>; + transport = "smem"; + mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "adsp_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "adsp"; + qcom,glink-label = "lpass"; + + qcom,adsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + + qcom,no-wake-svc = <0x190>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + }; + }; + + cdsp_pas: remoteproc-cdsp@32300000 { + compatible = "qcom,parrot-cdsp-pas"; + reg = <0x32300000 0x10000>; + status = "ok"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + cx-supply = <&VDD_CX_LEVEL>; + cx-uV-uA = ; + mx-supply = <&VDD_MXA_LEVEL>; + mx-uV-uA = ; + reg-names = "cx","mx"; + + interconnects = <&nsp_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; + interconnect-names = "rproc_ddr", "crypto_ddr"; + + qcom,qmp = <&aoss_qmp>; + memory-region = <&cdsp_mem>; + + /* Inputs from turing */ + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 0 0>, + <&cdsp_smp2p_in 2 0>, + <&cdsp_smp2p_in 1 0>, + <&cdsp_smp2p_in 3 0>, + <&cdsp_smp2p_in 7 0>; + + interrupt-names = "wdog", + "fatal", + "handover", + "ready", + "stop-ack", + "shutdown-ack"; + + /* Outputs to turing */ + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + qcom,remote-pid = <5>; + transport = "smem"; + mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "cdsp_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "cdsp"; + qcom,glink-label = "cdsp"; + + qcom,cdsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,msm_cdsprm_rpmsg { + compatible = "qcom,msm-cdsprm-rpmsg"; + qcom,glink-channels = "cdsprmglink-apps-dsp"; + qcom,intents = <0x20 12>; + + msm_cdsp_rm: qcom,msm_cdsp_rm { + compatible = "qcom,msm-cdsp-rm"; + qcom,qos-cores = <0 1 2 3>; + qcom,qos-latency-us = <70>; + qcom,qos-maxhold-ms = <20>; + }; + }; + }; + }; + + modem_pas: remoteproc-mss@04080000 { + compatible = "qcom,parrot-modem-pas"; + reg = <0x4080000 0x10000>; + status = "ok"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + cx-supply = <&VDD_CX_LEVEL>; + cx-uV-uA = ; + mx-supply = <&VDD_MODEM_LEVEL>; + mx-uV-uA = ; + reg-names = "cx", "mx"; + + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; + interconnect-names = "rproc_ddr","crypto_ddr"; + + qcom,qmp = <&aoss_qmp>; + memory-region = <&mpss_mem &system_cma>; + + /* Inputs from mss */ + interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 0>, + <&modem_smp2p_in 2 0>, + <&modem_smp2p_in 1 0>, + <&modem_smp2p_in 3 0>, + <&modem_smp2p_in 7 0>; + + interrupt-names = "wdog", + "fatal", + "handover", + "ready", + "stop-ack", + "shutdown-ack"; + + /* Outputs to mss */ + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + qcom,remote-pid = <1>; + transport = "smem"; + mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "mpss_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "modem"; + qcom,glink-label = "mpss"; + + qcom,modem_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,low-latency; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,modem_ds { + qcom,glink-channels = "DS"; + qcom,intents = <0x4000 0x2>; + }; + }; + }; + + wpss_pas: remoteproc-wpss@8a00000 { + compatible = "qcom,parrot-wpss-pas"; + reg = <0x08a00000 0x10000>; + status = "ok"; + + memory-region = <&wpss_mem>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + cx-supply = <&VDD_CX_LEVEL>; + cx-uV-uA = ; + mx-supply = <&VDD_MXA_LEVEL>; + mx-uV-uA = ; + reg-names = "cx","mx"; + + qcom,qmp = <&aoss_qmp>; + + /* Inputs from wpss */ + interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, + <&wpss_smp2p_in 0 0>, + <&wpss_smp2p_in 2 0>, + <&wpss_smp2p_in 1 0>, + <&wpss_smp2p_in 3 0>, + <&wpss_smp2p_in 7 0>; + + interrupt-names = "wdog", + "fatal", + "handover", + "ready", + "stop-ack", + "shutdown-ack"; + + /* Outputs to wpss */ + qcom,smem-states = <&wpss_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + qcom,remote-pid = <13>; + transport = "smem"; + mboxes = <&ipcc_mproc IPCC_CLIENT_WPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "wpss_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "wpss"; + qcom,glink-label = "wpss"; + + qcom,wpss_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + }; + }; + + spmi_bus: spmi0_bus: qcom,spmi@c42d000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0xc42d000 0x4000>, + <0xc400000 0x3000>, + <0xc500000 0x400000>, + <0xc440000 0x80000>, + <0xc4c0000 0x10000>; + reg-names = "cnfg", "core", "chnls", "obsrvr", "intr"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + cell-index = <0>; + qcom,channel = <0>; + qcom,ee = <0>; + qcom,bus-id = <0>; + }; + + spmi1_bus: qcom,spmi@c432000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0xc432000 0x4000>, + <0xc400000 0x3000>, + <0xc500000 0x400000>, + <0xc440000 0x80000>, + <0xc4d0000 0x10000>; + reg-names = "cnfg", "core", "chnls", "obsrvr", "intr"; + interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + cell-index = <0>; + qcom,channel = <0>; + qcom,ee = <0>; + qcom,bus-id = <1>; + depends-on-supply = <&spmi0_bus>; + }; + + spmi0_debug_bus: qcom,spmi-debug@10b14000 { + compatible = "qcom,spmi-pmic-arb-debug"; + reg = <0x10b14000 0x60>, <0x221c8784 0x4>; + reg-names = "core", "fuse"; + clocks = <&aoss_qmp>; + clock-names = "core_clk"; + qcom,fuse-enable-bit = <18>; + #address-cells = <2>; + #size-cells = <0>; + depends-on-supply = <&spmi1_bus>; + + qcom,pmk8350-debug@0 { + compatible = "qcom,spmi-pmic"; + reg = <0 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pm6450-debug@1 { + compatible = "qcom,spmi-pmic"; + reg = <1 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pm6150l-debug@4 { + compatible = "qcom,spmi-pmic"; + reg = <4 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pm6150l-debug@5 { + compatible = "qcom,spmi-pmic"; + reg = <5 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + pmr735a_debug: qcom,pmr735a-debug@6 { + compatible = "qcom,spmi-pmic"; + reg = <6 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + }; + + qcom,pmic_glink { + compatible = "qcom,qti-pmic-glink"; + qcom,pmic-glink-channel = "PMIC_RTR_ADSP_APPS"; + qcom,subsys-name = "lpass"; + qcom,protection-domain = "tms/servreg", "msm/adsp/charger_pd"; + depends-on-supply = <&ipcc_mproc>; + status = "disabled"; + + battery_charger: qcom,battery_charger { + compatible = "qcom,battery-charger"; + status = "disabled"; + }; + + ucsi: qcom,ucsi { + compatible = "qcom,ucsi-glink"; + status = "disabled"; + }; + + altmode: qcom,altmode { + compatible = "qcom,altmode-glink"; + #altmode-cells = <1>; + status = "disabled"; + }; + }; + + vendor_hooks: qcom,cpu-vendor-hooks { + compatible = "qcom,cpu-vendor-hooks"; + }; + + + qfprom: qfprom@221c8000 { + compatible = "qcom,qfprom"; + reg = <0x221c8000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + read-only; + ranges; + + adsp_variant: adsp_variant@114 { + reg = <0x117 0x1>; + bits = <2 6>; + }; + + feat_conf12: feat_conf12@0130 { + reg = <0x0130 0x4>; + }; + + feat_conf13: feat_conf13@0134 { + reg = <0x0134 0x4>; + }; + + gpu_speed_bin: gpu_speed_bin@119 { + reg = <0x119 0x2>; + bits = <5 8>; + }; + + gpu_gaming_bin: gpu_gaming_bin@130 { + reg = <0x130 0x1>; + bits = <6 1>; + }; + + boot_config: boot_config@600 { + reg = <0x600 0x1>; + }; + }; + + qfprom_sys: qfprom@0 { + nvmem-cells = <&adsp_variant>, + <&feat_conf12>, + <&feat_conf13>, + <&boot_config>; + nvmem-cell-names = "adsp_variant", + "feat_conf12", + "feat_conf13", + "boot_config"; + }; + + qcom,msm-cdsp-loader { + qcom,proc-img-to-load = "cdsp"; + qcom,rproc-handle = <&cdsp_pas>; + }; + + qcom,msm-adsprpc-mem { + compatible = "qcom,msm-adsprpc-mem-region"; + memory-region = <&adsp_mem_heap>; + restrict-access; + }; + + qcom,sps { + compatible = "qcom,msm-sps-4k"; + qcom,pipe-attr-ee; + }; + + msm_fastrpc: qcom,msm_fastrpc { + compatible = "qcom,msm-fastrpc-compute"; + qcom,adsp-remoteheap-vmid = <22 37>; + qcom,fastrpc-adsp-audio-pdr; + qcom,fastrpc-adsp-sensors-pdr; + qcom,rpc-latency-us = <235>; + qcom,fastrpc-gids = <2908>; + qcom,qos-cores = <0 1 2 3>; + + qcom,msm_fastrpc_compute_cb1 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1401 0x0400>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb2 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1402 0x0400>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb3 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1403 0x0400>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb4 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1404 0x0400>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb5 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1405 0x0400>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb6 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1406 0x0400>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb7 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1407 0x0400>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb8 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1408 0x0400>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb9 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + qcom,secure-context-bank; + iommus = <&apps_smmu 0x1409 0x0400>; + qcom,iommu-dma-addr-pool = <0x60000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */ + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb10 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1803 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb11 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1804 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb12 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1805 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + shared-cb = <5>; + }; + + qcom,msm_fastrpc_compute_cb13 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x140B 0x0400>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb14 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x140C 0x0400>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb15 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x140D 0x0400>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb16 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x140E 0x0400>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + }; + }; + + thermal_zones: thermal-zones { + }; + + qcom_ramoops { + compatible = "qcom,ramoops"; + memory-region = <&ramoops_mem>; + pmsg-size = <0x200000>; + mem-type = <2>; + }; + + logbuf: qcom,logbuf-vendor-hooks { + compatible = "qcom,logbuf-vendor-hooks"; + }; + + mini_dump_node { + compatible = "qcom,minidump"; + status = "ok"; + }; + + va_mini_dump { + compatible = "qcom,va-minidump"; + memory-region = <&va_md_mem>; + status = "ok"; + }; + +}; + +#include "diwali-gdsc.dtsi" +#include "ipcc-test-parrot.dtsi" + +&gcc_pcie_0_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&gcc_ufs_phy_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&gcc_usb30_prim_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&hlos1_vote_turing_mmu_tbu1_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&hlos1_vote_turing_mmu_tbu0_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&cam_cc_camss_top_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + clock-names = "ahb_clk"; + status = "ok"; +}; + +&disp_cc_mdss_core_gdsc { + clocks = <&gcc GCC_DISP_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&disp_cc_mdss_core_int2_gdsc { + clocks = <&gcc GCC_DISP_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&gpu_cc_cx_gdsc { + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&gpu_cc_gx_gdsc { + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_GFX_LEVEL>; + qcom,skip-disable-before-sw-enable; + status = "ok"; +}; + +&video_cc_mvs0_gdsc { + reg = <0xaaf6004 0x4>; + clocks = <&gcc GCC_VIDEO_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&video_cc_mvsc_gdsc { + clocks = <&gcc GCC_VIDEO_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +#include "parrot-regulators.dtsi" +#include "parrot-pinctrl.dtsi" +#include "parrot-qupv3.dtsi" +#include "parrot-dma-heaps.dtsi" +#include "msm-arm-smmu-parrot.dtsi" + +&qupv3_se3_2uart { + status = "ok"; +}; + +&qupv3_se11_4uart { + status = "ok"; +}; + +&qupv3_se2_i2c { + status = "ok"; + + fsa4480: fsa4480@42 { + reg = <0x42>; + }; +}; + +#include "parrot-thermal.dtsi" +#include "msm-rdbg.dtsi" + diff --git a/qcom/parrotp-atp.dts b/qcom/parrotp-atp.dts new file mode 100644 index 00000000..d2f73134 --- /dev/null +++ b/qcom/parrotp-atp.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrotp.dtsi" +#include "parrot-wcn3990.dtsi" +#include "parrotp-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. ParrotP ATP"; + compatible = "qcom,parrotp-atp", "qcom,parrotp", "qcom,atp"; + qcom,board-id = <33 0>; +}; diff --git a/qcom/parrotp-atp.dtsi b/qcom/parrotp-atp.dtsi new file mode 100644 index 00000000..bc0e5053 --- /dev/null +++ b/qcom/parrotp-atp.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-atp.dtsi" diff --git a/qcom/parrotp-idp-nopmi.dts b/qcom/parrotp-idp-nopmi.dts new file mode 100644 index 00000000..e69aac84 --- /dev/null +++ b/qcom/parrotp-idp-nopmi.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrotp.dtsi" +#include "parrot-wcn6750.dtsi" +#include "parrotp-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. ParrotP IDP"; + compatible = "qcom,parrotp-idp", "qcom,parrotp", "qcom,idp"; + qcom,board-id = <34 0>; + qcom,pmic-id-size = <9>; + qcom,pmic-id = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; +}; diff --git a/qcom/parrotp-idp-pm8350b.dts b/qcom/parrotp-idp-pm8350b.dts new file mode 100644 index 00000000..5a7d9de4 --- /dev/null +++ b/qcom/parrotp-idp-pm8350b.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrotp.dtsi" +#include "parrot-wcn6750.dtsi" +#include "parrotp-idp.dtsi" +#include "parrot-idp-pm8350b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. ParrotP IDP"; + compatible = "qcom,parrotp-idp", "qcom,parrotp", "qcom,idp"; + qcom,board-id = <34 0>; +}; diff --git a/qcom/parrotp-idp-wcn3990-amoled-rcm.dts b/qcom/parrotp-idp-wcn3990-amoled-rcm.dts new file mode 100644 index 00000000..63bd6c10 --- /dev/null +++ b/qcom/parrotp-idp-wcn3990-amoled-rcm.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrotp.dtsi" +#include "parrot-wcn3990.dtsi" +#include "parrotp-idp-wcn3990-amoled-rcm.dtsi" +#include "parrot-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. ParrotP WCN3990 IDP + AMOLED + RCM"; + compatible = "qcom,parrotp-idp", "qcom,parrotp", "qcom,idp"; + qcom,board-id = <34 3>; +}; diff --git a/qcom/parrotp-idp-wcn3990-amoled-rcm.dtsi b/qcom/parrotp-idp-wcn3990-amoled-rcm.dtsi new file mode 100644 index 00000000..c95e1e28 --- /dev/null +++ b/qcom/parrotp-idp-wcn3990-amoled-rcm.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-idp-wcn3990-amoled-rcm.dtsi" diff --git a/qcom/parrotp-idp-wcn3990.dts b/qcom/parrotp-idp-wcn3990.dts new file mode 100644 index 00000000..e74fce3d --- /dev/null +++ b/qcom/parrotp-idp-wcn3990.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrotp.dtsi" +#include "parrot-wcn3990.dtsi" +#include "parrotp-idp-wcn3990.dtsi" +#include "parrot-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. ParrotP IDP + WCN3990"; + compatible = "qcom,parrotp-idp", "qcom,parrotp", "qcom,idp"; + qcom,board-id = <34 1>; +}; diff --git a/qcom/parrotp-idp-wcn3990.dtsi b/qcom/parrotp-idp-wcn3990.dtsi new file mode 100644 index 00000000..82fd037d --- /dev/null +++ b/qcom/parrotp-idp-wcn3990.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-idp-wcn3990.dtsi" diff --git a/qcom/parrotp-idp-wcn6750-amoled-rcm.dts b/qcom/parrotp-idp-wcn6750-amoled-rcm.dts new file mode 100644 index 00000000..127c964b --- /dev/null +++ b/qcom/parrotp-idp-wcn6750-amoled-rcm.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrotp.dtsi" +#include "parrot-wcn6750.dtsi" +#include "parrotp-idp-wcn6750-amoled-rcm.dtsi" +#include "parrot-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. ParrotP WCN6750 IDP + AMOLED + RCM"; + compatible = "qcom,parrotp-idp", "qcom,parrotp", "qcom,idp"; + qcom,board-id = <34 2>; +}; diff --git a/qcom/parrotp-idp-wcn6750-amoled-rcm.dtsi b/qcom/parrotp-idp-wcn6750-amoled-rcm.dtsi new file mode 100644 index 00000000..24c7f1e0 --- /dev/null +++ b/qcom/parrotp-idp-wcn6750-amoled-rcm.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-idp-wcn6750-amoled-rcm.dtsi" diff --git a/qcom/parrotp-idp-wcn6750-amoled.dts b/qcom/parrotp-idp-wcn6750-amoled.dts new file mode 100644 index 00000000..2a9b1af7 --- /dev/null +++ b/qcom/parrotp-idp-wcn6750-amoled.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrotp.dtsi" +#include "parrot-wcn6750.dtsi" +#include "parrotp-idp-wcn6750-amoled.dtsi" +#include "parrot-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. ParrotP WCN6750 IDP + AMOLED"; + compatible = "qcom,parrotp-idp", "qcom,parrotp", "qcom,idp"; + qcom,board-id = <34 4>; +}; diff --git a/qcom/parrotp-idp-wcn6750-amoled.dtsi b/qcom/parrotp-idp-wcn6750-amoled.dtsi new file mode 100644 index 00000000..d116a8a8 --- /dev/null +++ b/qcom/parrotp-idp-wcn6750-amoled.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-idp-wcn6750-amoled.dtsi" diff --git a/qcom/parrotp-idp.dts b/qcom/parrotp-idp.dts new file mode 100644 index 00000000..38885a95 --- /dev/null +++ b/qcom/parrotp-idp.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrotp.dtsi" +#include "parrot-wcn6750.dtsi" +#include "parrotp-idp.dtsi" +#include "parrot-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. ParrotP IDP"; + compatible = "qcom,parrotp-idp", "qcom,parrotp", "qcom,idp"; + qcom,board-id = <34 0>; +}; diff --git a/qcom/parrotp-idp.dtsi b/qcom/parrotp-idp.dtsi new file mode 100644 index 00000000..b82bb81e --- /dev/null +++ b/qcom/parrotp-idp.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-idp.dtsi" diff --git a/qcom/parrotp-qrd-nopmi.dts b/qcom/parrotp-qrd-nopmi.dts new file mode 100644 index 00000000..9315c1d0 --- /dev/null +++ b/qcom/parrotp-qrd-nopmi.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrotp.dtsi" +#include "parrot-wcn3990.dtsi" +#include "parrotp-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. ParrotP QRD"; + compatible = "qcom,parrotp-qrd", "qcom,parrotp", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; + qcom,pmic-id-size = <9>; + qcom,pmic-id = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; +}; diff --git a/qcom/parrotp-qrd-pm8350b.dts b/qcom/parrotp-qrd-pm8350b.dts new file mode 100644 index 00000000..87a37829 --- /dev/null +++ b/qcom/parrotp-qrd-pm8350b.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrotp.dtsi" +#include "parrot-wcn3990.dtsi" +#include "parrotp-qrd.dtsi" +#include "parrot-qrd-pm8350b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. ParrotP QRD"; + compatible = "qcom,parrotp-qrd", "qcom,parrotp", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; +}; diff --git a/qcom/parrotp-qrd-wcn6750.dts b/qcom/parrotp-qrd-wcn6750.dts new file mode 100644 index 00000000..13d46a5b --- /dev/null +++ b/qcom/parrotp-qrd-wcn6750.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrotp.dtsi" +#include "parrot-wcn6750.dtsi" +#include "parrotp-qrd-wcn6750.dtsi" +#include "parrot-qrd-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. ParrotP WCN6750 QRD"; + compatible = "qcom,parrotp-qrd", "qcom,parrotp", "qcom,qrd"; + qcom,board-id = <0x1000B 1>; +}; diff --git a/qcom/parrotp-qrd-wcn6750.dtsi b/qcom/parrotp-qrd-wcn6750.dtsi new file mode 100644 index 00000000..c4b4d42b --- /dev/null +++ b/qcom/parrotp-qrd-wcn6750.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-qrd-wcn6750.dtsi" diff --git a/qcom/parrotp-qrd.dts b/qcom/parrotp-qrd.dts new file mode 100644 index 00000000..482dde29 --- /dev/null +++ b/qcom/parrotp-qrd.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrotp.dtsi" +#include "parrot-wcn3990.dtsi" +#include "parrotp-qrd.dtsi" +#include "parrot-qrd-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. ParrotP QRD"; + compatible = "qcom,parrotp-qrd", "qcom,parrotp", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; +}; diff --git a/qcom/parrotp-qrd.dtsi b/qcom/parrotp-qrd.dtsi new file mode 100644 index 00000000..690b6ecd --- /dev/null +++ b/qcom/parrotp-qrd.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-qrd.dtsi" diff --git a/qcom/parrotp-sg-atp.dts b/qcom/parrotp-sg-atp.dts new file mode 100644 index 00000000..e315796e --- /dev/null +++ b/qcom/parrotp-sg-atp.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrotp-sg.dtsi" +#include "parrot-wcn3990.dtsi" +#include "parrotp-sg-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. ParrotP SG ATP"; + compatible = "qcom,parrotp-atp", "qcom,parrotp", "qcom,atp"; + qcom,board-id = <33 0>; +}; diff --git a/qcom/parrotp-sg-atp.dtsi b/qcom/parrotp-sg-atp.dtsi new file mode 100644 index 00000000..df178a95 --- /dev/null +++ b/qcom/parrotp-sg-atp.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-sg-atp.dtsi" diff --git a/qcom/parrotp-sg-idp-nopmi.dts b/qcom/parrotp-sg-idp-nopmi.dts new file mode 100644 index 00000000..40942ef3 --- /dev/null +++ b/qcom/parrotp-sg-idp-nopmi.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrotp-sg.dtsi" +#include "parrot-wcn6750.dtsi" +#include "parrotp-sg-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. ParrotP SG IDP"; + compatible = "qcom,parrotp-idp", "qcom,parrotp", "qcom,idp"; + qcom,board-id = <34 0>; + qcom,pmic-id-size = <9>; + qcom,pmic-id = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; +}; diff --git a/qcom/parrotp-sg-idp-pm8350b.dts b/qcom/parrotp-sg-idp-pm8350b.dts new file mode 100644 index 00000000..e3e9e752 --- /dev/null +++ b/qcom/parrotp-sg-idp-pm8350b.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrotp-sg.dtsi" +#include "parrot-wcn6750.dtsi" +#include "parrotp-sg-idp.dtsi" +#include "parrot-idp-pm8350b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. ParrotP SG IDP"; + compatible = "qcom,parrotp-idp", "qcom,parrotp", "qcom,idp"; + qcom,board-id = <34 0>; +}; diff --git a/qcom/parrotp-sg-idp-wcn3990-amoled-rcm.dts b/qcom/parrotp-sg-idp-wcn3990-amoled-rcm.dts new file mode 100644 index 00000000..9d8691fd --- /dev/null +++ b/qcom/parrotp-sg-idp-wcn3990-amoled-rcm.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrotp-sg.dtsi" +#include "parrot-wcn3990.dtsi" +#include "parrotp-sg-idp-wcn3990-amoled-rcm.dtsi" +#include "parrot-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. ParrotP SG WCN3990 IDP + AMOLED + RCM"; + compatible = "qcom,parrotp-idp", "qcom,parrotp", "qcom,idp"; + qcom,board-id = <34 3>; +}; diff --git a/qcom/parrotp-sg-idp-wcn3990-amoled-rcm.dtsi b/qcom/parrotp-sg-idp-wcn3990-amoled-rcm.dtsi new file mode 100644 index 00000000..2017e3eb --- /dev/null +++ b/qcom/parrotp-sg-idp-wcn3990-amoled-rcm.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-sg-idp-wcn3990-amoled-rcm.dtsi" diff --git a/qcom/parrotp-sg-idp-wcn3990.dts b/qcom/parrotp-sg-idp-wcn3990.dts new file mode 100644 index 00000000..6faa5dd7 --- /dev/null +++ b/qcom/parrotp-sg-idp-wcn3990.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrotp-sg.dtsi" +#include "parrot-wcn3990.dtsi" +#include "parrotp-sg-idp-wcn3990.dtsi" +#include "parrot-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. ParrotP SG IDP + WCN3990"; + compatible = "qcom,parrotp-idp", "qcom,parrotp", "qcom,idp"; + qcom,board-id = <34 1>; +}; diff --git a/qcom/parrotp-sg-idp-wcn3990.dtsi b/qcom/parrotp-sg-idp-wcn3990.dtsi new file mode 100644 index 00000000..403d64b6 --- /dev/null +++ b/qcom/parrotp-sg-idp-wcn3990.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-sg-idp-wcn3990.dtsi" diff --git a/qcom/parrotp-sg-idp-wcn6750-amoled-rcm.dts b/qcom/parrotp-sg-idp-wcn6750-amoled-rcm.dts new file mode 100644 index 00000000..a72ee971 --- /dev/null +++ b/qcom/parrotp-sg-idp-wcn6750-amoled-rcm.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrotp-sg.dtsi" +#include "parrot-wcn6750.dtsi" +#include "parrotp-sg-idp-wcn6750-amoled-rcm.dtsi" +#include "parrot-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. ParrotP SG WCN6750 IDP + AMOLED + RCM"; + compatible = "qcom,parrotp-idp", "qcom,parrotp", "qcom,idp"; + qcom,board-id = <34 2>; +}; diff --git a/qcom/parrotp-sg-idp-wcn6750-amoled-rcm.dtsi b/qcom/parrotp-sg-idp-wcn6750-amoled-rcm.dtsi new file mode 100644 index 00000000..445c3218 --- /dev/null +++ b/qcom/parrotp-sg-idp-wcn6750-amoled-rcm.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-sg-idp-wcn6750-amoled-rcm.dtsi" diff --git a/qcom/parrotp-sg-idp-wcn6750-amoled.dts b/qcom/parrotp-sg-idp-wcn6750-amoled.dts new file mode 100644 index 00000000..5592cedf --- /dev/null +++ b/qcom/parrotp-sg-idp-wcn6750-amoled.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrotp-sg.dtsi" +#include "parrot-wcn6750.dtsi" +#include "parrotp-sg-idp-wcn6750-amoled.dtsi" +#include "parrot-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. ParrotP SG WCN6750 IDP + AMOLED"; + compatible = "qcom,parrotp-idp", "qcom,parrotp", "qcom,idp"; + qcom,board-id = <34 4>; +}; diff --git a/qcom/parrotp-sg-idp-wcn6750-amoled.dtsi b/qcom/parrotp-sg-idp-wcn6750-amoled.dtsi new file mode 100644 index 00000000..68af7ea9 --- /dev/null +++ b/qcom/parrotp-sg-idp-wcn6750-amoled.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-sg-idp-wcn6750-amoled.dtsi" diff --git a/qcom/parrotp-sg-idp.dts b/qcom/parrotp-sg-idp.dts new file mode 100644 index 00000000..3c8985f2 --- /dev/null +++ b/qcom/parrotp-sg-idp.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrotp-sg.dtsi" +#include "parrot-wcn6750.dtsi" +#include "parrotp-sg-idp.dtsi" +#include "parrot-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. ParrotP SG IDP"; + compatible = "qcom,parrotp-idp", "qcom,parrotp", "qcom,idp"; + qcom,board-id = <34 0>; +}; diff --git a/qcom/parrotp-sg-idp.dtsi b/qcom/parrotp-sg-idp.dtsi new file mode 100644 index 00000000..e96825bb --- /dev/null +++ b/qcom/parrotp-sg-idp.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-sg-idp.dtsi" diff --git a/qcom/parrotp-sg-qrd-nopmi.dts b/qcom/parrotp-sg-qrd-nopmi.dts new file mode 100644 index 00000000..40a3fdac --- /dev/null +++ b/qcom/parrotp-sg-qrd-nopmi.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrotp-sg.dtsi" +#include "parrot-wcn3990.dtsi" +#include "parrotp-sg-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. ParrotP SG QRD"; + compatible = "qcom,parrotp-qrd", "qcom,parrotp", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; + qcom,pmic-id-size = <9>; + qcom,pmic-id = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; +}; diff --git a/qcom/parrotp-sg-qrd-pm8350b.dts b/qcom/parrotp-sg-qrd-pm8350b.dts new file mode 100644 index 00000000..1a4fddb9 --- /dev/null +++ b/qcom/parrotp-sg-qrd-pm8350b.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrotp-sg.dtsi" +#include "parrot-wcn3990.dtsi" +#include "parrotp-sg-qrd.dtsi" +#include "parrot-qrd-pm8350b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. ParrotP SG QRD"; + compatible = "qcom,parrotp-qrd", "qcom,parrotp", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; +}; diff --git a/qcom/parrotp-sg-qrd-wcn6750.dts b/qcom/parrotp-sg-qrd-wcn6750.dts new file mode 100644 index 00000000..73daea69 --- /dev/null +++ b/qcom/parrotp-sg-qrd-wcn6750.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrotp-sg.dtsi" +#include "parrot-wcn6750.dtsi" +#include "parrotp-sg-qrd-wcn6750.dtsi" +#include "parrot-qrd-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. ParrotP SG WCN6750 QRD"; + compatible = "qcom,parrotp-qrd", "qcom,parrotp", "qcom,qrd"; + qcom,board-id = <0x1000B 1>; +}; diff --git a/qcom/parrotp-sg-qrd-wcn6750.dtsi b/qcom/parrotp-sg-qrd-wcn6750.dtsi new file mode 100644 index 00000000..9b286ff5 --- /dev/null +++ b/qcom/parrotp-sg-qrd-wcn6750.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-sg-qrd-wcn6750.dtsi" diff --git a/qcom/parrotp-sg-qrd.dts b/qcom/parrotp-sg-qrd.dts new file mode 100644 index 00000000..7c9c7353 --- /dev/null +++ b/qcom/parrotp-sg-qrd.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrotp-sg.dtsi" +#include "parrot-wcn3990.dtsi" +#include "parrotp-sg-qrd.dtsi" +#include "parrot-qrd-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. ParrotP SG QRD"; + compatible = "qcom,parrotp-qrd", "qcom,parrotp", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; +}; diff --git a/qcom/parrotp-sg-qrd.dtsi b/qcom/parrotp-sg-qrd.dtsi new file mode 100644 index 00000000..d35576f4 --- /dev/null +++ b/qcom/parrotp-sg-qrd.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-sg-qrd.dtsi" diff --git a/qcom/parrotp-sg.dts b/qcom/parrotp-sg.dts new file mode 100644 index 00000000..a4144ed1 --- /dev/null +++ b/qcom/parrotp-sg.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrotp-sg.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. ParrotP SG SoC"; + compatible = "qcom,parrotp"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/parrotp-sg.dtsi b/qcom/parrotp-sg.dtsi new file mode 100644 index 00000000..fb30189e --- /dev/null +++ b/qcom/parrotp-sg.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-sg.dtsi" + +/ { + + model = "Qualcomm Technologies, Inc. ParrotP SG"; + compatible = "qcom,parrotp"; + qcom,msm-id = <634 0x10000>; +}; + +&msm_gpu { + /delete-property/qcom,gpu-model; + qcom,gpu-model = "AdrenoA21v1"; +}; diff --git a/qcom/parrotp.dts b/qcom/parrotp.dts new file mode 100644 index 00000000..778774d1 --- /dev/null +++ b/qcom/parrotp.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrotp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. ParrotP SoC"; + compatible = "qcom,parrotp"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/parrotp.dtsi b/qcom/parrotp.dtsi new file mode 100644 index 00000000..64b0552b --- /dev/null +++ b/qcom/parrotp.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot.dtsi" + +/ { + + model = "Qualcomm Technologies, Inc. ParrotP"; + compatible = "qcom,parrotp"; + qcom,msm-id = <583 0x10000>, <631 0x10000>, <638 0x10000>; +}; diff --git a/qcom/platform_map.bzl b/qcom/platform_map.bzl index eea59c6e..a6838098 100644 --- a/qcom/platform_map.bzl +++ b/qcom/platform_map.bzl @@ -150,6 +150,39 @@ _platform_map = { {"name": "monaco-standalone-atp-v1-overlay.dtbo"}, ], }, + "parrot": { + "dtb_list": [ + # keep sorted + {"name": "parrot.dtb"}, + {"name": "parrotp.dtb"}, + {"name": "parrot-sg.dtb"}, + {"name": "parrotp-sg.dtb"}, + {"name": "parrot-4gb.dtb"}, + ], + "dtbo_list": [ + # keep sorted + {"name": "parrot-rumi-overlay.dtbo"}, + {"name": "parrot-atp-overlay.dtbo"}, + {"name": "parrot-idp-overlay.dtbo"}, + {"name": "parrot-idp-wcn3990-overlay.dtbo"}, + {"name": "parrot-idp-wcn3990-amoled-rcm-overlay.dtbo"}, + {"name": "parrot-idp-wcn6750-amoled-rcm-overlay.dtbo"}, + {"name": "parrot-idp-wcn6750-amoled-overlay.dtbo"}, + {"name": "parrot-idp-nopmi-overlay.dtbo"}, + {"name": "parrot-idp-pm8350b-overlay.dtbo"}, + {"name": "parrot-qrd-overlay.dtbo"}, + {"name": "parrot-qrd-wcn6750-overlay.dtbo"}, + {"name": "parrot-qrd-nopmi-overlay.dtbo"}, + {"name": "parrot-qrd-pm8350b-overlay.dtbo"}, + {"name": "parrot-idp-4gb-overlay.dtbo"}, + {"name": "parrot-idp-wcn3990-4gb-overlay.dtbo"}, + {"name": "parrot-idp-wcn3990-amoled-rcm-4gb-overlay.dtbo"}, + {"name": "parrot-idp-wcn6750-amoled-rcm-4gb-overlay.dtbo"}, + {"name": "parrot-idp-wcn6750-amoled-4gb-overlay.dtbo"}, + {"name": "parrot-qrd-4gb-overlay.dtbo"}, + {"name": "parrot-qrd-wcn6750-4gb-overlay.dtbo"}, + ], + }, } def _get_dtb_lists(target, dt_overlay_supported): diff --git a/qcom/pm6150l.dtsi b/qcom/pm6150l.dtsi new file mode 100644 index 00000000..5f476b01 --- /dev/null +++ b/qcom/pm6150l.dtsi @@ -0,0 +1,482 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + pm6150l_4: qcom,pm6150l@4 { + compatible = "qcom,spmi-pmic"; + reg = <4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm6150l_revid: qcom,revid@100 { + reg = <0x100>; + }; + + qcom,power-on@800 { + reg = <0x800>; + }; + + pm6150l_tz: qcom,temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels = <&pm6150l_vadc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + qcom,temperature-threshold-set = <1>; + }; + + pm6150l_bcl: bcl@3d00 { + compatible = "qcom,bcl-v5"; + reg = <0x3d00>; + interrupts = <0x4 0x3d 0x0 IRQ_TYPE_NONE>, + <0x4 0x3d 0x1 IRQ_TYPE_NONE>, + <0x4 0x3d 0x2 IRQ_TYPE_NONE>; + interrupt-names = "bcl-lvl0", + "bcl-lvl1", + "bcl-lvl2"; + #thermal-sensor-cells = <1>; + }; + + pm6150l_vadc: vadc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set"; + #io-channel-cells = <1>; + io-channel-ranges; + + /* Channel node */ + ref_gnd { + reg = ; + label = "ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + vref_1p25 { + reg = ; + label = "vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + die_temp { + reg = ; + label = "die_temp"; + qcom,pre-scaling = <1 1>; + }; + + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + }; + + pm6150l_adc_tm: adc_tm@3500 { + reg = <0x3500>; + interrupts = <0x4 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "threshold"; + #address-cells = <1>; + #size-cells = <0>; + #thermal-sensor-cells = <1>; + }; + + pm6150l_clkdiv: clock-controller@5b00 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5b00>; + #clock-cells = <1>; + qcom,num-clkdivs = <1>; + clock-output-names = "pm6150l_div_clk1"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + status = "disabled"; + }; + + pm6150l_gpios: pinctrl@c000 { + compatible = "qcom,pm6150l-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pm6150l_5: qcom,pm6150l@5 { + compatible ="qcom,spmi-pmic"; + reg = <5 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm6150l_pwm_1: qcom,pwms@bc00 { + status = "disabled"; + reg = <0xbc00>; + reg-names = "lpg-base"; + qcom,num-lpg-channels = <1>; + #pwm-cells = <2>; + }; + + pm6150l_lcdb: qcom,lcdb@ec00 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0xec00>; + interrupts = <0x5 0xec 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "sc-irq"; + qcom,pmic-revid = <&pm6150l_revid>; + qcom,voltage-step-ramp; + status = "disabled"; + + lcdb_ldo_vreg: ldo { + label = "ldo"; + regulator-name = "lcdb_ldo"; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <6000000>; + }; + + lcdb_ncp_vreg: ncp { + label = "ncp"; + regulator-name = "lcdb_ncp"; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <6000000>; + }; + + lcdb_bst_vreg: bst { + label = "bst"; + regulator-name = "lcdb_bst"; + regulator-min-microvolt = <4700000>; + regulator-max-microvolt = <6275000>; + }; + }; + + flash_led: qcom,leds@d300 { + status = "disabled"; + reg = <0xd300>; + label = "flash"; + interrupts = <0x5 0xd3 0x0 IRQ_TYPE_EDGE_RISING>, + <0x5 0xd3 0x3 IRQ_TYPE_EDGE_RISING>, + <0x5 0xd3 0x4 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "led-fault-irq", + "all-ramp-down-done-irq", + "all-ramp-up-done-irq"; + qcom,hdrm-auto-mode; + qcom,short-circuit-det; + qcom,open-circuit-det; + qcom,vph-droop-det; + qcom,thermal-derate-en; + qcom,thermal-derate-current = <200 500 1000>; + qcom,isc-delay = <192>; + qcom,pmic-revid = <&pm6150l_revid>; + + pm6150l_flash0: qcom,flash_0 { + label = "flash"; + qcom,led-name = "led:flash_0"; + qcom,max-current = <1500>; + qcom,default-led-trigger = "flash0_trigger"; + qcom,id = <0>; + qcom,current-ma = <1000>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pm6150l_flash1: qcom,flash_1 { + label = "flash"; + qcom,led-name = "led:flash_1"; + qcom,max-current = <1500>; + qcom,default-led-trigger = "flash1_trigger"; + qcom,id = <1>; + qcom,current-ma = <1000>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pm6150l_flash2: qcom,flash_2 { + label = "flash"; + qcom,led-name = "led:flash_2"; + qcom,max-current = <750>; + qcom,default-led-trigger = "flash2_trigger"; + qcom,id = <2>; + qcom,current-ma = <500>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + status = "disabled"; + }; + + pm6150l_torch0: qcom,torch_0 { + label = "torch"; + qcom,led-name = "led:torch_0"; + qcom,max-current = <500>; + qcom,default-led-trigger = "torch0_trigger"; + qcom,id = <0>; + qcom,current-ma = <300>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pm6150l_torch1: qcom,torch_1 { + label = "torch"; + qcom,led-name = "led:torch_1"; + qcom,max-current = <500>; + qcom,default-led-trigger = "torch1_trigger"; + qcom,id = <1>; + qcom,current-ma = <300>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pm6150l_torch2: qcom,torch_2 { + label = "torch"; + qcom,led-name = "led:torch_2"; + qcom,max-current = <500>; + qcom,default-led-trigger = "torch2_trigger"; + qcom,id = <2>; + qcom,current-ma = <300>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + status = "disabled"; + }; + + pm6150l_switch0: qcom,led_switch_0 { + label = "switch"; + qcom,led-name = "led:switch_0"; + qcom,led-mask = <1>; + qcom,default-led-trigger = "switch0_trigger"; + }; + + pm6150l_switch1: qcom,led_switch_1 { + label = "switch"; + qcom,led-name = "led:switch_1"; + qcom,led-mask = <2>; + qcom,default-led-trigger = "switch1_trigger"; + }; + + pm6150l_switch2: qcom,led_switch_2 { + label = "switch"; + qcom,led-name = "led:switch_2"; + qcom,led-mask = <3>; + qcom,default-led-trigger = "switch2_trigger"; + }; + }; + + pm6150l_wled: qcom,wled@d800 { + reg = <0xd800>, <0xd900>; + reg-names = "wled-ctrl-base", "wled-sink-base"; + label = "backlight"; + interrupts = <0x5 0xd8 0x1 IRQ_TYPE_EDGE_RISING>, + <0x5 0xd8 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x5 0xd8 0x5 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "ovp-irq", "pre-flash-irq", + "flash-irq"; + qcom,auto-calibration; + status = "disabled"; + + wled_flash: qcom,wled-flash { + label = "flash"; + qcom,default-led-trigger = "wled_flash"; + }; + + wled_torch: qcom,wled-torch { + label = "torch"; + qcom,default-led-trigger = "wled_torch"; + qcom,wled-torch-timer = <1200>; + }; + + wled_switch: qcom,wled-switch { + label = "switch"; + qcom,default-led-trigger = "wled_switch"; + }; + }; + + pm6150l_lpg: qcom,pwms@b100 { + reg = <0xb100>, <0xb000>; + reg-names = "lpg-base", "lut-base"; + #pwm-cells = <2>; + qcom,num-lpg-channels = <3>; + qcom,lut-patterns = <0 10 20 30 40 50 60 70 80 90 100 + 90 80 70 60 50 40 30 20 10 0>; + lpg1 { + qcom,lpg-chan-id = <1>; + qcom,ramp-step-ms = <100>; + qcom,ramp-pause-hi-count = <2>; + qcom,ramp-pause-lo-count = <2>; + qcom,ramp-low-index = <0>; + qcom,ramp-high-index = <20>; + qcom,ramp-from-low-to-high; + qcom,ramp-pattern-repeat; + }; + + lpg2 { + qcom,lpg-chan-id = <2>; + qcom,ramp-step-ms = <100>; + qcom,ramp-pause-hi-count = <2>; + qcom,ramp-pause-lo-count = <2>; + qcom,ramp-low-index = <0>; + qcom,ramp-high-index = <20>; + qcom,ramp-from-low-to-high; + qcom,ramp-pattern-repeat; + }; + + lpg3 { + qcom,lpg-chan-id = <3>; + qcom,ramp-step-ms = <100>; + qcom,ramp-pause-hi-count = <2>; + qcom,ramp-pause-lo-count = <2>; + qcom,ramp-low-index = <0>; + qcom,ramp-high-index = <20>; + qcom,ramp-from-low-to-high; + qcom,ramp-pattern-repeat; + }; + }; + + pm6150l_rgb_led: qcom,leds@d000 { + reg = <0xd000>; + red { + label = "red"; + pwms = <&pm6150l_lpg 0 1000000>; + led-sources = <0>; + linux,default-trigger = "timer"; + }; + + green { + label = "green"; + pwms = <&pm6150l_lpg 1 1000000>; + led-sources = <1>; + linux,default-trigger = "timer"; + }; + + blue { + label = "blue"; + pwms = <&pm6150l_lpg 2 1000000>; + led-sources = <2>; + linux,default-trigger = "timer"; + }; + }; + + pm6150a_amoled: qcom,amoled { + status = "disabled"; + + oledb_vreg: oledb@e000 { + reg = <0xe000>; + reg-names = "oledb_base"; + regulator-name = "oledb"; + regulator-min-microvolt = <4925000>; + regulator-max-microvolt = <8100000>; + qcom,swire-control; + }; + + ab_vreg: ab@de00 { + reg = <0xde00>; + reg-names = "ab_base"; + regulator-name = "ab"; + regulator-min-microvolt = <4600000>; + regulator-max-microvolt = <6100000>; + qcom,swire-control; + }; + + ibb_vreg: ibb@dc00 { + reg = <0xdc00>; + reg-names = "ibb_base"; + regulator-name = "ibb"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <5400000>; + qcom,swire-control; + }; + }; + }; +}; + +&thermal_zones { + pm6150l_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm6150l_tz>; + + trips { + pm6150l_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pm6150l_trip1: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "passive"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; + + pm6150l-bcl-lvl0 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm6150l_bcl 5>; + + trips { + l_bcl_lvl0: l-bcl-lvl0 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + pm6150l-bcl-lvl1 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm6150l_bcl 6>; + + trips { + l_bcl_lvl1: l-bcl-lvl1 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + pm6150l-bcl-lvl2 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm6150l_bcl 7>; + + trips { + l_bcl_lvl2: l-bcl-lvl2 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; +}; diff --git a/qcom/pm6450.dtsi b/qcom/pm6450.dtsi new file mode 100644 index 00000000..3c08ec15 --- /dev/null +++ b/qcom/pm6450.dtsi @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + qcom,pm6450@1 { + compatible = "qcom,spmi-pmic"; + reg = <1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm6450_tz: qcom,temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm6450_gpios: pinctrl@8800 { + compatible = "qcom,pm6450-gpio"; + reg = <0x8800>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pm6450_pwm_1: qcom,pwms@e800 { + status = "disabled"; + reg = <0xe800>; + reg-names = "lpg-base"; + qcom,num-lpg-channels = <1>; + #pwm-cells = <2>; + }; + }; +}; + +&thermal_zones { + pm6450_temp_alarm: pm6450_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm6450_tz>; + + trips { + pm6450_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pm6450_trip1: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "passive"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; +}; diff --git a/qcom/pm7250b.dtsi b/qcom/pm7250b.dtsi new file mode 100644 index 00000000..4559bd12 --- /dev/null +++ b/qcom/pm7250b.dtsi @@ -0,0 +1,374 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + pm7250b_2: qcom,pm7250b@2 { + compatible = "qcom,spmi-pmic"; + reg = <2 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + qcom,power-on@800 { + reg = <0x800>; + }; + + pm7250b_tz: qcom,temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x2 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels = <&pm7250b_vadc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + qcom,temperature-threshold-set = <1>; + }; + + pm7250b_clkdiv: clock-controller@5b00 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5b00>; + #clock-cells = <1>; + qcom,num-clkdivs = <1>; + clock-output-names = "pm7250b_div_clk1"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + status = "disabled"; + }; + + pm7250b_vadc: vadc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set"; + #io-channel-cells = <1>; + io-channel-ranges; + + /* Channel node */ + ref_gnd@0 { + reg = ; + label = "ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + vref_1p25@1 { + reg = ; + label = "vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + die_temp@2 { + reg = ; + label = "die_temp"; + qcom,pre-scaling = <1 1>; + }; + + vph_pwr@83 { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + vbat_sns@84 { + reg = ; + label = "vbat_sns"; + qcom,pre-scaling = <1 3>; + }; + + usb_in_i_uv@7 { + reg = ; + label = "usb_in_i_uv"; + qcom,pre-scaling = <1 1>; + }; + + usb_in_v_div_16@8 { + reg = ; + label = "usb_in_v_div_16"; + qcom,pre-scaling = <1 16>; + }; + + chg_temp@9 { + reg = ; + label = "chg_temp"; + qcom,pre-scaling = <1 1>; + }; + + bat_therm@4a { + reg = ; + label = "bat_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + bat_therm_30k@2a { + reg = ; + label = "bat_therm_30k"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + bat_therm_400k@6a { + reg = ; + label = "bat_therm_400k"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + bat_id@4b { + reg = ; + label = "bat_id"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + smb1390_therm@e { + reg = ; + label = "smb1390_therm"; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + chg_sbux@99 { + reg = ; + label = "chg_sbux"; + qcom,pre-scaling = <1 3>; + }; + + mid_chg_div6@1e { + reg = ; + label = "chg_mid"; + qcom,pre-scaling = <1 6>; + }; + }; + + pm7250b_adc_tm: adc_tm@3500 { + reg = <0x3500>; + interrupts = <0x2 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "threshold"; + #address-cells = <1>; + #size-cells = <0>; + #thermal-sensor-cells = <1>; + }; + + pm7250b_bcl: bcl@1d00 { + compatible = "qcom,bcl-v5"; + reg = <0x1d00>; + interrupts = <0x2 0x1d 0x0 IRQ_TYPE_NONE>, + <0x2 0x1d 0x1 IRQ_TYPE_NONE>, + <0x2 0x1d 0x2 IRQ_TYPE_NONE>; + interrupt-names = "bcl-lvl0", + "bcl-lvl1", + "bcl-lvl2"; + #thermal-sensor-cells = <1>; + }; + + bcl_soc:bcl-soc { + compatible = "qcom,msm-bcl-soc"; + #thermal-sensor-cells = <0>; + }; + + pm7250b_gpios: pinctrl@c000 { + compatible = "qcom,pm7250b-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pm7250b_3: qcom,pm7250b@3 { + compatible = "qcom,spmi-pmic"; + reg = <3 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm7250b_vib: qcom,vibrator@5300 { + reg = <0x5300>; + qcom,vib-ldo-volt-uv = <3000000>; + qcom,disable-overdrive; + }; + }; +}; + +&thermal_zones { + pm7250b_temp_alarm: pm7250b_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm7250b_tz>; + + trips { + pm7250b_trip0: trip0 { + temperature = <90000>; + hysteresis = <0>; + type = "passive"; + }; + + pm7250b_trip1: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "passive"; + }; + + pm7250b_trip2: trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; + + pm7250b-ibat-lvl0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm7250b_bcl 0>; + + trips { + ibat_lvl0:ibat-lvl0 { + temperature = <5500>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pm7250b-ibat-lvl1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm7250b_bcl 1>; + + trips { + ibat_lvl1:ibat-lvl1 { + temperature = <6000>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pm7250b-bcl-lvl0 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm7250b_bcl 5>; + + trips { + thermal-engine-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + thermal-hal-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + b_bcl_lvl0: b-bcl-lvl0 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + pm7250b-bcl-lvl1 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm7250b_bcl 6>; + + trips { + thermal-engine-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + thermal-hal-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + b_bcl_lvl1: b-bcl-lvl1 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + pm7250b-bcl-lvl2 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm7250b_bcl 7>; + + trips { + thermal-engine-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + thermal-hal-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + b_bcl_lvl2: b-bcl-lvl2 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + socd { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&bcl_soc>; + + trips { + thermal-engine-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + thermal-hal-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + socd_trip:socd-trip { + temperature = <90>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; +}; diff --git a/qcom/pm8350b.dtsi b/qcom/pm8350b.dtsi new file mode 100644 index 00000000..06c66741 --- /dev/null +++ b/qcom/pm8350b.dtsi @@ -0,0 +1,389 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + qcom,pm8350b@3 { + compatible = "qcom,spmi-pmic"; + reg = <3 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8350b_tz: qcom,temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8350b_pbs2: qcom,pbs@1900 { + compatible = "qcom,qpnp-pbs"; + reg = <0x1900>; + }; + + pm8350b_gpios: pinctrl@8800 { + compatible = "qcom,pm8350b-gpio"; + reg = <0x8800>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pm8350b_bcl: bcl@4700 { + compatible = "qcom,bcl-v5"; + reg = <0x4700 0x100>; + interrupts = <0x3 0x47 0x0 IRQ_TYPE_NONE>, + <0x3 0x47 0x1 IRQ_TYPE_NONE>, + <0x3 0x47 0x2 IRQ_TYPE_NONE>; + interrupt-names = "bcl-lvl0", + "bcl-lvl1", + "bcl-lvl2"; + qcom,pmic7-threshold; + #thermal-sensor-cells = <1>; + }; + + bcl_soc:bcl-soc { + compatible = "qcom,msm-bcl-soc"; + #thermal-sensor-cells = <0>; + }; + + pm8350b_haptics: qcom,hv-haptics@f000 { + compatible = "qcom,hv-haptics"; + reg = <0xf000>, <0xf100>, <0xf200>; + interrupts = <0x3 0xf0 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "fifo-empty"; + qcom,vmax-mv = <3600>; + qcom,brake-mode = ; + qcom,brake-pattern = /bits/ 8 <0xff 0x3f 0x1f>; + qcom,lra-period-us = <6667>; + qcom,drv-sig-shape = ; + qcom,brake-sig-shape = ; + status = "disabled"; + + hap_swr_slave_reg: qcom,hap-swr-slave-reg { + regulator-name = "hap-swr-slave-reg"; + }; + + effect_0 { + /* CLICK */ + qcom,effect-id = <0>; + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern-data = <0x01f S_PERIOD_T_LRA 0>, + <0x03f S_PERIOD_T_LRA 0>, + <0x05f S_PERIOD_T_LRA 0>, + <0x07f S_PERIOD_T_LRA 0>, + <0x17f S_PERIOD_T_LRA 0>, + <0x15f S_PERIOD_T_LRA 0>, + <0x13f S_PERIOD_T_LRA 0>, + <0x11f S_PERIOD_T_LRA 0>; + qcom,wf-pattern-period-us = <6667>; + qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>; + qcom,wf-pattern-preload; + qcom,wf-auto-res-disable; + }; + + effect_1 { + /* DOUBLE_CLICK */ + qcom,effect-id = <1>; + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern-data = <0x01f S_PERIOD_T_LRA 0>, + <0x03f S_PERIOD_T_LRA 0>, + <0x05f S_PERIOD_T_LRA 0>, + <0x07f S_PERIOD_T_LRA 0>, + <0x17f S_PERIOD_T_LRA 0>, + <0x15f S_PERIOD_T_LRA 0>, + <0x13f S_PERIOD_T_LRA 0>, + <0x11f S_PERIOD_T_LRA 0>; + qcom,wf-pattern-period-us = <6667>; + qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>; + qcom,wf-auto-res-disable; + }; + + effect_2 { + /* TICK */ + qcom,effect-id = <2>; + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern-data = <0x01f S_PERIOD_T_LRA 0>, + <0x03f S_PERIOD_T_LRA 0>, + <0x05f S_PERIOD_T_LRA 0>, + <0x07f S_PERIOD_T_LRA 0>, + <0x17f S_PERIOD_T_LRA 0>, + <0x15f S_PERIOD_T_LRA 0>, + <0x13f S_PERIOD_T_LRA 0>, + <0x11f S_PERIOD_T_LRA 0>; + qcom,wf-pattern-period-us = <6667>; + qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>; + qcom,wf-auto-res-disable; + }; + + effect_3 { + /* THUD */ + qcom,effect-id = <3>; + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern-data = <0x01f S_PERIOD_T_LRA 0>, + <0x03f S_PERIOD_T_LRA 0>, + <0x05f S_PERIOD_T_LRA 0>, + <0x07f S_PERIOD_T_LRA 0>, + <0x17f S_PERIOD_T_LRA 0>, + <0x15f S_PERIOD_T_LRA 0>, + <0x13f S_PERIOD_T_LRA 0>, + <0x11f S_PERIOD_T_LRA 0>; + qcom,wf-pattern-period-us = <6667>; + qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>; + qcom,wf-auto-res-disable; + }; + + effect_4 { + /* POP */ + qcom,effect-id = <4>; + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern-data = <0x01f S_PERIOD_T_LRA 0>, + <0x03f S_PERIOD_T_LRA 0>, + <0x05f S_PERIOD_T_LRA 0>, + <0x07f S_PERIOD_T_LRA 0>, + <0x17f S_PERIOD_T_LRA 0>, + <0x15f S_PERIOD_T_LRA 0>, + <0x13f S_PERIOD_T_LRA 0>, + <0x11f S_PERIOD_T_LRA 0>; + qcom,wf-pattern-period-us = <6667>; + qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>; + qcom,wf-auto-res-disable; + }; + + effect_5 { + /* HEAVY CLICK */ + qcom,effect-id = <5>; + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern-data = <0x01f S_PERIOD_T_LRA 0>, + <0x03f S_PERIOD_T_LRA 0>, + <0x05f S_PERIOD_T_LRA 0>, + <0x07f S_PERIOD_T_LRA 0>, + <0x17f S_PERIOD_T_LRA 0>, + <0x15f S_PERIOD_T_LRA 0>, + <0x13f S_PERIOD_T_LRA 0>, + <0x11f S_PERIOD_T_LRA 0>; + qcom,wf-pattern-period-us = <6667>; + qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>; + qcom,wf-auto-res-disable; + }; + }; + + pm8350b_amoled: qcom,amoled { + #address-cells = <1>; + #size-cells = <0>; + + oledb_vreg: oledb@fa00 { + reg = <0xfa00>; + reg-names = "oledb_base"; + regulator-name = "oledb"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <8000000>; + qcom,swire-control; + }; + + ab_vreg: ab@f900 { + reg = <0xf900>; + reg-names = "ab_base"; + regulator-name = "ab"; + regulator-min-microvolt = <4600000>; + regulator-max-microvolt = <5200000>; + qcom,swire-control; + }; + + ibb_vreg: ibb@f800 { + reg = <0xf800>; + reg-names = "ibb_base"; + regulator-name = "ibb"; + regulator-min-microvolt = <1400000>; + regulator-max-microvolt = <6600000>; + qcom,swire-control; + regulator-allow-set-load; + }; + }; + + qcom,amoled-ecm@f900 { + compatible = "qcom,amoled-ecm"; + reg = <0xf900>; + nvmem-names = "amoled-ecm-sdam0", "amoled-ecm-sdam1", + "amoled-ecm-sdam2"; + nvmem = <&pmk8350_sdam_13>, <&pmk8350_sdam_14>, + <&pmk8350_sdam_41>; + interrupt-names = "ecm-sdam0", "ecm-sdam1", + "ecm-sdam2"; + interrupts = <0x0 0x7c 0x1 IRQ_TYPE_EDGE_RISING>, + <0x0 0x7d 0x1 IRQ_TYPE_EDGE_RISING>, + <0x0 0x98 0x1 IRQ_TYPE_EDGE_RISING>; + }; + }; +}; + +&thermal_zones { + pm8350b_temp_alarm: pm8350b_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pm8350b_tz>; + + trips { + pm8350b_trip0: trip0 { + temperature = <90000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8350b_trip1: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8350b_trip2: trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; + + pm8350b-ibat-lvl0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8350b_bcl 0>; + + trips { + ibat_lvl0:ibat-lvl0 { + temperature = <9000>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pm8350b-ibat-lvl1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8350b_bcl 1>; + + trips { + ibat_lvl1:ibat-lvl1 { + temperature = <10000>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pm8350b-bcl-lvl0 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pm8350b_bcl 5>; + + trips { + thermal-engine-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + thermal-hal-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + b_bcl_lvl0: b-bcl-lvl0 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + pm8350b-bcl-lvl1 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pm8350b_bcl 6>; + + trips { + thermal-engine-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + thermal-hal-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + b_bcl_lvl1: b-bcl-lvl1 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + pm8350b-bcl-lvl2 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pm8350b_bcl 7>; + + trips { + thermal-engine-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + thermal-hal-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + b_bcl_lvl2: b-bcl-lvl2 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + socd { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&bcl_soc>; + + trips { + thermal-engine-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + thermal-hal-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + socd_trip:socd-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; +}; diff --git a/qcom/pmk8350.dtsi b/qcom/pmk8350.dtsi new file mode 100644 index 00000000..2c947449 --- /dev/null +++ b/qcom/pmk8350.dtsi @@ -0,0 +1,258 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + pmk8350: qcom,pmk8350@0 { + compatible = "qcom,spmi-pmic"; + reg = <0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pon_pbs@800 { + reg = <0x800>; + qcom,system-reset; + qcom,store-hard-reset-reason; + }; + + pmk8350_pon: pon_hlos@1300 { + reg = <0x1300>; + interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "kpdpwr", "resin"; + }; + + pmk8350_vadc: vadc@3100 { + compatible = "qcom,spmi-adc7"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set"; + #io-channel-cells = <1>; + io-channel-ranges; + + /* PMK8350 Channel nodes */ + pmk8350_ref_gnd { + reg = ; + label = "pmk8350_ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + pmk8350_vref_1p25 { + reg = ; + label = "pmk8350_vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + pmk8350_die_temp { + reg = ; + label = "pmk8350_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + pmk8350_xo_therm { + reg = ; + label = "pmk8350_xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + /* PM8350 Channel nodes */ + pm8350_ref_gnd { + reg = ; + label = "pm8350_ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + pm8350_vref_1p25 { + reg = ; + label = "pm8350_vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + pm8350_die_temp { + reg = ; + label = "pm8350_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + pm8350_vph_pwr { + reg = ; + label = "pm8350_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + /* PM8350b Channel nodes */ + pm8350b_ref_gnd { + reg = ; + label = "pm8350b_ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + pm8350b_vref_1p25 { + reg = ; + label = "pm8350b_vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + pm8350b_die_temp { + reg = ; + label = "pm8350b_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + pm8350b_vph_pwr { + reg = ; + label = "pm8350b_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + pm8350b_vbat_sns { + reg = ; + label = "pm8350b_vbat_sns"; + qcom,pre-scaling = <1 3>; + }; + + /* PMR735a Channel nodes */ + pmr735a_ref_gnd { + reg = ; + label = "pmr735a_ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + pmr735a_vref_1p25 { + reg = ; + label = "pmr735a_vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + pmr735a_die_temp { + reg = ; + label = "pmr735a_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PMR735b Channel nodes */ + pmr735b_ref_gnd { + reg = ; + label = "pmr735b_ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + pmr735b_vref_1p25 { + reg = ; + label = "pmr735b_vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + pmr735b_die_temp { + reg = ; + label = "pmr735b_die_temp"; + qcom,pre-scaling = <1 1>; + }; + }; + + pmk8350_adc_tm: adc_tm@3400 { + reg = <0x3400>; + interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "threshold"; + #address-cells = <1>; + #size-cells = <0>; + #thermal-sensor-cells = <1>; + }; + + pmk8350_sdam_1: sdam@7000 { + compatible = "qcom,spmi-sdam"; + reg = <0x7000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + pmk8350_sdam_2: sdam@7100 { + compatible = "qcom,spmi-sdam"; + reg = <0x7100>; + #address-cells = <1>; + #size-cells = <1>; + + restart_reason: restart@48 { + reg = <0x48 0x1>; + bits = <1 7>; + }; + }; + + pmk8350_sdam_5: sdam@7400 { + compatible = "qcom,spmi-sdam"; + reg = <0x7400>; + }; + + pmk8350_sdam_13: sdam@7c00 { + compatible = "qcom,spmi-sdam"; + reg = <0x7c00>; + }; + + pmk8350_sdam_14: sdam@7d00 { + compatible = "qcom,spmi-sdam"; + reg = <0x7d00>; + }; + + pmk8350_sdam_21: sdam@8400 { + compatible = "qcom,spmi-sdam"; + reg = <0x8400>; + }; + + pmk8350_sdam_22: sdam@8500 { + compatible = "qcom,spmi-sdam"; + reg = <0x8500>; + }; + + pmk8350_sdam_23: sdam@8600 { + compatible = "qcom,spmi-sdam"; + reg = <0x8600>; + #address-cells = <1>; + #size-cells = <1>; + }; + + pmk8350_sdam_41: sdam@9800 { + compatible = "qcom,spmi-sdam"; + reg = <0x9800>; + }; + + pmk8350_sdam_46: sdam@9d00 { + compatible = "qcom,spmi-sdam"; + reg = <0x9d00>; + }; + + pmk8350_gpios: pinctrl@b000 { + compatible = "qcom,pmk8350-gpio"; + reg = <0xb000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pmk8350_rtc: rtc@6100 { + compatible = "qcom,pmk8350-rtc"; + reg = <0x6100>, <0x6200>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; + }; + }; +}; diff --git a/qcom/pmr735a.dtsi b/qcom/pmr735a.dtsi new file mode 100644 index 00000000..00107934 --- /dev/null +++ b/qcom/pmr735a.dtsi @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + pmr735a_spmi: qcom,pmr735a@4 { + compatible = "qcom,spmi-pmic"; + reg = <4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmr735a_tz: qcom,temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmr735a_gpios: pinctrl@8800 { + compatible = "qcom,pmr735a-gpio"; + reg = <0x8800>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +&thermal_zones { + pmr735a_temp_alarm: pmr735a_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pmr735a_tz>; + + trips { + pmr735a_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pmr735a_trip1: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "passive"; + }; + + pmr735a_trip2: trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; +}; diff --git a/qcom/waipio-thermal-modem.dtsi b/qcom/waipio-thermal-modem.dtsi new file mode 100644 index 00000000..c6c5df15 --- /dev/null +++ b/qcom/waipio-thermal-modem.dtsi @@ -0,0 +1,669 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + qmi-tmd-devices { + compatible = "qcom,qmi-cooling-devices"; + + modem { + qcom,instance-id = ; + + modem_lte_dsc: mmodem_lte_dsc_kr { + qcom,qmi-dev-name = "modem_lte_dsc"; + #cooling-cells = <2>; + }; + + modem_nr_dsc: modem_nr_dsc_kr { + qcom,qmi-dev-name = "modem_nr_dsc"; + #cooling-cells = <2>; + }; + + modem_nr_scg_dsc: modem_nr_scg_dsc_kr { + qcom,qmi-dev-name = "modem_nr_scg_dsc"; + #cooling-cells = <2>; + }; + + sdr0_lte_dsc: sdr0_lte_dsc_kr { + qcom,qmi-dev-name = "sdr0_lte_dsc"; + #cooling-cells = <2>; + }; + + sdr1_lte_dsc: sdr1_lte_dsc_kr { + qcom,qmi-dev-name = "sdr1_lte_dsc"; + #cooling-cells = <2>; + }; + + sdr0_nr_dsc: sdr0_nr_dsc_kr { + qcom,qmi-dev-name = "sdr0_nr_dsc"; + #cooling-cells = <2>; + }; + + sdr1_nr_dsc: sdr1_nr_dsc_kr { + qcom,qmi-dev-name = "sdr1_nr_dsc"; + #cooling-cells = <2>; + }; + + pa_lte_sdr0_dsc: pa_lte_sdr0_dsc_kr { + qcom,qmi-dev-name = "pa_lte_sdr0_dsc"; + #cooling-cells = <2>; + }; + + pa_lte_sdr1_dsc: pa_lte_sdr1_dsc_kr { + qcom,qmi-dev-name = "pa_lte_sdr1_dsc"; + #cooling-cells = <2>; + }; + + pa_nr_sdr0_dsc: pa_nr_sdr0_dsc_kr { + qcom,qmi-dev-name = "pa_nr_sdr0_dsc"; + #cooling-cells = <2>; + }; + + pa_nr_sdr1_dsc: pa_nr_sdr1_dsc_kr { + qcom,qmi-dev-name = "pa_nr_sdr1_dsc"; + #cooling-cells = <2>; + }; + + pa_nr_sdr0_scg_dsc: pa_nr_sdr0_scg_kr { + qcom,qmi-dev-name = "pa_nr_sdr0_scg_dsc"; + #cooling-cells = <2>; + }; + + pa_nr_sdr1_scg_dsc: pa_nr_sdr1_scg_kr { + qcom,qmi-dev-name = "pa_nr_sdr1_scg_dsc"; + #cooling-cells = <2>; + }; + + mmw0_dsc: mmw0_dsc_kr { + qcom,qmi-dev-name = "mmw0_dsc"; + #cooling-cells = <2>; + }; + + mmw1_dsc: mmw1_dsc_kr { + qcom,qmi-dev-name = "mmw1_dsc"; + #cooling-cells = <2>; + }; + + mmw2_dsc: mmw2_dsc_kr { + qcom,qmi-dev-name = "mmw2_dsc"; + #cooling-cells = <2>; + }; + + mmw3_dsc: mmw3_dsc_kr { + qcom,qmi-dev-name = "mmw3_dsc"; + #cooling-cells = <2>; + }; + + mmw_ific_dsc: mmw_ific_dsc_kr { + qcom,qmi-dev-name = "mmw_ific_dsc"; + #cooling-cells = <2>; + }; + + qmi_wlan: wlan { + qcom,qmi-dev-name = "wlan"; + #cooling-cells = <2>; + }; + + modem_vdd: modem_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <2>; + }; + }; + + modem_usr { + qcom,instance-id = ; + + mmodem_lte_dsc { + qcom,qmi-dev-name = "modem_lte_dsc"; + }; + + modem_nr_dsc { + qcom,qmi-dev-name = "modem_nr_dsc"; + }; + + modem_nr_scg_dsc { + qcom,qmi-dev-name = "modem_nr_scg_dsc"; + }; + + sdr0_lte_dsc { + qcom,qmi-dev-name = "sdr0_lte_dsc"; + }; + + sdr1_lte_dsc { + qcom,qmi-dev-name = "sdr1_lte_dsc"; + }; + + sdr0_nr_dsc { + qcom,qmi-dev-name = "sdr0_nr_dsc"; + }; + + sdr1_nr_dsc { + qcom,qmi-dev-name = "sdr1_nr_dsc"; + }; + + pa_lte_sdr0_dsc { + qcom,qmi-dev-name = "pa_lte_sdr0_dsc"; + }; + + pa_lte_sdr1_dsc { + qcom,qmi-dev-name = "pa_lte_sdr1_dsc"; + }; + + pa_nr_sdr0_dsc { + qcom,qmi-dev-name = "pa_nr_sdr0_dsc"; + }; + + pa_nr_sdr1_dsc { + qcom,qmi-dev-name = "pa_nr_sdr1_dsc"; + }; + + pa_nr_sdr0_scg_dsc { + qcom,qmi-dev-name = "pa_nr_sdr0_scg_dsc"; + }; + + pa_nr_sdr1_scg_dsc { + qcom,qmi-dev-name = "pa_nr_sdr1_scg_dsc"; + }; + + mmw0_dsc { + qcom,qmi-dev-name = "mmw0_dsc"; + }; + + mmw1_dsc { + qcom,qmi-dev-name = "mmw1_dsc"; + }; + + mmw2_dsc { + qcom,qmi-dev-name = "mmw2_dsc"; + }; + + mmw3_dsc { + qcom,qmi-dev-name = "mmw3_dsc"; + }; + + mmw_ific_dsc { + qcom,qmi-dev-name = "mmw_ific_dsc"; + }; + }; + }; + + qmi_sensor: qmi-ts-sensors { + compatible = "qcom,qmi-sensors"; + #thermal-sensor-cells = <1>; + + modem { + qcom,instance-id = ; + qcom,qmi-sensor-names = "pa", + "pa_1", + "sys_therm1", + "sys_therm2", + "modem_bcl_warn", + "modem_tsens", + "modem_tsens1", + "sdr0_pa0", + "sdr0", + "sdr1_pa0", + "sdr1", + "sdr_mmw_therm", + "mmw0", + "mmw1", + "mmw2", + "mmw3", + "mmw_pa1", + "mmw_pa2", + "mmw_pa3", + "mmw_ific0", + "sub1_modem_cfg", + "sub1_lte_cc", + "sub1_mcg_fr1_cc", + "sub1_mcg_fr2_cc", + "sub1_scg_fr1_cc", + "sub1_scg_fr2_cc", + "sdr0_pa", + "sdr1_pa"; + }; + }; +}; + +&thermal_zones { + pa { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_PA)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_PA_1)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + bcl-warn { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_BCL_WARN)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sdr0-pa0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SDR0_PA0)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sdr0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SDR0)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sdr1-pa0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SDR1_PA0)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sdr1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SDR1)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sdr-mmw-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SDR_MMW)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + mmw0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_MMW0)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + mmw1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_MMW1)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + mmw2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_MMW2)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + mmw3 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_MMW3)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + mmw_pa1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_MMW_PA1)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + mmw_pa2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_MMW_PA2)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + mmw_pa3 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_MMW_PA3)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + mmw-ific0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_MMW_IFIC0)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sub1-modem-cfg { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SUB1_MODEM_CFG)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sub1-lte-cc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SUB1_LTE_CC)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sub1_mcg_fr1_cc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SUB1_MCG_FR1_CC)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sub1_mcg_fr2_cc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SUB1_MCG_FR2_CC)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sub1_scg_fr1_cc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SUB1_SCG_FR1_CC)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sub1_scg_fr2_cc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SUB1_SCG_FR2_CC)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sdr0-pa { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SDR0_PA)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sdr1-pa { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SDR1_PA)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +};