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ARM: dts: msm: add FHD+ mode for csot panel

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This change add a mode with FHD+ resolution for csot panel.

Change-Id: I72c5efc4159fb0ed99fcaa5fd93069601993d598
Signed-off-by: Jinfeng Gu <quic_gjinfeng@quicinc.com>
This commit is contained in:
Jinfeng Gu
2024-04-06 22:24:12 +08:00
parent b9fe27e94b
commit daf6614ab6
6 changed files with 673 additions and 117 deletions
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66
display/sun-sde-display-common.dtsi
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@@ -14,6 +14,7 @@
#include "dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi"
#include "dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi"
#include "dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi"
#include "dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi"
#include "dsi-panel-sharp-dsc-4k-cmd.dtsi"
#include "dsi-panel-sharp-dsc-4k-video.dtsi"
#include "dsi-panel-sim-cmd-au.dtsi"
@@ -373,48 +374,41 @@
};
timing@1 {
qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a
0b 0a 02 04 00 21 0f];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
timing@2 {
qcom,mdss-dsi-panel-phy-timings = [00 1f 08 07 18 22 08
08 08 08 02 04 1a 0d];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
timing@3 {
timing@2 {
qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 1f 06
06 06 06 02 04 13 0b];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
timing@4 {
timing@3 {
qcom,mdss-dsi-panel-phy-timings = [00 11 03 04 12 1e 04
04 04 03 02 04 0e 09];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
timing@5 {
timing@4 {
qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 10 1d 03
03 03 02 02 04 0c 08];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
timing@6 {
timing@5 {
qcom,mdss-dsi-panel-phy-timings = [00 0c 02 02 10 1c 03
03 03 02 02 04 0b 08];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
timing@7 {
timing@6 {
qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 0f 1c 02
02 02 02 02 04 0a 07];
qcom,display-topology = <2 2 1>;
@@ -644,6 +638,54 @@
};
};
&dsi_nt37801_amoled_fhd_plus_cmd {
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1";
qcom,esd-check-enabled;
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
qcom,mdss-dsi-panel-status-value = <0x9c>;
qcom,mdss-dsi-panel-status-read-length = <1>;
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a
0b 0a 02 04 00 21 0f];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
timing@1 {
qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07
06 06 07 02 04 16 0b];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
timing@2 {
qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07
06 06 07 02 04 16 0b];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
timing@3 {
qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07
06 06 07 02 04 16 0b];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
timing@4 {
qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07
06 06 07 02 04 16 0b];
qcom,display-topology = <2 2 1>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_ext_bridge_1080p {
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
qcom,mdss-dsi-display-timings {