From d9416335832c8fbf5d4a63e78c2337b5a7953361 Mon Sep 17 00:00:00 2001 From: "Bao D. Nguyen" Date: Fri, 16 Jun 2023 13:57:27 -0700 Subject: [PATCH] ARM: dts: qcom: add ufs support for Sun Add ufs support for Sun platforms. Change-Id: I4de4b9fb2235192735e1069efea6d246b7960d3f Signed-off-by: Bao D. Nguyen --- qcom/sun-rumi.dtsi | 50 +++++++++++++ qcom/sun.dtsi | 174 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 224 insertions(+) diff --git a/qcom/sun-rumi.dtsi b/qcom/sun-rumi.dtsi index a65905b5..3a737dd7 100644 --- a/qcom/sun-rumi.dtsi +++ b/qcom/sun-rumi.dtsi @@ -49,3 +49,53 @@ maximum-speed = "high-speed"; }; }; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qrbtc-sdm845"; + + /* VDDA_UFS_CORE */ + vdda-phy-supply = <&pm_v6j_l1>; + vdda-phy-max-microamp = <211000>; + + /* VDDA_UFS_0_1P2 */ + vdda-pll-supply = <&pm_v8g_l3>; + vdda-pll-max-microamp = <18300>; + + /* Phy GDSC for VDD_MX, always on */ + vdd-phy-gdsc-supply = <&gcc_ufs_mem_phy_gdsc>; + + /* Qref power supply, Refer Qref diagram */ + vdda-qref-supply = <&pm_v8i_l3>; + vdda-qref-max-microamp = <64500>; + + status = "ok"; +}; + +&ufshc_mem { + limit-tx-hs-gear = <1>; + limit-rx-hs-gear = <1>; + limit-rate = <2>; /* HS Rate-B */ + rpm-level = <0>; + spm-level = <0>; + + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + + vcc-supply = <&pm_humu_l17>; + vcc-max-microamp = <1300000>; + + vccq-supply = <&pm_v8d_l1>; + vccq-max-microamp = <750000>; + + qcom,vddp-ref-clk-supply = <&pm_v8i_l2>; + qcom,vddp-ref-clk-max-microamp = <100>; + + qcom,vccq-parent-supply = <&pm_v8i_s7>; + qcom,vccq-parent-max-microamp = <210000>; + + vdda-qref-supply = <&pm_v8i_l3>; + vdda-qref-max-microamp = <30000>; + + qcom,disable-lpm; + + status = "ok"; +}; diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index 6d587057..37f04182 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -33,6 +33,7 @@ aliases { serial0 = &qupv3_se7_2uart; + ufshc1 = &ufshc_mem; /* Embedded UFS Slot */ }; firmware: firmware { }; @@ -734,6 +735,179 @@ compatible = "arm,psci-1.0"; method = "smc"; }; + + ufsphy_mem: ufsphy_mem@1d80000 { + reg = <0x1d80000 0x2000>; + reg-names = "phy_mem"; + #phy-cells = <0>; + + lanes-per-direction = <2>; + clock-names = "ref_clk_src", + "ref_aux_clk", "qref_clk", + "rx_sym0_mux_clk", "rx_sym1_mux_clk", "tx_sym0_mux_clk", + "rx_sym0_phy_clk", "rx_sym1_phy_clk", "tx_sym0_phy_clk"; + clocks = <&rpmhcc RPMH_CXO_PAD_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&tcsrcc TCSR_UFS_CLKREF_EN>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>; + resets = <&ufshc_mem 0>; + status = "disabled"; + }; + + ice_cfg: shared_ice { + alg1 { + alg-name = "alg1"; + rx-alloc-percent = <60>; + status = "disabled"; + }; + + alg2 { + alg-name = "alg2"; + status = "disabled"; + + }; + + alg3 { + alg-name = "alg3"; + num-core = <28 28 15 13>; + status = "ok"; + }; + }; + + ufshc_mem: ufshc@1d84000 { + compatible = "qcom,ufshc"; + reg = <0x1d84000 0x3000>, + <0x1d88000 0x8000>, + <0x1d90000 0x9800>; + reg-names = "ufs_mem", "ufs_ice", "ufs_ice_hwkm"; + interrupts = ; + phys = <&ufsphy_mem>; + phy-names = "ufsphy"; + #reset-cells = <1>; + + lanes-per-direction = <2>; + dev-ref-clk-freq = <0>; /* 19.2 MHz */ + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&rpmhcc RPMH_LN_BB_CLK3>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + freq-table-hz = + <100000000 403000000>, + <0 0>, + <0 0>, + <100000000 403000000>, + <100000000 403000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + + interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>; + interconnect-names = "ufs-ddr", "cpu-ufs"; + + qcom,ufs-bus-bw,name = "ufshc_mem"; + qcom,ufs-bus-bw,num-cases = <30>; + qcom,ufs-bus-bw,num-paths = <2>; + qcom,ufs-bus-bw,vectors-KBps = + /* + * During HS G3 UFS runs at nominal voltage corner, vote + * higher bandwidth to push other buses in the data path + * to run at nominal to achieve max throughput. + * 4GBps pushes BIMC to run at nominal. + * 200MBps pushes CNOC to run at nominal. + * Vote for half of this bandwidth for HS G3 1-lane. + * For max bandwidth, vote high enough to push the buses + * to run in turbo voltage corner. + */ + <0 0>, <0 0>, /* No vote */ + <922 0>, <1000 0>, /* PWM G1 */ + <1844 0>, <1000 0>, /* PWM G2 */ + <3688 0>, <1000 0>, /* PWM G3 */ + <7376 0>, <1000 0>, /* PWM G4 */ + <14752 0>, <1000 0>, /* PWM G5 */ + <1844 0>, <1000 0>, /* PWM G1 L2 */ + <3688 0>, <1000 0>, /* PWM G2 L2 */ + <7376 0>, <1000 0>, /* PWM G3 L2 */ + <14752 0>, <1000 0>, /* PWM G4 L2 */ + <29504 0>, <1000 0>, /* PWM G5 L2 */ + <127796 0>, <1000 0>, /* HS G1 RA */ + <255591 0>, <1000 0>, /* HS G2 RA */ + <1492582 0>, <102400 0>, /* HS G3 RA */ + <2915200 0>, <204800 0>, /* HS G4 RA */ + <255591 0>, <1000 0>, /* HS G1 RA L2 */ + <511181 0>, <1000 0>, /* HS G2 RA L2 */ + <1492582 0>, <204800 0>, /* HS G3 RA L2 */ + <2915200 0>, <409600 0>, /* HS G4 RA L2 */ + <149422 0>, <1000 0>, /* HS G1 RB */ + <298189 0>, <1000 0>, /* HS G2 RB */ + <1492582 0>, <102400 0>, /* HS G3 RB */ + <2915200 0>, <204800 0>, /* HS G4 RB */ + <298189 0>, <1000 0>, /* HS G1 RB L2 */ + <596378 0>, <1000 0>, /* HS G2 RB L2 */ + /* As UFS working in HS G3 RB L2 mode, aggregated + * bandwidth (AB) should take care of providing + * optimum throughput requested. However, as tested, + * in order to scale up CNOC clock, instantaneous + * bindwidth (IB) needs to be given a proper value too. + */ + <1492582 0>, <204800 409600>, /* HS G3 RB L2 KBPs */ + <2915200 0>, <409600 409600>, /* HS G4 RB L2 */ + <5836800 0>, <819200 0>, /* HS G5 RA L2*/ + <5836800 0>, <819200 0>, /* HS G5 RB L2 */ + <7643136 0>, <819200 0>; /* Max. bandwidth */ + + qcom,bus-vector-names = "MIN", + "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", "PWM_G5_L1", + "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", "PWM_G5_L2", + "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1", + "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2", + "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1", + "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2", + "HS_RA_G5_L2", "HS_RB_G5_L2", + "MAX"; + + iommus = <&apps_smmu 0x60 0x0>; + shared-ice-cfg = <&ice_cfg>; + + qcom,bypass-pbl-rst-wa; + + status = "disabled"; + + qos0 { + mask = <0xfc>; + vote = <44>; + perf; + cpu_freq_vote = <2 5 7>; + }; + + qos1 { + mask = <0x03>; + vote = <44>; + cpu_freq_vote = <0>; + }; + }; }; &reserved_memory {