From af9ee05319547438b56573d290783e88595b1f4d Mon Sep 17 00:00:00 2001 From: Xubin Bai Date: Wed, 19 Jul 2023 02:02:55 -0700 Subject: [PATCH] ARM: dts: msm: Unstub dispcc for Sun Unstub the dispcc device so that it starts controlling HW. Change-Id: I548b5eb65c80032057877f15fa4abe0be42417e1 Signed-off-by: Xubin Bai --- qcom/sun.dtsi | 27 +++++++++++++++++++++++---- 1 file changed, 23 insertions(+), 4 deletions(-) diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index 97acaf44..245bdbb0 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -482,8 +482,17 @@ }; dispcc: clock-controller@af00000 { - compatible = "qcom,dummycc"; - clock-output-names = "dispcc_clocks"; + compatible = "qcom,sun-dispcc", "syscon"; + reg = <0xaf00000 0x20000>; + reg-name = "cc_base"; + vdd_mm-supply = <&VDD_MM_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <&gcc GCC_DISP_AHB_CLK>; + clock-names = "bi_tcxo", + "sleep_clk", + "iface"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -625,15 +634,25 @@ /* DISP_CC GDSCs */ disp_cc_mdss_core_gdsc: qcom,gdsc@af09000 { - compatible = "qcom,stub-regulator"; + compatible = "qcom,gdsc"; + reg = <0xaf09000 0x4>; regulator-name = "disp_cc_mdss_core_gdsc"; + parent-supply = <&VDD_MM_LEVEL>; + proxy-supply = <&disp_cc_mdss_core_gdsc>; + qcom,proxy-consumer-enable; + qcom,retain-regs; qcom,support-hw-trigger; + qcom,support-cfg-gdscr; }; disp_cc_mdss_core_int2_gdsc: qcom,gdsc@af0b000 { - compatible = "qcom,stub-regulator"; + compatible = "qcom,gdsc"; + reg = <0xaf0b000 0x4>; regulator-name = "disp_cc_mdss_core_int2_gdsc"; + parent-supply = <&VDD_MM_LEVEL>; + qcom,retain-regs; qcom,support-hw-trigger; + qcom,support-cfg-gdscr; }; /* EVA_CC GDSCs */