From d56825f5c411151d1516280c5e30d7797665bde5 Mon Sep 17 00:00:00 2001
From: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
Date: Fri, 10 Jan 2025 16:35:04 +0530
Subject: [PATCH] ARM: dts: msm: add disp_cc io to sde cesta

To enable and disable mdp clock gating functionality with
cesta immediate vote approach, add disp_cc_io memory to
sde cesta.

Change-Id: I2bd6d80269a69d870f2c8b4ff0b1bf8b1270aa6f
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
Signed-off-by: lnxdisplay <lnxdisplay@localhost>
---
 display/sun-sde.dtsi | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi
index f1e10426..ebb9dbbd 100644
--- a/display/sun-sde.dtsi
+++ b/display/sun-sde.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: BSD-3-Clause
 /*
- * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
@@ -222,8 +222,9 @@
 			<0xaf33000 0x30>,
 			<0xaf34000 0x30>,
 			<0xaf35000 0x30>,
-			<0xaf36000 0x30>;
-		reg-names = "rscc", "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5";
+			<0xaf36000 0x30>,
+			<0xaf0f000 0x10>;
+		reg-names = "rscc", "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5", "disp_cc";
 
 		clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
 				<&dispcc DISP_CC_MDSS_MDP_CLK_SRC>,