Merge "ARM: dts: msm: add sde_rscc register offset to cesta for sun target"

This commit is contained in:
QCTECMDR Service
2024-07-08 12:08:23 -07:00
committed by Gerrit - the friendly Code Review server
2 changed files with 5 additions and 3 deletions

View File

@@ -210,14 +210,15 @@
sde_cesta: qcom,sde_cesta@0x0af30000 {
cell-index = <0>;
compatible = "qcom,sde-cesta";
reg = <0xaf30000 0x60>,
reg = <0x0af20000 0x850>,
<0xaf30000 0x60>,
<0xaf31000 0x30>,
<0xaf32000 0x30>,
<0xaf33000 0x30>,
<0xaf34000 0x30>,
<0xaf35000 0x30>,
<0xaf36000 0x30>;
reg-names = "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5";
reg-names = "rscc", "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5";
clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK_SRC>;

View File

@@ -37,7 +37,8 @@
qcom,sde-vm-exclude-reg-names = "sid_phys";
qcom,tvm-include-reg = <0xaf30000 0x60>,
qcom,tvm-include-reg = <0x0af20000 0x850>,
<0xaf30000 0x60>,
<0xaf31000 0x30>,
<0xaf32000 0x30>,
<0xaf33000 0x30>,