From d310a153840d2489dae750b3d6de24fb5322882c Mon Sep 17 00:00:00 2001
From: Prem Sai Grandhi <quic_grandhir@quicinc.com>
Date: Thu, 16 Jan 2025 17:53:28 +0530
Subject: [PATCH] ARM: dts: msm: Add llcc perfmon node for kera SOC

Add llcc perfmon entry, qdss clock node to
llcc perfmon driver and aoss_qmp headers.

Change-Id: I34d57d4ab8ccb161a48ff7a89110ef67107d37a2
Signed-off-by: Prem Sai Grandhi <quic_grandhir@quicinc.com>
---
 qcom/kera.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi
index cbb612cc..60c6c9b0 100644
--- a/qcom/kera.dtsi
+++ b/qcom/kera.dtsi
@@ -19,6 +19,8 @@
 #include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
 #include <dt-bindings/spmi/spmi.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/power/qcom-aoss-qmp.h>
+#include <dt-bindings/clock/qcom,aop-qmp.h>
 
 / {
 	model = "Qualcomm Technologies, Inc. Kera";
@@ -1286,6 +1288,12 @@
 			"llcc_broadcast_or_base", "llcc_broadcast_and_base";
 		interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
 		cap-based-alloc-and-pwr-collapse;
+
+		llcc_perfmon {
+			compatible = "qcom,llcc-perfmon";
+			clocks = <&aoss_qmp QDSS_CLK>;
+			clock-names = "qdss_clk";
+		};
 	};
 
 	gic-interrupt-router {