From 40c568a6d182095de26452c239be8bf3b0c88aea Mon Sep 17 00:00:00 2001 From: Kamal Agrawal Date: Sat, 3 Feb 2024 16:22:37 +0530 Subject: [PATCH] ARM: dts: msm: Update DDR bandwidth for sun GMU scaling SVS is the highest voltage corner for GMU. The lowest DDR BW that puts CX at SVS corner is 1555 MHz. This DDR vote puts CX at a corner high enough such that GMU can run at 650 MHz. This is to get better GMU performance at no extra power cost. Change-Id: I919476577e9b2e69161142c93d47e91505ffc222 Signed-off-by: Kamal Agrawal --- gpu/sun-gpu.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gpu/sun-gpu.dtsi b/gpu/sun-gpu.dtsi index 46db9ce5..9d7d3cb1 100644 --- a/gpu/sun-gpu.dtsi +++ b/gpu/sun-gpu.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024)) @@ -171,7 +171,7 @@ qcom,gmu-freq-table = <500000000 RPMH_REGULATOR_LEVEL_LOW_SVS>, <650000000 RPMH_REGULATOR_LEVEL_SVS>; - qcom,gmu-perf-ddr-bw = ; + qcom,gmu-perf-ddr-bw = ; iommus = <&kgsl_smmu 0x5 0x000>; qcom,iommu-dma = "disabled";