diff --git a/display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi b/display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi
index aad5198e..5d19e90e 100644
--- a/display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi
+++ b/display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi
@@ -38,6 +38,11 @@
 		qcom,mdss-dsi-te-check-enable;
 		qcom,mdss-dsi-te-using-te-pin;
 		qcom,spr-pack-type = "pentile";
+		qcom,mdss-dsi-panel-hdr-enabled;
+		qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250
+			15700 12250 35800 6750 2550>;
+		qcom,mdss-dsi-panel-peak-brightness = <13000000>;
+		qcom,mdss-dsi-panel-blackness-level = <10>;
 		qcom,mdss-dsi-display-timings {
 			timing@0 {
 				cell-index = <0>;
@@ -56,6 +61,7 @@
 				qcom,mdss-dsi-v-top-border = <0>;
 				qcom,mdss-dsi-v-bottom-border = <0>;
 				qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
+				qcom,mdss-dsi-panel-clockrate = <1223800000>;
 
 				qcom,mdss-dsi-on-command = [
 					39 01 00 00 00 00 06 f0 55 aa 52 08 01
diff --git a/display/dsi-panel-nt37801-dsc-10bit-video.dtsi b/display/dsi-panel-nt37801-dsc-10bit-video.dtsi
index 79524689..010d6f73 100644
--- a/display/dsi-panel-nt37801-dsc-10bit-video.dtsi
+++ b/display/dsi-panel-nt37801-dsc-10bit-video.dtsi
@@ -31,6 +31,11 @@
 		qcom,mdss-dsi-wr-mem-start = <0x2c>;
 		qcom,mdss-dsi-wr-mem-continue = <0x3c>;
 		qcom,spr-pack-type = "pentile";
+		qcom,mdss-dsi-panel-hdr-enabled;
+		qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250
+			15700 12250 35800 6750 2550>;
+		qcom,mdss-dsi-panel-peak-brightness = <13000000>;
+		qcom,mdss-dsi-panel-blackness-level = <10>;
 		qcom,mdss-dsi-display-timings {
 			timing@0 {
 				cell-index = <0>;
diff --git a/display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi b/display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi
index e1c2f792..84dfd229 100644
--- a/display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi
+++ b/display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi
@@ -40,6 +40,11 @@
 		qcom,mdss-dsi-te-check-enable;
 		qcom,mdss-dsi-te-using-te-pin;
 		qcom,spr-pack-type = "pentile";
+		qcom,mdss-dsi-panel-hdr-enabled;
+		qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250
+			15700 12250 35800 6750 2550>;
+		qcom,mdss-dsi-panel-peak-brightness = <13000000>;
+		qcom,mdss-dsi-panel-blackness-level = <10>;
 		qcom,mdss-dsi-display-timings {
 			timing@0 {
 				cell-index = <0>;
diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi
index fc12f0d7..29afd64e 100644
--- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi
+++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi
@@ -51,7 +51,12 @@
 		 * # R B R B ...     B R B R ...      R B R B ...     B R B R ...
 		 * ###############################################################
 		 */
-		qcom,spr-pentile-pack-type = "RG-BG Type A";
+		qcom,spr-pentile-pack-type = "BG-RG Type B";
+		qcom,mdss-dsi-panel-hdr-enabled;
+		qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250
+			15700 12250 35800 6750 2550>;
+		qcom,mdss-dsi-panel-peak-brightness = <13000000>;
+		qcom,mdss-dsi-panel-blackness-level = <10>;
 
 		qcom,mdss-dsi-display-timings {
 			timing@0 {
diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi
index 7b969aa8..a23f1478 100644
--- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi
+++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi
@@ -40,6 +40,11 @@
 		qcom,mdss-dsi-te-check-enable;
 		qcom,mdss-dsi-te-using-te-pin;
 		qcom,spr-pack-type = "pentile";
+		qcom,mdss-dsi-panel-hdr-enabled;
+		qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250
+			15700 12250 35800 6750 2550>;
+		qcom,mdss-dsi-panel-peak-brightness = <13000000>;
+		qcom,mdss-dsi-panel-blackness-level = <10>;
 		qcom,mdss-dsi-display-timings {
 			timing@0 {
 				cell-index = <0>;
diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi
index 4ebc8416..08e9b8b7 100644
--- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi
+++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi
@@ -40,6 +40,25 @@
 		qcom,mdss-dsi-te-check-enable;
 		qcom,mdss-dsi-te-using-te-pin;
 		qcom,spr-pack-type = "pentile";
+		/*
+		 * ###############################################################
+		 * # Pentile SPR phases for SM8750 and later
+		 * ###############################################################
+		 * # RG/BG Type A    BG/RG Type A    GR/GB Type A    GB/GR Type A
+		 * # R B R B ...     B R B R ...      R B R B ...     B R B R ...
+		 * #  G G G G ...     G G G G ...    G G G G ...     G G G G ...
+		 * #
+		 * # RG/BG Type B    BG/RG Type B    GR/GB Type B    GB/GR Type B
+		 * #  G G G G ...     G G G G ...    G G G G ...     G G G G ...
+		 * # R B R B ...     B R B R ...      R B R B ...     B R B R ...
+		 * ###############################################################
+		 */
+		qcom,spr-pentile-pack-type = "BG-RG Type B";
+		qcom,mdss-dsi-panel-hdr-enabled;
+		qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250
+			15700 12250 35800 6750 2550>;
+		qcom,mdss-dsi-panel-peak-brightness = <13000000>;
+		qcom,mdss-dsi-panel-blackness-level = <10>;
 		qcom,mdss-dsi-display-timings {
 			timing@0 {
 				cell-index = <0>;
diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi
index 1d5cf4e7..5f34e53e 100644
--- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi
+++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi
@@ -53,7 +53,12 @@
 		 * # R B R B ...     B R B R ...      R B R B ...     B R B R ...
 		 * ###############################################################
 		 */
-		qcom,spr-pentile-pack-type = "RG-BG Type A";
+		qcom,spr-pentile-pack-type = "BG-RG Type B";
+		qcom,mdss-dsi-panel-hdr-enabled;
+		qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250
+			15700 12250 35800 6750 2550>;
+		qcom,mdss-dsi-panel-peak-brightness = <13000000>;
+		qcom,mdss-dsi-panel-blackness-level = <10>;
 		qcom,mdss-dsi-display-timings {
 			timing@0 {
 				cell-index = <0>;
diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi
index dd6127df..26b49ed2 100644
--- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi
+++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi
@@ -41,7 +41,12 @@
 		 * # R B R B ...     B R B R ...      R B R B ...     B R B R ...
 		 * ###############################################################
 		 */
-		qcom,spr-pentile-pack-type = "RG-BG Type A";
+		qcom,spr-pentile-pack-type = "BG-RG Type B";
+		qcom,mdss-dsi-panel-hdr-enabled;
+		qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250
+			15700 12250 35800 6750 2550>;
+		qcom,mdss-dsi-panel-peak-brightness = <13000000>;
+		qcom,mdss-dsi-panel-blackness-level = <10>;
 
 		qcom,mdss-dsi-wr-mem-start = <0x2c>;
 		qcom,mdss-dsi-wr-mem-continue = <0x3c>;
diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi
index 71f33306..f94d9550 100644
--- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi
+++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi
@@ -33,6 +33,11 @@
 		qcom,mdss-dsi-wr-mem-start = <0x2c>;
 		qcom,mdss-dsi-wr-mem-continue = <0x3c>;
 		qcom,spr-pack-type = "pentile";
+		qcom,mdss-dsi-panel-hdr-enabled;
+		qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250
+			15700 12250 35800 6750 2550>;
+		qcom,mdss-dsi-panel-peak-brightness = <13000000>;
+		qcom,mdss-dsi-panel-blackness-level = <10>;
 		qcom,mdss-dsi-display-timings {
 			timing@0 {
 				cell-index = <0>;
diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi
index 461591aa..21e44730 100644
--- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi
+++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi
@@ -33,6 +33,25 @@
 		qcom,mdss-dsi-wr-mem-start = <0x2c>;
 		qcom,mdss-dsi-wr-mem-continue = <0x3c>;
 		qcom,spr-pack-type = "pentile";
+		/*
+		 * ###############################################################
+		 * # Pentile SPR phases for SM8750 and later
+		 * ###############################################################
+		 * # RG/BG Type A    BG/RG Type A    GR/GB Type A    GB/GR Type A
+		 * # R B R B ...     B R B R ...      R B R B ...     B R B R ...
+		 * #  G G G G ...     G G G G ...    G G G G ...     G G G G ...
+		 * #
+		 * # RG/BG Type B    BG/RG Type B    GR/GB Type B    GB/GR Type B
+		 * #  G G G G ...     G G G G ...    G G G G ...     G G G G ...
+		 * # R B R B ...     B R B R ...      R B R B ...     B R B R ...
+		 * ###############################################################
+		 */
+		qcom,spr-pentile-pack-type = "BG-RG Type B";
+		qcom,mdss-dsi-panel-hdr-enabled;
+		qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250
+			15700 12250 35800 6750 2550>;
+		qcom,mdss-dsi-panel-peak-brightness = <13000000>;
+		qcom,mdss-dsi-panel-blackness-level = <10>;
 		qcom,mdss-dsi-display-timings {
 			timing@0 {
 				cell-index = <0>;
diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi
index fe387ae4..64d790cd 100644
--- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi
+++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi
@@ -46,7 +46,12 @@
 		 * # R B R B ...     B R B R ...      R B R B ...     B R B R ...
 		 * ###############################################################
 		 */
-		qcom,spr-pentile-pack-type = "RG-BG Type A";
+		qcom,spr-pentile-pack-type = "BG-RG Type B";
+		qcom,mdss-dsi-panel-hdr-enabled;
+		qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250
+			15700 12250 35800 6750 2550>;
+		qcom,mdss-dsi-panel-peak-brightness = <13000000>;
+		qcom,mdss-dsi-panel-blackness-level = <10>;
 		qcom,mdss-dsi-display-timings {
 			timing@0 {
 				cell-index = <0>;
diff --git a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi
index b90133b6..3384bf40 100644
--- a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi
+++ b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi
@@ -40,6 +40,11 @@
 		qcom,spr-pack-type = "pentile";
 		qcom,qsync-enable;
 		qcom,mdss-dsi-qsync-min-refresh-rate = <60>;
+		qcom,mdss-dsi-panel-hdr-enabled;
+		qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250
+			15700 12250 35800 6750 2550>;
+		qcom,mdss-dsi-panel-peak-brightness = <13000000>;
+		qcom,mdss-dsi-panel-blackness-level = <10>;
 		qcom,mdss-dsi-display-timings {
 			timing@0 {
 				cell-index = <0>;
diff --git a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi
index c665564d..5a534706 100644
--- a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi
+++ b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi
@@ -42,6 +42,11 @@
 		qcom,spr-pack-type = "pentile";
 		qcom,qsync-enable;
 		qcom,mdss-dsi-qsync-min-refresh-rate = <60>;
+		qcom,mdss-dsi-panel-hdr-enabled;
+		qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250
+			15700 12250 35800 6750 2550>;
+		qcom,mdss-dsi-panel-peak-brightness = <13000000>;
+		qcom,mdss-dsi-panel-blackness-level = <10>;
 		qcom,mdss-dsi-display-timings {
 			timing@0 {
 				cell-index = <0>;
diff --git a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi
index 4992feb5..7840c1c2 100644
--- a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi
+++ b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi
@@ -28,6 +28,11 @@
 		qcom,adjust-timer-wakeup-ms = <1>;
 		qcom,panel-cphy-mode;
 		qcom,spr-pack-type = "pentile";
+		qcom,mdss-dsi-panel-hdr-enabled;
+		qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250
+			15700 12250 35800 6750 2550>;
+		qcom,mdss-dsi-panel-peak-brightness = <13000000>;
+		qcom,mdss-dsi-panel-blackness-level = <10>;
 
 		qcom,mdss-dsi-wr-mem-start = <0x2c>;
 		qcom,mdss-dsi-wr-mem-continue = <0x3c>;
diff --git a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi
index 061be26c..93fd3234 100644
--- a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi
+++ b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi
@@ -35,6 +35,11 @@
 		qcom,spr-pack-type = "pentile";
 		qcom,qsync-enable;
 		qcom,mdss-dsi-qsync-min-refresh-rate = <80>;
+		qcom,mdss-dsi-panel-hdr-enabled;
+		qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250
+			15700 12250 35800 6750 2550>;
+		qcom,mdss-dsi-panel-peak-brightness = <13000000>;
+		qcom,mdss-dsi-panel-blackness-level = <10>;
 		qcom,mdss-dsi-display-timings {
 			timing@0 {
 				cell-index = <0>;
diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi
index 7e0b89cc..8a68f314 100644
--- a/display/sun-sde-common.dtsi
+++ b/display/sun-sde-common.dtsi
@@ -259,6 +259,7 @@
 
 		qcom,sde-cdp-setting = <1 1>, <1 0>;
 
+		qcom,sde-qos-cpu-mask = <0x3>;
 		qcom,sde-qos-cpu-mask-performance = <0x3>;
 		qcom,sde-qos-cpu-dma-latency = <300>;
 		qcom,sde-qos-cpu-irq-latency = <300>;
diff --git a/display/sun-sde-display-cdp.dtsi b/display/sun-sde-display-cdp.dtsi
index 2049962d..b2dd5503 100644
--- a/display/sun-sde-display-cdp.dtsi
+++ b/display/sun-sde-display-cdp.dtsi
@@ -307,6 +307,13 @@
 			&dsi_nt37801_amoled_video
 			&dsi_nt37801_amoled_video_cphy
 			&dsi_nt37801_amoled_cmd_spr
-			&dsi_nt37801_amoled_vid_spr>;
+			&dsi_nt37801_amoled_vid_spr
+			&dsi_nt37801_amoled_dsc_10b_cmd
+			&dsi_nt37801_amoled_dsc_10b_video
+			&dsi_nt37801_amoled_qsync_cmd
+			&dsi_nt37801_amoled_qsync_video
+			&dsi_nt37801_amoled_fhd_plus_cmd
+			&dsi_nt37801_amoled_cmd_ddicspr
+			&dsi_nt37801_amoled_video_ddicspr>;
 	};
 };
diff --git a/display/sun-sde-display-mtp.dtsi b/display/sun-sde-display-mtp.dtsi
index baa362b2..b62cf120 100644
--- a/display/sun-sde-display-mtp.dtsi
+++ b/display/sun-sde-display-mtp.dtsi
@@ -289,5 +289,12 @@
 				&dsi_nt37801_amoled_video
 				&dsi_nt37801_amoled_video_cphy
 				&dsi_nt37801_amoled_cmd_spr
-				&dsi_nt37801_amoled_vid_spr>;
+				&dsi_nt37801_amoled_vid_spr
+				&dsi_nt37801_amoled_dsc_10b_cmd
+				&dsi_nt37801_amoled_dsc_10b_video
+				&dsi_nt37801_amoled_qsync_cmd
+				&dsi_nt37801_amoled_qsync_video
+				&dsi_nt37801_amoled_fhd_plus_cmd
+				&dsi_nt37801_amoled_cmd_ddicspr
+				&dsi_nt37801_amoled_video_ddicspr>;
 };
diff --git a/display/sun-sde-display-qrd.dtsi b/display/sun-sde-display-qrd.dtsi
index c1339749..2e91032c 100644
--- a/display/sun-sde-display-qrd.dtsi
+++ b/display/sun-sde-display-qrd.dtsi
@@ -230,5 +230,7 @@
 	qcom,display-panels = <&dsi_nt37801_amoled_cmd
 				&dsi_nt37801_amoled_cmd_cphy
 				&dsi_nt37801_amoled_video
-				&dsi_nt37801_amoled_video_cphy>;
+				&dsi_nt37801_amoled_video_cphy
+				&dsi_nt37801_amoled_qsync_cmd_cphy
+				&dsi_nt37801_amoled_qsync_video_cphy>;
 };
diff --git a/display/sun-sde-display.dtsi b/display/sun-sde-display.dtsi
index c779d0fd..a1a671ef 100644
--- a/display/sun-sde-display.dtsi
+++ b/display/sun-sde-display.dtsi
@@ -24,12 +24,16 @@
 		compatible = "qcom,wb-display";
 		cell-index = <0>;
 		label = "wb_display1";
+		clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
+		clock-names = "mdp_core_clk";
 	};
 
 	sde_wb2: qcom,wb-display@2 {
 		compatible = "qcom,wb-display";
 		cell-index = <1>;
 		label = "wb_display2";
+		clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
+		clock-names = "mdp_core_clk";
 	};
 
 
@@ -92,10 +96,17 @@
 		  * MDP clock nodes, no actual vote shall be added and this
 		  * change is done just to satisfy sync state requirements.
 		  */
-		 <&dispcc DISP_CC_MDSS_MDP_CLK>;
+		 <&dispcc DISP_CC_MDSS_MDP_CLK>,
+		 /*
+		  * The esync clk RCG is only necessary here to set its parent
+		  * to the pll dsi clk, which also needs to be available at the
+		  * point that its known whether the clock will be used. After
+		  * updating the parent, this clock handle is no longer needed.
+		  */
+		 <&dispcc DISP_CC_ESYNC0_CLK_SRC>;
 	clock-names = "pll_byte_clk0", "pll_dsi_clk0",
 		      "pll_byte_clk1", "pll_dsi_clk1",
-		      "mdp_core_clk";
+		      "mdp_core_clk", "esync_clk_rcg";
 	vddio-supply = <&L12B>;
 	vci-supply = <&L13B>;
 	vdd-supply = <&L11B>;
@@ -121,10 +132,17 @@
 		  * MDP clock nodes, no actual vote shall be added and this
 		  * change is done just to satisfy sync state requirements.
 		  */
-		 <&dispcc DISP_CC_MDSS_MDP_CLK>;
+		 <&dispcc DISP_CC_MDSS_MDP_CLK>,
+		 /*
+		  * The esync clk RCG is only necessary here to set its parent
+		  * to the pll dsi clk, which also needs to be available at the
+		  * point that its known whether the clock will be used. After
+		  * updating the parent, this clock handle is no longer needed.
+		  */
+		 <&dispcc DISP_CC_ESYNC1_CLK_SRC>;
 	clock-names = "pll_byte_clk0", "pll_dsi_clk0",
 		      "pll_byte_clk1", "pll_dsi_clk1",
-		      "mdp_core_clk";
+		      "mdp_core_clk", "esync_clk_rcg";
 	vddio-supply = <&L12B>;
 	vci-supply = <&L13B>;
 	vdd-supply = <&L11B>;
diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi
index f0d8064c..29503362 100644
--- a/display/sun-sde.dtsi
+++ b/display/sun-sde.dtsi
@@ -197,6 +197,8 @@
 		qcom,iommu-faults = "non-fatal";
 		qcom,iommu-earlymap; /* for cont-splash */
 		dma-coherent;
+		clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
+		clock-names = "mdp_core_clk";
 	};
 
 	smmu_sde_sec: qcom,smmu_sde_sec_cb {
@@ -205,6 +207,8 @@
 		memory-region = <&smmu_sde_iommu_region_partition>;
 		qcom,iommu-faults = "non-fatal";
 		qcom,iommu-vmid = <0xa>;
+		clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
+		clock-names = "mdp_core_clk";
 	};
 
 	sde_cesta: qcom,sde_cesta@0x0af30000 {
@@ -313,15 +317,13 @@
 		<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
 		<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
 		<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
-		<&mdss_dsi_phy0 1>,
 		<&dispcc DISP_CC_ESYNC0_CLK>,
-		<&dispcc DISP_CC_ESYNC0_CLK_SRC>,
 		<&dispcc DISP_CC_OSC_CLK>,
 		<&dispcc DISP_CC_MDSS_ESC0_CLK>,
 		<&rpmhcc RPMH_CXO_CLK>;
 	clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
-			"pixel_clk", "pixel_clk_rcg", "pll_dsi_clk",
-			"esync_clk", "esync_clk_rcg", "osc_clk", "esc_clk", "xo";
+			"pixel_clk", "pixel_clk_rcg", "esync_clk", "osc_clk",
+			"esc_clk", "xo";
 };
 
 &mdss_dsi1 {
@@ -332,15 +334,13 @@
 		<&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
 		<&dispcc DISP_CC_MDSS_PCLK1_CLK>,
 		<&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>,
-		<&mdss_dsi_phy1 1>,
 		<&dispcc DISP_CC_ESYNC1_CLK>,
-		<&dispcc DISP_CC_ESYNC1_CLK_SRC>,
 		<&dispcc DISP_CC_OSC_CLK>,
 		<&dispcc DISP_CC_MDSS_ESC1_CLK>,
 		<&rpmhcc RPMH_CXO_CLK>;
 	clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
-			"pixel_clk", "pixel_clk_rcg", "pll_dsi_clk",
-			"esync_clk", "esync_clk_rcg", "osc_clk", "esc_clk", "xo";
+			"pixel_clk", "pixel_clk_rcg", "esync_clk", "osc_clk",
+			"esc_clk", "xo";
 };
 
 &mdss_dsi_phy0 {