From cef56baa85275d3ee0356ed2f890bb9f89de46da Mon Sep 17 00:00:00 2001
From: Prasanna S <quic_prass@quicinc.com>
Date: Thu, 25 May 2023 11:28:19 +0530
Subject: [PATCH] ARM: dts: msm: Add QUPv3 UART console node for sun

Enable console support on sun.

Change-Id: If6c1b2a81e2e18bbfee793c9188afb82dcf6f596
Signed-off-by: Prasanna S <quic_prass@quicinc.com>
---
 qcom/sun-pinctrl.dtsi | 39 +++++++++++++++++++++++++++++++++++++++
 qcom/sun-qupv3.dtsi   | 33 +++++++++++++++++++++++++++++++++
 qcom/sun-rumi.dtsi    |  4 ++++
 qcom/sun.dtsi         |  9 ++++++++-
 4 files changed, 84 insertions(+), 1 deletion(-)
 create mode 100644 qcom/sun-qupv3.dtsi

diff --git a/qcom/sun-pinctrl.dtsi b/qcom/sun-pinctrl.dtsi
index 11ea4f47..fd1f8a7f 100644
--- a/qcom/sun-pinctrl.dtsi
+++ b/qcom/sun-pinctrl.dtsi
@@ -4,5 +4,44 @@
  */
 
 &tlmm {
+	qupv3_se7_2uart_pins: qupv3_se7_2uart_pins {
+		qupv3_se7_2uart_tx_active: qupv3_se7_2uart_tx_active {
+			mux {
+				pins = "gpio62";
+				function = "qup1_se7_l2";
+			};
 
+			config {
+				pins = "gpio62";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se7_2uart_rx_active: qupv3_se7_2uart_rx_active {
+			mux {
+				pins = "gpio63";
+				function = "qup1_se7_l3";
+			};
+
+			config {
+				pins = "gpio63";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se7_2uart_sleep: qupv3_se7_2uart_sleep {
+			mux {
+				pins = "gpio62", "gpio63";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio62", "gpio63";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+		};
+	};
 };
diff --git a/qcom/sun-qupv3.dtsi b/qcom/sun-qupv3.dtsi
new file mode 100644
index 00000000..7a81d7c2
--- /dev/null
+++ b/qcom/sun-qupv3.dtsi
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+&soc {
+	/* QUPv3_1 Wrapper Instance */
+	qupv3_1: qcom,qupv3_1_geni_se@AC0000 {
+		compatible = "qcom,geni-se-qup";
+		reg = <0xAC0000 0x2000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		clock-names = "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		ranges;
+		status = "ok";
+
+		/* Debug UART Instance */
+		qupv3_se7_2uart: qcom,qup_uart@A9C000 {
+			compatible = "qcom,geni-debug-uart";
+			reg = <0xA9C000 0x4000>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se7_2uart_tx_active>, <&qupv3_se7_2uart_rx_active>;
+			pinctrl-1 = <&qupv3_se7_2uart_sleep>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/qcom/sun-rumi.dtsi b/qcom/sun-rumi.dtsi
index 104b0371..485d3902 100644
--- a/qcom/sun-rumi.dtsi
+++ b/qcom/sun-rumi.dtsi
@@ -17,3 +17,7 @@
 &memtimer {
 	clock-frequency = <192000>;
 };
+
+&qupv3_se7_2uart {
+	qcom,rumi_platform;
+};
diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi
index 866b2571..a2d608c2 100644
--- a/qcom/sun.dtsi
+++ b/qcom/sun.dtsi
@@ -30,7 +30,9 @@
 		bootargs = "nokaslr kpti=0 log_buf_len=256K swiotlb=0 loop.max_part=7";
 	};
 
-	aliases { };
+	aliases {
+		serial0 = &qupv3_se7_2uart;
+	};
 
 	firmware: firmware { };
 
@@ -847,3 +849,8 @@
 #include "msm-arm-smmu-sun.dtsi"
 #include "sun-pinctrl.dtsi"
 #include "sun-regulators.dtsi"
+#include "sun-qupv3.dtsi"
+
+&qupv3_se7_2uart {
+	status = "ok";
+};