diff --git a/Kbuild b/Kbuild
index 762643b2..e80ba254 100644
--- a/Kbuild
+++ b/Kbuild
@@ -1,7 +1,19 @@
 dtbo-$(CONFIG_ARCH_SUN) += display/sun-sde.dtbo \
 		display/sun-sde-display-cdp-overlay.dtbo \
 		display/sun-sde-display-mtp-overlay.dtbo \
-		display/sun-sde-display-rumi-overlay.dtbo
+		display/sun-sde-display-rumi-overlay.dtbo \
+		display/sun-sde-display-rcm-overlay.dtbo \
+		display/sun-sde-display-qrd-sku1-overlay.dtbo \
+		display/sun-sde-display-qrd-sku1-v8-overlay.dtbo \
+		display/sun-sde-display-qrd-sku2-v8-overlay.dtbo \
+		display/sun-sde-display-cdp-kiwi-overlay.dtbo \
+		display/sun-sde-display-mtp-kiwi-overlay.dtbo \
+		display/sun-sde-display-cdp-kiwi-v8-overlay.dtbo \
+		display/sun-sde-display-mtp-kiwi-v8-overlay.dtbo \
+		display/sun-sde-display-cdp-nfc-overlay.dtbo \
+		display/sun-sde-display-mtp-nfc-overlay.dtbo \
+		display/sun-sde-display-cdp-v8-overlay.dtbo \
+		display/sun-sde-display-mtp-v8-overlay.dtbo
 
 always-y    := $(dtb-y) $(dtbo-y)
 subdir-y    := $(dts-dirs)
diff --git a/bindings/sde.txt b/bindings/sde.txt
index c088ece5..2abbe5a5 100644
--- a/bindings/sde.txt
+++ b/bindings/sde.txt
@@ -387,6 +387,31 @@ Optional properties:
                 corresponding DSPP block offset as base.
 - qcom,sde-dspp-demura-size:    A u32 value indicating the demura block register address range
 - qcom,sde-dspp-demura-version:    A u32 value indicating the version of demura hardware.
+- qcom,sde-dspp-aiqe-off:	Array of u32 values indicating the offset of each AIQE block
+				relative to its parent DSPP block.
+- qcom,sde-dspp-aiqe-version:   A u32 value indicating the version of the AIQE hardware.
+- qcom,sde-dspp-aiqe-size:      A u32 value indicating the shared memory size of each AIQE
+				hardware block instance.
+- qcom,sde-dspp-aiqe-dither-off: Array of u32 values indicating the offset of each AIQE
+				dither block relative to its parent DSPP block.
+- qcom,sde-dspp-aiqe-dither-version: A u32 value indicating the version of the AIQE dither
+				hardware.
+- qcom,sde-dspp-aiqe-dither-size: A u32 value indicating the shared memory size of each AIQE
+				dither hardware block instance.
+- qcom,sde-dspp-aiqe-wrapper-off: Array of u32 values indicating the offset of each AIQE
+				wrapper block relative to its parent DSPP block.
+- qcom,sde-dspp-aiqe-wrapper-version: A u32 value indicating the version of the AIQE wrapper
+				hardware.
+- qcom,sde-dspp-aiqe-wrapper-size: A u32 value indicating the shared memory size of each AIQE
+				wrapper hardware block instance.
+- qcom,sde-aiqe-has-feature-mdnie:	Boolean property indicating the presence of AIQE feature mDNIe
+				hardware.
+- qcom,sde-aiqe-has-feature-abc:	Boolean property indicating the presence of AIQE feature ABC
+				hardware.
+- qcom,sde-aiqe-has-feature-ssrc:	Boolean property indicating the presence of AIQE feature SSRC
+				hardware.
+- qcom,sde-aiqe-has-feature-copr:	Boolean property indicating the presence of AIQE feature COPR
+				hardware.
 - qcom,sde-lm-noise-off:	A u32 value indicating noise layer offset from mixer base.
 - qcom,sde-lm-noise-version:	A u32 value indicating the noise layer version.
 - qcom,sde-vbif-id:		Array of vbif ids corresponding to the
@@ -710,6 +735,23 @@ Example:
     qcom,sde-lm-noise-off = <0x320>;
     qcom,sde-lm-noise-version = <0x00010000>;
 
+    qcom,sde-dspp-aiqe-off = <0x39000 0xffffffff 0x3a000 0xffffffff>;
+    qcom,sde-dspp-aiqe-version = <0x00010000>;
+    qcom,sde-dspp-aiqe-size = <0x3fc>;
+
+    qcom,sde-dspp-aiqe-dither-off = <0x39700 0xffffffff 0x3a700 0xffffffff>;
+    qcom,sde-dspp-aiqe-dither-version = <0x00010000>;
+    qcom,sde-dspp-aiqe-dither-size = <0x20>;
+
+    qcom,sde-dspp-aiqe-wrapper-off = <0x39780 0xffffffff 0x3a780 0xffffffff>;
+    qcom,sde-dspp-aiqe-wrapper-version = <0x00010000>;
+    qcom,sde-dspp-aiqe-wrapper-size = <0x1c>;
+
+    qcom,sde-aiqe-has-feature-mdnie;
+    qcom,sde-aiqe-has-feature-abc;
+    qcom,sde-aiqe-has-feature-ssrc;
+    qcom,sde-aiqe-has-feature-copr;
+
     qcom,sde-dspp-rc-mem-size = <2720>;
     qcom,sde-dest-scaler-top-off = <0x00061000>;
     qcom,sde-dest-scaler-off = <0x800 0x1000>;
diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi
index eacca56f..5612ec26 100644
--- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi
+++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi
@@ -32,6 +32,7 @@
 		qcom,mdss-dsi-te-check-enable;
 		qcom,mdss-dsi-te-using-te-pin;
 		qcom,panel-cphy-mode;
+		qcom,spr-pack-type = "pentile";
 
 		qcom,mdss-dsi-display-timings {
 			timing@0 {
@@ -87,6 +88,8 @@
 					39 01 00 00 00 00 05 FF AA 55 A5 82
 					39 01 00 00 00 00 02 6F 08
 					39 01 00 00 00 00 03 F3 CC 0C
+					39 01 00 00 00 00 06 F0 55 AA 52 08 01
+					39 01 00 00 00 00 05 B2 55 01 FF 03
 					05 01 00 00 78 00 01 11
 					05 01 00 00 14 00 01 29
 				];
diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi
index 92004657..e417cdb2 100644
--- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi
+++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi
@@ -13,6 +13,8 @@
 
 		qcom,dsi-ctrl-num = <0>;
 		qcom,dsi-phy-num = <0>;
+		qcom,dsi-sec-ctrl-num = <1>;
+		qcom,dsi-sec-phy-num = <1>;
 
 		qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
 		qcom,mdss-dsi-lane-map = "lane_map_0123";
@@ -32,6 +34,7 @@
 		qcom,mdss-dsi-te-dcs-command = <1>;
 		qcom,mdss-dsi-te-check-enable;
 		qcom,mdss-dsi-te-using-te-pin;
+		qcom,spr-pack-type = "pentile";
 		qcom,mdss-dsi-display-timings {
 			timing@0 {
 				cell-index = <0>;
@@ -51,6 +54,12 @@
 				qcom,mdss-dsi-v-bottom-border = <0>;
 				qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
 
+				qcom,mdss-dsi-timing-switch-command = [
+					39 01 00 00 00 00 05 2A 00 00 05 9F
+					39 01 00 00 00 00 05 2B 00 00 0C 7F
+					39 01 00 00 00 00 02 8F 00
+				];
+
 				qcom,mdss-dsi-on-command = [
 					39 01 00 00 00 00 06 F0 55 AA 52 08 01
 					39 01 00 00 00 00 02 6F 01
@@ -83,6 +92,8 @@
 					39 01 00 00 00 00 02 9C 01
 					05 01 00 00 00 00 01 2C
 					39 01 00 00 00 00 02 2F 00
+					39 01 00 00 00 00 06 F0 55 AA 52 08 01
+					39 01 00 00 00 00 05 B2 55 01 FF 03
 					05 01 00 00 78 00 01 11
 					05 01 00 00 14 00 01 29
 				];
@@ -103,6 +114,85 @@
 				qcom,mdss-dsc-bit-per-pixel = <8>;
 				qcom,mdss-dsc-block-prediction-enable;
 			};
+
+			timing@1 {
+				cell-index = <1>;
+				qcom,mdss-dsi-panel-framerate = <120>;
+				qcom,mdss-dsi-panel-width = <1080>;
+				qcom,mdss-dsi-panel-height = <2400>;
+				qcom,mdss-dsi-h-front-porch = <20>;
+				qcom,mdss-dsi-h-back-porch = <20>;
+				qcom,mdss-dsi-h-pulse-width = <4>;
+				qcom,mdss-dsi-h-sync-skew = <0>;
+				qcom,mdss-dsi-v-back-porch = <18>;
+				qcom,mdss-dsi-v-front-porch = <20>;
+				qcom,mdss-dsi-v-pulse-width = <2>;
+				qcom,mdss-dsi-h-left-border = <0>;
+				qcom,mdss-dsi-h-right-border = <0>;
+				qcom,mdss-dsi-v-top-border = <0>;
+				qcom,mdss-dsi-v-bottom-border = <0>;
+				qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
+
+				qcom,mdss-dsi-timing-switch-command = [
+					39 01 00 00 00 00 05 2A 00 00 04 37
+					39 01 00 00 00 00 05 2B 00 00 09 5F
+					39 01 00 00 00 00 02 8F 01
+				];
+
+				qcom,mdss-dsi-on-command = [
+					39 01 00 00 00 00 06 F0 55 AA 52 08 01
+					39 01 00 00 00 00 02 6F 01
+					39 01 00 00 00 00 04 C5 0B 0B 0B
+					39 01 00 00 00 00 05 FF AA 55 A5 80
+					39 01 00 00 00 00 02 6F 02
+					39 01 00 00 00 00 02 F5 10
+					39 01 00 00 00 00 02 6F 1B
+					39 01 00 00 00 00 02 F4 55
+					39 01 00 00 00 00 02 6F 18
+					39 01 00 00 00 00 02 F8 19
+					39 01 00 00 00 00 02 6F 0F
+					39 01 00 00 00 00 02 FC 00
+					39 01 00 00 00 00 05 2A 00 00 04 37
+					39 01 00 00 00 00 05 2B 00 00 09 5F
+					39 01 00 00 00 00 03 90 03 03
+					39 01 00 00 00 00 13 91 89 28 00 28 D2 00 02 86 04 3A 00 0A 02 AB 01 E9 10 F0
+					39 01 00 00 00 00 13 93 89 28 00 28 D2 00 02 25 03 B6 00 07 02 AB 02 8B 10 F0
+					39 01 00 00 00 00 13 95 89 28 00 28 D2 00 01 C3 02 FC 00 05 02 AB 03 D1 10 F0
+					39 01 00 00 00 00 02 03 00
+					39 01 00 00 00 00 02 8F 01
+					39 01 00 00 00 00 02 6F 06
+					39 01 00 00 00 00 02 F3 DC
+					39 01 00 00 00 00 02 26 00
+					39 01 00 00 00 00 02 35 00
+					39 01 00 00 00 00 05 3B 00 18 00 10
+					39 01 00 00 00 00 02 53 20
+					39 01 00 00 00 00 07 51 07 FF 07 FF 0F FF
+					39 01 00 00 00 00 02 5A 01
+					39 01 00 00 00 00 02 5F 00
+					39 01 00 00 00 00 02 9C 01
+					05 01 00 00 00 00 01 2C
+					39 01 00 00 00 00 02 2F 00
+
+					05 01 00 00 78 00 01 11
+					05 01 00 00 14 00 01 29
+				];
+
+				qcom,mdss-dsi-off-command = [
+					05 01 00 00 14 00 02 28 00
+					05 01 00 00 78 00 02 10 00];
+				qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+				qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+				qcom,mdss-dsi-timing-switch-command-state =
+					"dsi_lp_mode";
+				qcom,mdss-dsi-h-sync-pulse = <0>;
+				qcom,compression-mode = "dsc";
+				qcom,mdss-dsc-slice-height = <40>;
+				qcom,mdss-dsc-slice-width = <540>;
+				qcom,mdss-dsc-slice-per-pkt = <1>;
+				qcom,mdss-dsc-bit-per-component = <8>;
+				qcom,mdss-dsc-bit-per-pixel = <8>;
+				qcom,mdss-dsc-block-prediction-enable;
+			};
 		};
 	};
 };
diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi
index 65b22528..53de247a 100644
--- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi
+++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi
@@ -22,6 +22,7 @@
 		qcom,mdss-dsi-tx-eot-append;
 		qcom,adjust-timer-wakeup-ms = <1>;
 		qcom,panel-cphy-mode;
+		qcom,spr-pack-type = "pentile";
 
 		qcom,mdss-dsi-wr-mem-start = <0x2c>;
 		qcom,mdss-dsi-wr-mem-continue = <0x3c>;
@@ -87,6 +88,8 @@
 					39 01 00 00 00 00 05 FF AA 55 A5 82
 					39 01 00 00 00 00 02 6F 08
 					39 01 00 00 00 00 03 F3 CC 0C
+					39 01 00 00 00 00 06 F0 55 AA 52 08 01
+					39 01 00 00 00 00 05 B2 55 01 FF 03
 					05 01 00 00 78 00 01 11
 					05 01 00 00 14 00 01 29
 				];
diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi
index 0bab8128..d4647340 100644
--- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi
+++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi
@@ -10,6 +10,8 @@
 		qcom,mdss-dsi-border-color = <0>;
 		qcom,dsi-ctrl-num = <0>;
 		qcom,dsi-phy-num = <0>;
+		qcom,dsi-sec-ctrl-num = <1>;
+		qcom,dsi-sec-phy-num = <1>;
 		qcom,mdss-dsi-traffic-mode = "burst_mode";
 		qcom,mdss-dsi-bllp-eof-power-mode;
 		qcom,mdss-dsi-bllp-power-mode;
@@ -25,6 +27,7 @@
 
 		qcom,mdss-dsi-wr-mem-start = <0x2c>;
 		qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+		qcom,spr-pack-type = "pentile";
 		qcom,mdss-dsi-display-timings {
 			timing@0 {
 				cell-index = <0>;
@@ -84,6 +87,8 @@
 					39 01 00 00 00 00 02 9C 01
 					05 01 00 00 00 00 01 2C
 					39 01 00 00 00 00 02 2f 00
+					39 01 00 00 00 00 06 F0 55 AA 52 08 01
+					39 01 00 00 00 00 05 B2 55 01 FF 03
 					05 01 00 00 78 00 01 11
 					05 01 00 00 14 00 01 29
 				];
diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi
index 1a6143bc..bec6e766 100644
--- a/display/sun-sde-common.dtsi
+++ b/display/sun-sde-common.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: BSD-3-Clause
 /*
- * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -177,8 +177,8 @@
 		qcom,sde-has-dest-scaler;
 		qcom,sde-max-trusted-vm-displays = <1>;
 
-		qcom,sde-max-bw-low-kbps = <17000000>;
-		qcom,sde-max-bw-high-kbps = <27000000>;
+		qcom,sde-max-bw-low-kbps = <18900000>;
+		qcom,sde-max-bw-high-kbps = <28500000>;
 		qcom,sde-min-core-ib-kbps = <2500000>;
 		qcom,sde-min-llcc-ib-kbps = <0>;
 		qcom,sde-min-dram-ib-kbps = <800000>;
@@ -193,6 +193,23 @@
 		qcom,sde-dspp-demura-size = <0xe4>;
 		qcom,sde-dspp-demura-version = <0x00020000>;
 
+		qcom,sde-dspp-aiqe-off = <0x39000 0xffffffff 0x3a000 0xffffffff>;
+		qcom,sde-dspp-aiqe-version = <0x00010000>;
+		qcom,sde-dspp-aiqe-size = <0x3fc>;
+
+		qcom,sde-dspp-aiqe-dither-off = <0x39700 0xffffffff 0x3a700 0xffffffff>;
+		qcom,sde-dspp-aiqe-dither-version = <0x00010000>;
+		qcom,sde-dspp-aiqe-dither-size = <0x20>;
+
+		qcom,sde-dspp-aiqe-wrapper-off = <0x39780 0xffffffff 0x3a780 0xffffffff>;
+		qcom,sde-dspp-aiqe-wrapper-version = <0x00010000>;
+		qcom,sde-dspp-aiqe-wrapper-size = <0x1c>;
+
+		qcom,sde-aiqe-has-feature-mdnie;
+		qcom,sde-aiqe-has-feature-abc;
+		qcom,sde-aiqe-has-feature-ssrc;
+		qcom,sde-aiqe-has-feature-copr;
+
 		qcom,sde-lm-noise-off = <0x320>;
 		qcom,sde-lm-noise-version = <0x00010000>;
 
@@ -268,10 +285,10 @@
 				qcom,sde-fp16-unmult = <0x200 0x00010000>;
 				qcom,sde-fp16-gc = <0x200 0x00010000>;
 				qcom,sde-fp16-csc = <0x200 0x00010000>;
-				qcom,sde-ucsc-igc = <0x700 0x00010000>;
-				qcom,sde-ucsc-unmult = <0x700 0x00010000>;
-				qcom,sde-ucsc-gc = <0x700 0x00010000>;
-				qcom,sde-ucsc-csc = <0x700 0x00010000>;
+				qcom,sde-ucsc-igc = <0x700 0x00010001>;
+				qcom,sde-ucsc-unmult = <0x700 0x00010001>;
+				qcom,sde-ucsc-gc = <0x700 0x00010001>;
+				qcom,sde-ucsc-csc = <0x700 0x00010001>;
 				qcom,sde-ucsc-alpha-dither = <0x700 0x00010000>;
 			};
 
@@ -281,10 +298,10 @@
 				qcom,sde-fp16-unmult = <0x280 0x00010000>;
 				qcom,sde-fp16-gc = <0x280 0x00010000>;
 				qcom,sde-fp16-csc = <0x280 0x00010000>;
-				qcom,sde-ucsc-igc = <0x1700 0x00010000>;
-				qcom,sde-ucsc-unmult = <0x1700 0x00010000>;
-				qcom,sde-ucsc-gc = <0x1700 0x00010000>;
-				qcom,sde-ucsc-csc = <0x1700 0x00010000>;
+				qcom,sde-ucsc-igc = <0x1700 0x00010001>;
+				qcom,sde-ucsc-unmult = <0x1700 0x00010001>;
+				qcom,sde-ucsc-gc = <0x1700 0x00010001>;
+				qcom,sde-ucsc-csc = <0x1700 0x00010001>;
 				qcom,sde-ucsc-alpha-dither = <0x1700 0x00010000>;
 			};
 		};
@@ -297,10 +314,10 @@
 				qcom,sde-fp16-unmult = <0x200 0x00010000>;
 				qcom,sde-fp16-gc = <0x200 0x00010000>;
 				qcom,sde-fp16-csc = <0x200 0x00010000>;
-				qcom,sde-ucsc-igc = <0x700 0x00010000>;
-				qcom,sde-ucsc-unmult = <0x700 0x00010000>;
-				qcom,sde-ucsc-gc = <0x700 0x00010000>;
-				qcom,sde-ucsc-csc = <0x700 0x00010000>;
+				qcom,sde-ucsc-igc = <0x700 0x00010001>;
+				qcom,sde-ucsc-unmult = <0x700 0x00010001>;
+				qcom,sde-ucsc-gc = <0x700 0x00010001>;
+				qcom,sde-ucsc-csc = <0x700 0x00010001>;
 				qcom,sde-ucsc-alpha-dither = <0x700 0x00010000>;
 			};
 
@@ -310,24 +327,24 @@
 				qcom,sde-fp16-unmult = <0x200 0x00010000>;
 				qcom,sde-fp16-gc = <0x200 0x00010000>;
 				qcom,sde-fp16-csc = <0x200 0x00010000>;
-				qcom,sde-ucsc-igc = <0x1700 0x00010000>;
-				qcom,sde-ucsc-unmult = <0x1700 0x00010000>;
-				qcom,sde-ucsc-gc = <0x1700 0x00010000>;
-				qcom,sde-ucsc-csc = <0x1700 0x00010000>;
+				qcom,sde-ucsc-igc = <0x1700 0x00010001>;
+				qcom,sde-ucsc-unmult = <0x1700 0x00010001>;
+				qcom,sde-ucsc-gc = <0x1700 0x00010001>;
+				qcom,sde-ucsc-csc = <0x1700 0x00010001>;
 				qcom,sde-ucsc-alpha-dither = <0x1700 0x00010000>;
 			};
 		};
 
 		qcom,sde-dspp-blocks {
-			qcom,sde-dspp-igc = <0x1260 0x00040000>;
+			qcom,sde-dspp-igc = <0x1260 0x00050000>;
 			qcom,sde-dspp-hsic = <0x800 0x00010007>;
 			qcom,sde-dspp-memcolor = <0x880 0x00010007>;
 			qcom,sde-dspp-hist = <0x800 0x00010007>;
 			qcom,sde-dspp-sixzone = <0x900 0x00020000>;
 			qcom,sde-dspp-vlut = <0xa00 0x00010008>;
 			qcom,sde-dspp-gamut = <0x1000 0x00040003>;
-			qcom,sde-dspp-pcc = <0x1700 0x00040000>;
-			qcom,sde-dspp-gc = <0x17c0 0x00010008>;
+			qcom,sde-dspp-pcc = <0x1700 0x00060000>;
+			qcom,sde-dspp-gc = <0x17c0 0x00020000>;
 			qcom,sde-dspp-dither = <0x82c 0x00010007>;
 		};
 	};
diff --git a/display/sun-sde-display-cdp-kiwi-overlay.dts b/display/sun-sde-display-cdp-kiwi-overlay.dts
new file mode 100644
index 00000000..acfc23ea
--- /dev/null
+++ b/display/sun-sde-display-cdp-kiwi-overlay.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "sun-sde-display-cdp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Sun CDP Kiwi WLAN";
+	compatible = "qcom,sun-cdp", "qcom,sun", "qcom,cdp";
+	qcom,msm-id = <618 0x10000>, <618 0x20000>;
+	qcom,board-id = <0x20001 0>;
+};
diff --git a/display/sun-sde-display-cdp-kiwi-v8-overlay.dts b/display/sun-sde-display-cdp-kiwi-v8-overlay.dts
new file mode 100644
index 00000000..fba63430
--- /dev/null
+++ b/display/sun-sde-display-cdp-kiwi-v8-overlay.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "sun-sde-display-cdp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Sun CDP Kiwi WLAN V8 Power Grid";
+	compatible = "qcom,sun-cdp", "qcom,sun", "qcom,sunp-cdp", "qcom,sunp",
+			"qcom,cdp";
+	qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
+	qcom,board-id = <0x60001 0>;
+};
diff --git a/display/sun-sde-display-cdp-nfc-overlay.dts b/display/sun-sde-display-cdp-nfc-overlay.dts
new file mode 100644
index 00000000..f9aba3ab
--- /dev/null
+++ b/display/sun-sde-display-cdp-nfc-overlay.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "sun-sde-display-cdp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Sun CDP SN300 NFC";
+	compatible = "qcom,sun-cdp", "qcom,sun", "qcom,sunp-cdp", "qcom,sunp", "qcom,cdp";
+	qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
+	qcom,board-id = <0x40001 0>;
+};
diff --git a/display/sun-sde-display-cdp-overlay.dts b/display/sun-sde-display-cdp-overlay.dts
index ab2f2519..a3b29d3c 100644
--- a/display/sun-sde-display-cdp-overlay.dts
+++ b/display/sun-sde-display-cdp-overlay.dts
@@ -11,6 +11,6 @@
 / {
 	model = "Qualcomm Technologies, Inc. Sun CDP";
 	compatible = "qcom,sun-cdp", "qcom,sun", "qcom,cdp";
-	qcom,msm-id = <618 0x10000>, <618 0x20000>;
+	qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
 	qcom,board-id = <1 0>;
 };
diff --git a/display/sun-sde-display-cdp-v8-overlay.dts b/display/sun-sde-display-cdp-v8-overlay.dts
new file mode 100644
index 00000000..dee0d9e7
--- /dev/null
+++ b/display/sun-sde-display-cdp-v8-overlay.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "sun-sde-display-cdp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Sun CDP V8 Power Grid";
+	compatible = "qcom,sun-cdp", "qcom,sun", "qcom,sunp-cdp", "qcom,sunp",
+			"qcom,cdp";
+	qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
+	qcom,board-id = <0x50001 0>;
+};
diff --git a/display/sun-sde-display-cdp.dtsi b/display/sun-sde-display-cdp.dtsi
index 0e65dc00..7c979c54 100644
--- a/display/sun-sde-display-cdp.dtsi
+++ b/display/sun-sde-display-cdp.dtsi
@@ -43,22 +43,28 @@
 
 &dsi_nt37801_amoled_cmd {
 	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
 	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
 	qcom,mdss-dsi-bl-min-level = <10>;
 	qcom,mdss-dsi-bl-max-level = <4095>;
 	qcom,mdss-brightness-max-level = <8191>;
 	qcom,mdss-dsi-bl-inverted-dbv;
 	qcom,platform-reset-gpio = <&tlmm 98 0>;
+	qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
 };
 
 &dsi_nt37801_amoled_video {
 	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
 	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
 	qcom,mdss-dsi-bl-min-level = <10>;
 	qcom,mdss-dsi-bl-max-level = <4095>;
 	qcom,mdss-brightness-max-level = <8191>;
 	qcom,mdss-dsi-bl-inverted-dbv;
 	qcom,platform-reset-gpio = <&tlmm 98 0>;
+	qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
 };
 
 &dsi_vtdr6130_amoled_120hz_video {
@@ -174,6 +180,7 @@
 };
 
 &qupv3_se15_i2c {
+	status = "disabled";
 	st_fts@49 {
 		panel = <&dsi_nt37801_amoled_cmd
 			&dsi_nt37801_amoled_cmd_cphy
diff --git a/display/sun-sde-display-common.dtsi b/display/sun-sde-display-common.dtsi
index d0b187ab..23bce180 100644
--- a/display/sun-sde-display-common.dtsi
+++ b/display/sun-sde-display-common.dtsi
@@ -348,6 +348,7 @@
 
 &dsi_nt37801_amoled_cmd {
 	qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
+	qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1";
 
 	qcom,mdss-dsi-display-timings {
 		timing@0 {
@@ -356,11 +357,45 @@
 			qcom,display-topology = <2 2 1>;
 			qcom,default-topology-index = <0>;
 		};
+
+		timing@1 {
+			qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a
+						0b 0a 02 04 00 21 0f];
+			qcom,display-topology = <2 2 1>;
+			qcom,default-topology-index = <0>;
+		};
+	};
+};
+
+&dsi_nt37801_amoled_video_cphy {
+	qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
+
+	qcom,mdss-dsi-display-timings {
+		timing@0 {
+			qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 25 25 08
+				19 09 02 04 00 00 00];
+			qcom,display-topology = <2 2 1>;
+			qcom,default-topology-index = <0>;
+		};
+	};
+};
+
+&dsi_nt37801_amoled_cmd_cphy {
+	qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
+
+	qcom,mdss-dsi-display-timings {
+		timing@0 {
+			qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 23 22 08
+				19 08 02 04 00 00 00];
+			qcom,display-topology = <2 2 1>;
+			qcom,default-topology-index = <0>;
+		};
 	};
 };
 
 &dsi_nt37801_amoled_video {
 	qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
+	qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1";
 
 	qcom,mdss-dsi-display-timings {
 		timing@0 {
diff --git a/display/sun-sde-display-mtp-kiwi-overlay.dts b/display/sun-sde-display-mtp-kiwi-overlay.dts
new file mode 100644
index 00000000..6d755f25
--- /dev/null
+++ b/display/sun-sde-display-mtp-kiwi-overlay.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "sun-sde-display-mtp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Sun MTP Kiwi WLAN";
+	compatible = "qcom,sun-mtp", "qcom,sun", "qcom,mtp";
+	qcom,msm-id = <618 0x10000>, <618 0x20000>;
+	qcom,board-id = <0x20008 0>;
+};
diff --git a/display/sun-sde-display-mtp-kiwi-v8-overlay.dts b/display/sun-sde-display-mtp-kiwi-v8-overlay.dts
new file mode 100644
index 00000000..c354a996
--- /dev/null
+++ b/display/sun-sde-display-mtp-kiwi-v8-overlay.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "sun-sde-display-mtp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Sun MTP Kiwi WLAN V8 Power Grid";
+	compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp",
+			"qcom,mtp";
+	qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
+	qcom,board-id = <0x50008 0>;
+};
diff --git a/display/sun-sde-display-mtp-nfc-overlay.dts b/display/sun-sde-display-mtp-nfc-overlay.dts
new file mode 100644
index 00000000..544c30fe
--- /dev/null
+++ b/display/sun-sde-display-mtp-nfc-overlay.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "sun-sde-display-mtp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Sun MTP SN300 NFC";
+	compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp";
+	qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
+	qcom,board-id = <0x30008 0>;
+};
diff --git a/display/sun-sde-display-mtp-overlay.dts b/display/sun-sde-display-mtp-overlay.dts
index 9038f744..48ad6325 100644
--- a/display/sun-sde-display-mtp-overlay.dts
+++ b/display/sun-sde-display-mtp-overlay.dts
@@ -11,6 +11,6 @@
 / {
 	model = "Qualcomm Technologies, Inc. Sun MTP";
 	compatible = "qcom,sun-mtp", "qcom,sun", "qcom,mtp";
-	qcom,msm-id = <618 0x10000>, <618 0x20000>;
+	qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
 	qcom,board-id = <8 0>;
 };
diff --git a/display/sun-sde-display-mtp-v8-overlay.dts b/display/sun-sde-display-mtp-v8-overlay.dts
new file mode 100644
index 00000000..3cfae533
--- /dev/null
+++ b/display/sun-sde-display-mtp-v8-overlay.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "sun-sde-display-mtp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Sun MTP V8 Power Grid";
+	compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp",
+			"qcom,mtp";
+	qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
+	qcom,board-id = <0x40008 0>;
+};
diff --git a/display/sun-sde-display-qrd-sku1-overlay.dts b/display/sun-sde-display-qrd-sku1-overlay.dts
new file mode 100644
index 00000000..2479ab77
--- /dev/null
+++ b/display/sun-sde-display-qrd-sku1-overlay.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "sun-sde-display-qrd.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Sun QRD SKU1";
+	compatible = "qcom,sun-qrd", "qcom,sun", "qcom,sunp-qrd", "qcom,sunp",
+			"qcom,qrd";
+	qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
+	qcom,board-id = <0x1000B 0>;
+};
diff --git a/display/sun-sde-display-qrd-sku1-v8-overlay.dts b/display/sun-sde-display-qrd-sku1-v8-overlay.dts
new file mode 100644
index 00000000..4780320d
--- /dev/null
+++ b/display/sun-sde-display-qrd-sku1-v8-overlay.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "sun-sde-display-qrd.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Sun QRD SKU1 V8 Power Grid";
+	compatible = "qcom,sun-qrd", "qcom,sun", "qcom,sunp-qrd", "qcom,sunp",
+			"qcom,qrd";
+	qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
+	qcom,board-id = <0x3000B 0>;
+};
diff --git a/display/sun-sde-display-qrd-sku2-v8-overlay.dts b/display/sun-sde-display-qrd-sku2-v8-overlay.dts
new file mode 100644
index 00000000..0820a163
--- /dev/null
+++ b/display/sun-sde-display-qrd-sku2-v8-overlay.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "sun-sde-display-qrd.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Sun QRD SKU2 V8 Power Grid";
+	compatible = "qcom,sun-qrd", "qcom,sun", "qcom,sunp-qrd", "qcom,sunp",
+				"qcom,qrd";
+	qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
+	qcom,board-id = <0x2000B 0>;
+};
diff --git a/display/sun-sde-display-qrd.dtsi b/display/sun-sde-display-qrd.dtsi
new file mode 100644
index 00000000..65f8e0d2
--- /dev/null
+++ b/display/sun-sde-display-qrd.dtsi
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "sun-sde-display.dtsi"
+
+&dsi_nt37801_amoled_cmd {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <10>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,mdss-brightness-max-level = <8191>;
+	qcom,mdss-dsi-bl-inverted-dbv;
+	qcom,platform-reset-gpio = <&tlmm 98 0>;
+};
+
+&dsi_nt37801_amoled_cmd_cphy {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <10>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,mdss-brightness-max-level = <8191>;
+	qcom,mdss-dsi-bl-inverted-dbv;
+	qcom,platform-reset-gpio = <&tlmm 98 0>;
+};
+
+&dsi_nt37801_amoled_video {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <10>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,mdss-brightness-max-level = <8191>;
+	qcom,mdss-dsi-bl-inverted-dbv;
+	qcom,platform-reset-gpio = <&tlmm 98 0>;
+};
+
+&dsi_nt37801_amoled_video_cphy {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <10>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,mdss-brightness-max-level = <8191>;
+	qcom,mdss-dsi-bl-inverted-dbv;
+	qcom,platform-reset-gpio = <&tlmm 98 0>;
+};
+
+&sde_dsi {
+	qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd_cphy>;
+};
+
+&qupv3_se4_spi {
+	st_fts@0 {
+		panel = <&dsi_nt37801_amoled_cmd_cphy
+			&dsi_nt37801_amoled_video_cphy
+			&dsi_nt37801_amoled_cmd
+			&dsi_nt37801_amoled_video>;
+	};
+};
diff --git a/display/sun-sde-display-rcm-overlay.dts b/display/sun-sde-display-rcm-overlay.dts
new file mode 100644
index 00000000..4236e89b
--- /dev/null
+++ b/display/sun-sde-display-rcm-overlay.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "sun-sde-display-rcm.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Sun RCM";
+	compatible = "qcom,sun-rcm", "qcom,sun", "qcom,rcm";
+	qcom,msm-id = <618 0x10000>, <618 0x20000>;
+	qcom,board-id = <0x15 0>;
+};
diff --git a/display/sun-sde-display-rcm.dtsi b/display/sun-sde-display-rcm.dtsi
new file mode 100644
index 00000000..4566cd46
--- /dev/null
+++ b/display/sun-sde-display-rcm.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "sun-sde-display-cdp.dtsi"
diff --git a/display/sun-sde-display.dtsi b/display/sun-sde-display.dtsi
index 67eb583c..d48d6045 100644
--- a/display/sun-sde-display.dtsi
+++ b/display/sun-sde-display.dtsi
@@ -51,8 +51,8 @@
 &sde_dsi {
 	clocks = <&mdss_dsi_phy0 0>,
 		 <&mdss_dsi_phy0 1>,
-		 <&mdss_dsi_phy1 2>,
-		 <&mdss_dsi_phy1 3>,
+		 <&mdss_dsi_phy1 0>,
+		 <&mdss_dsi_phy1 1>,
 		 /*
 		  * Currently the dsi clock handles are under the dsi
 		  * controller DT node. As soon as the controller probe
@@ -80,8 +80,8 @@
 &sde_dsi1 {
 	clocks = <&mdss_dsi_phy0 0>,
 		 <&mdss_dsi_phy0 1>,
-		 <&mdss_dsi_phy1 2>,
-		 <&mdss_dsi_phy1 3>,
+		 <&mdss_dsi_phy1 0>,
+		 <&mdss_dsi_phy1 1>,
 		 /*
 		  * Currently the dsi clock handles are under the dsi
 		  * controller DT node. As soon as the controller probe
@@ -107,7 +107,7 @@
 };
 
 &mdss_mdp {
-	connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &sde_wb1 &sde_wb2>;
+	connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &sde_wb1 &sde_wb2 &sde_dp>;
 };
 
 &dsi_vtdr6130_amoled_cmd {
diff --git a/display/sun-sde.dts b/display/sun-sde.dts
index d55ab390..4b3a3f74 100644
--- a/display/sun-sde.dts
+++ b/display/sun-sde.dts
@@ -9,6 +9,6 @@
 #include "sun-sde.dtsi"
 
 / {
-	qcom,msm-id = <618 0x10000>;
+	qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
 	qcom,board-id = <15 0>;
 };
diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi
index 0a76d14e..18c83c8e 100644
--- a/display/sun-sde.dtsi
+++ b/display/sun-sde.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: BSD-3-Clause
 /*
- * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
@@ -13,10 +13,184 @@
 #include "sun-sde-common.dtsi"
 
 &soc {
+	ext_disp: qcom,msm-ext-disp {
+		compatible = "qcom,msm-ext-disp";
+
+		ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx {
+			compatible = "qcom,msm-ext-disp-audio-codec-rx";
+		};
+	};
+
+	qcom_msmhdcp: qcom,msm_hdcp {
+		compatible = "qcom,msm-hdcp";
+	};
+
+	sde_dp_pll: qcom,dp_pll@88eb000 {
+		compatible = "qcom,dp-pll-3nm-v1";
+		#clock-cells = <1>;
+	};
+
+	sde_dp: qcom,dp_display@af54000 {
+		cell-index = <0>;
+		compatible = "qcom,dp-display";
+
+		usb-phy = <&usb_qmp_dp_phy>;
+		qcom,ext-disp = <&ext_disp>;
+		usb-controller = <&usb0>;
+		qcom,altmode-dev = <&altmode 0>;
+		qcom,dp-aux-switch = <&wcd_usbss>;
+
+		reg =   <0xaf54000 0x104>,
+			<0xaf54200 0x0c0>,
+			<0xaf55000 0x770>,
+			<0xaf56000 0x09c>,
+			<0x88ebc00 0x200>,
+			<0x88eb400 0x200>,
+			<0x88eb800 0x200>,
+			<0x88eb000 0x200>,
+			<0x88e8000 0x020>,
+			<0xaee1000 0x034>,
+			<0xaf57000 0x09c>,
+			<0xaf09000 0x014>;
+		reg-names = "dp_ahb", "dp_aux", "dp_link",
+			"dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",
+			"dp_pll", "usb3_dp_com", "hdcp_physical",
+			"dp_p1", "gdsc";
+
+		interrupt-parent = <&mdss_mdp>;
+		interrupts = <12 0>;
+
+		#clock-cells = <1>;
+		clocks =  <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
+			<&rpmhcc RPMH_CXO_CLK>,
+			<&tcsrcc TCSR_USB3_CLKREF_EN>,
+			<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
+			<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
+			<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
+			<&sde_dp_pll 0>,
+			<&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
+			<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+			<&sde_dp_pll 1>,
+			<&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>,
+			<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
+			<&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
+		clock-names = "core_aux_clk", "rpmh_cxo_clk", "core_usb_ref_clk_src",
+			"core_usb_pipe_clk", "link_clk", "link_clk_src", "link_parent",
+			"link_iface_clk", "pixel_clk_rcg", "pixel_parent",
+			"pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk";
+
+		qcom,dp-pll = <&sde_dp_pll>;
+		qcom,phy-version = <0x800>;
+		qcom,aux-cfg0-settings = [20 00];
+		qcom,aux-cfg1-settings = [24 13];
+		qcom,aux-cfg2-settings = [28 A4];
+		qcom,aux-cfg3-settings = [2c 00];
+		qcom,aux-cfg4-settings = [30 0a];
+		qcom,aux-cfg5-settings = [34 26];
+		qcom,aux-cfg6-settings = [38 0a];
+		qcom,aux-cfg7-settings = [3c 03];
+		qcom,aux-cfg8-settings = [40 b7];
+		qcom,aux-cfg9-settings = [44 03];
+
+		qcom,max-pclk-frequency-khz = <675000>;
+
+		qcom,widebus-enable;
+		qcom,mst-enable;
+		qcom,dsc-feature-enable;
+		qcom,fec-feature-enable;
+		qcom,dsc-continuous-pps;
+
+		qcom,qos-cpu-mask = <0xf>;
+		qcom,qos-cpu-latency-us = <300>;
+
+		vdda-1p2-supply = <&L3G>;
+		vdda-0p9-supply = <&L2D>;
+		vdda_usb-0p9-supply = <&L2D>;
+		vdd_mx-supply = <&VDD_MXA_LEVEL>;
+		dp_phy_gdsc-supply = <&gcc_usb3_phy_gdsc>;
+
+		qcom,hbr-rbr-voltage-swing = <0x27 0x2f 0x36 0x3f>,
+					<0x31 0x3e 0x3f 0xff>,
+					<0x36 0x3f 0xff 0xff>,
+					<0x3f 0xff 0xff 0xff>;
+		qcom,hbr-rbr-pre-emphasis = <0x20 0x2d 0x34 0x3a>,
+					<0x20 0x2e 0x35 0xff>,
+					<0x20 0x2e 0xff 0xff>,
+					<0x22 0xff 0xff 0xff>;
+
+		qcom,hbr2-3-voltage-swing = <0x22 0x32 0x36 0x3a>,
+					<0x29 0x39 0x3f 0xff>,
+					<0x30 0x3f 0xff 0xff>,
+					<0x3f 0xff 0xff 0xff>;
+		qcom,hbr2-3-pre-emphasis = <0x20 0x2c 0x35 0x3b>,
+					<0x22 0x2e 0x36 0xff>,
+					<0x22 0x31 0xff 0xff>,
+					<0x24 0xff 0xff 0xff>;
+
+		qcom,ctrl-supply-entries {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			qcom,ctrl-supply-entry@0 {
+				reg = <0>;
+				qcom,supply-name = "vdda-1p2";
+				qcom,supply-min-voltage = <1200000>;
+				qcom,supply-max-voltage = <1200000>;
+				qcom,supply-enable-load = <30000>;
+				qcom,supply-disable-load = <0>;
+			};
+		};
+
+		qcom,phy-supply-entries {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			qcom,phy-supply-entry@0 {
+				reg = <0>;
+				qcom,supply-name = "vdda-0p9";
+				qcom,supply-min-voltage = <912000>;
+				qcom,supply-max-voltage = <912000>;
+				qcom,supply-enable-load = <114000>;
+				qcom,supply-disable-load = <0>;
+			};
+
+			qcom,phy-supply-entry@1 {
+				reg = <1>;
+				qcom,supply-name = "vdda_usb-0p9";
+				qcom,supply-min-voltage = <880000>;
+				qcom,supply-max-voltage = <880000>;
+				qcom,supply-enable-load = <2500>;
+				qcom,supply-disable-load = <0>;
+			};
+		};
+
+		qcom,pll-supply-entries {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			qcom,pll-supply-entry@0 {
+				reg = <0>;
+				qcom,supply-name = "vdd_mx";
+				qcom,supply-min-voltage =
+						<RPMH_REGULATOR_LEVEL_TURBO>;
+				qcom,supply-max-voltage =
+						<RPMH_REGULATOR_LEVEL_MAX>;
+				qcom,supply-enable-load = <0>;
+				qcom,supply-disable-load = <0>;
+			};
+		};
+	};
+
+	smmu_sde_iommu_region_partition: smmu_sde_iommu_region_partition {
+		iommu-addresses = <&smmu_sde_unsec 0x0 0x00060000>,
+				  <&smmu_sde_unsec 0xd5500000 0x02b00000>,
+				  <&smmu_sde_sec 0x0 0x00020000>;
+	};
+
 	smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
 		compatible = "qcom,smmu_sde_unsec";
 		iommus = <&apps_smmu 0x800 0x2>;
-		qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
+		memory-region = <&smmu_sde_iommu_region_partition>;
 		qcom,iommu-faults = "non-fatal";
 		qcom,iommu-earlymap; /* for cont-splash */
 		dma-coherent;
@@ -25,7 +199,7 @@
 	smmu_sde_sec: qcom,smmu_sde_sec_cb {
 		compatible = "qcom,smmu_sde_sec";
 		iommus = <&apps_smmu 0x801 0x0>;
-		qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
+		memory-region = <&smmu_sde_iommu_region_partition>;
 		qcom,iommu-faults = "non-fatal";
 		qcom,iommu-vmid = <0xa>;
 	};
@@ -63,7 +237,7 @@
 	qcom,sde-has-idle-pc;
 
 	qcom,sde-ib-bw-vote = <2500000 0 800000>;
-	qcom,sde-dspp-ltm-version = <0x00010002>;
+	qcom,sde-dspp-ltm-version = <0x00010003>;
 	/* offsets are based off dspp 0, 1, 2, and 3 */
 	qcom,sde-dspp-ltm-off = <0x15300 0x14300 0x13300 0x12300>;